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| author | Jan Beulich <jbeulich@suse.com> | 2013-10-11 09:30:31 +0200 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2013-10-11 09:30:31 +0200 |
| commit | 4b46e7be783df641b2889e514e85643febd378c2 (patch) | |
| tree | 27b7a86cad841a488a8b6f1aaea3fc695efcd859 /xen/arch/x86/domain.c | |
| parent | d06a0d715ec1423b6c42141ab1b0ff69a3effb56 (diff) | |
| download | xen-4b46e7be783df641b2889e514e85643febd378c2.tar.gz xen-4b46e7be783df641b2889e514e85643febd378c2.tar.bz2 xen-4b46e7be783df641b2889e514e85643febd378c2.zip | |
x86: use {rd,wr}{fs,gs}base when available
... as being intended to be faster than MSR reads/writes.
In the case of emulate_privileged_op() also use these in favor of the
cached (but possibly stale) addresses from arch.pv_vcpu. This allows
entirely removing the code that was the subject of XSA-67.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
Acked-by: Keir Fraser <keir@xen.org>
Diffstat (limited to 'xen/arch/x86/domain.c')
| -rw-r--r-- | xen/arch/x86/domain.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 52b7a37fec..b67fcb8f78 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1092,7 +1092,7 @@ static void load_segments(struct vcpu *n) { /* This can only be non-zero if selector is NULL. */ if ( n->arch.pv_vcpu.fs_base ) - wrmsrl(MSR_FS_BASE, n->arch.pv_vcpu.fs_base); + wrfsbase(n->arch.pv_vcpu.fs_base); /* Most kernels have non-zero GS base, so don't bother testing. */ /* (This is also a serialising instruction, avoiding AMD erratum #88.) */ @@ -1100,7 +1100,7 @@ static void load_segments(struct vcpu *n) /* This can only be non-zero if selector is NULL. */ if ( n->arch.pv_vcpu.gs_base_user ) - wrmsrl(MSR_GS_BASE, n->arch.pv_vcpu.gs_base_user); + wrgsbase(n->arch.pv_vcpu.gs_base_user); /* If in kernel mode then switch the GS bases around. */ if ( (n->arch.flags & TF_kernel_mode) ) |