From 4b46e7be783df641b2889e514e85643febd378c2 Mon Sep 17 00:00:00 2001 From: Jan Beulich Date: Fri, 11 Oct 2013 09:30:31 +0200 Subject: x86: use {rd,wr}{fs,gs}base when available ... as being intended to be faster than MSR reads/writes. In the case of emulate_privileged_op() also use these in favor of the cached (but possibly stale) addresses from arch.pv_vcpu. This allows entirely removing the code that was the subject of XSA-67. Signed-off-by: Jan Beulich Reviewed-by: Andrew Cooper Acked-by: Keir Fraser --- xen/arch/x86/domain.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'xen/arch/x86/domain.c') diff --git a/xen/arch/x86/domain.c b/xen/arch/x86/domain.c index 52b7a37fec..b67fcb8f78 100644 --- a/xen/arch/x86/domain.c +++ b/xen/arch/x86/domain.c @@ -1092,7 +1092,7 @@ static void load_segments(struct vcpu *n) { /* This can only be non-zero if selector is NULL. */ if ( n->arch.pv_vcpu.fs_base ) - wrmsrl(MSR_FS_BASE, n->arch.pv_vcpu.fs_base); + wrfsbase(n->arch.pv_vcpu.fs_base); /* Most kernels have non-zero GS base, so don't bother testing. */ /* (This is also a serialising instruction, avoiding AMD erratum #88.) */ @@ -1100,7 +1100,7 @@ static void load_segments(struct vcpu *n) /* This can only be non-zero if selector is NULL. */ if ( n->arch.pv_vcpu.gs_base_user ) - wrmsrl(MSR_GS_BASE, n->arch.pv_vcpu.gs_base_user); + wrgsbase(n->arch.pv_vcpu.gs_base_user); /* If in kernel mode then switch the GS bases around. */ if ( (n->arch.flags & TF_kernel_mode) ) -- cgit v1.2.3