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* ipq806x: 5.15: replace stmmac pcs fix with upstream versionChristian Marangi2022-10-113-83/+261
| | | | | | Replace stmmac pcs fix with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: 5.15: replace gcc fixes with upstream versionChristian Marangi2022-10-1113-272/+1761
| | | | | | Replace gcc patch fixes with upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: 5.15: replace lcc patch with upstream versionChristian Marangi2022-10-114-59/+294
| | | | | | Replace lcc patch with proposed upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: 5.15: replace dtsi patches with upstream versionChristian Marangi2022-10-1148-1179/+1618
| | | | | | | | | Reorganize dtsi patches with upstream version and drop dtsi in 5.15 files. Also add an additional upstream patch for hwspinlock support. Refresh all the dts with needed changes. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: 5.15: remove PCI_DOMAINS patch not needed anymoreChristian Marangi2022-10-111-29/+0
| | | | | | | This doesn't cause any panic anymore and no regression are observed with ath10k. Remove this additional patch. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: 5.15: remove qcom adm Documentation patchChristian Marangi2022-10-111-71/+0
| | | | | | | Remove qcom adm Documentation patch that is not needed for the target. Probably a leftover when the adm bus was added, now merged upstream. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq806x: split files dir to 5.10 and 5.15Christian Marangi2022-10-1164-0/+8525
| | | | | | | In preparation for a cleanup of 5.15 patches copy the files dir to 5.10 and 5.15 kernel version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* lantiq: dts: vr9: Add missing properties to the CPU port on the switchMartin Blumenstingl2022-10-101-0/+6
| | | | | | | | | | | | | | | | The CPU port should define the phy-mode and and a PHY phandle or fixed-link to indicate how the CPU port is connected to the SoC's Ethernet controller. On xRX200 this is all internal connection, so use phy-mode = "internal" along with a fixed-link that matches the definition inside &eth0. Linux 6.0 shows a warning since upstream commit e09e9873152e3f ("net: dsa: make phylink-related OF properties mandatory on DSA and CPU ports"). when these properties are missing. Adding the properties before OpenWrt is updated to Linux 6.0 is harmless. Suggested-by: Martin Schiller <ms@dev.tdt.de> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
* ramips: use lzma-loader on JCG Q20Du Cai2022-10-091-0/+1
| | | | | | Fixes the LZMA uncompression issue on JCG Q20. Signed-off-by: Du Cai <caidu@smail.nju.edu.cn>
* ipq40xx: convert to DSA and enable Sony NCP-HG100/CellularINAGAKI Hiroshi2022-10-094-19/+23
| | | | | | | This patch converts networking on Sony NCP-HG100/Cellular to DSA and re-enables support for the device. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ipq40xx: ZTE MF289F: convert to DSADirk Buchwalder2022-10-093-22/+19
| | | | | | | | | Convert ZTE MF289F device to DSA, re-order network ports to match the labels on the case and re-enable the device. Signed-off-by: Dirk Buchwalder <buchwalder@posteo.de> Reviewed-by: Robert Marko <robimarko@gmail.com> Reviewed-by: Lech Perczak <lech.perczak@gmail.com>
* kernel: bump 5.15 to 5.15.72John Audia2022-10-0932-290/+151
| | | | | | | | | | | | | | | | | Removed upstreamed: generic/pending-5.15/722-net-mt7531-only-do-PLL-once-after-the-reset.patch[1] bcm53xx/patches-5.15/082-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[2] All other patches automatically rebased Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 Run-tested: bcm2711/RPi4B, mt7622/RT3200, mvebu/cortexa72 (RB5009UG+S+IN) 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=5de02ab84aeca765da0e4d8e999af35325ac67c2 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.72&id=ab5c5787ab5ecdc4a7ea20b4ef542579e1beb49d Signed-off-by: John Audia <therealgraysky@proton.me>
* kernel: bump 5.10 to 5.10.147John Audia2022-10-0917-108/+37
| | | | | | | | | | | Removed upstreamed: bcm53xx/patches-5.10/083-v6.0-clk-iproc-Do-not-rely-on-node-name-for-correct-PLL-s.patch[1] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.10.147&id=a8e6cde5062fb2aff81f86cc0770591714bee545 Signed-off-by: John Audia <therealgraysky@proton.me>
* mediatek: filogic: set correct PWM clock and clean thermal zoneDaniel Golle2022-10-093-18/+18
| | | | | | | | | | | | * set correct clocks for PWM to work. * MT7986 PWM does have the 26MHz-clock-select, set that in patch * drop useless 'passive' trip point in thermal zone * extend pwm-fan to have 3 active operating points * set reasonable trip points in thermal zone * invert pwm-fan operating points and set shorter period to allow less noisy operation of the PWM fan of the BPi-R3. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* realtek: cleanup rtl83{8x,9x}_enable_learning/floodINAGAKI Hiroshi2022-10-082-44/+22
| | | | | | | | | | | | | In *_enable_learning() only address learning should be configured, so remove enabling forwarding. Forwarding is configured by the respective *_enable_flood() functions. Clean up both functions for RTL838x and RTL839x, and fix the comment on the number of entries. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash RTL838x, RTL839x changes] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: swap *_phylink_mac_link_down() contentsINAGAKI Hiroshi2022-10-081-7/+8
| | | | | | | | | Fix the (accidentally?) swapped contents of rtl83xx_phylink_mac_link_down() and rtl93xx_phylink_mac_link_down(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix place of fdb/mdb info messagesINAGAKI Hiroshi2022-10-081-2/+2
| | | | | | | | | Those messages should be printed when entry was found (idx >= 0). Move them to the right place to not print invalid entry indices. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amden commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: add missing of.h include in phy driverINAGAKI Hiroshi2022-10-081-0/+1
| | | | | | | | of.h is required for of_property_read_u32(). Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: fix use of uninitialized sds_modeINAGAKI Hiroshi2022-10-081-2/+1
| | | | | | | | | The initial state of sds_mode in rtl9300_force_sds_mode() is null and it will be configured in switch-case. So print message after it. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: use MIPS fw_init_cmdline()INAGAKI Hiroshi2022-10-081-20/+2
| | | | | | | | | Use the generic function of MIPS in Linux Kernel instead of open coding our own initialisation. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [amend commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net>
* realtek: update SMP-related calls in prom_init()INAGAKI Hiroshi2022-10-081-6/+2
| | | | | | | | | | | | | | | | | | | | The availabibity of probing CPC depends on CONFIG_MIPS_CPC symbol and it will be checked in arch/mips/include/asm/mips-cpc.h. RTL9310 selects this symbol, so the family check is redudant. Furthermore, mips_cm_probe() is already called from setup_arch() in mips/kernel/setup.c before prom_init(), and as such is not required. Also move mips_cpc_probe() to run just before registering SMP ops. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com> [squash SMP change commits, reword commit message] Signed-off-by: Sander Vanheule <sander@svanheule.net> --- This patch only really has an impact on the rtl931x subtarget, which has no devices. Noboby is currently set up to test these patches either, but the end result is closer to MIPS_GENERIC, so I do not expect it to cause issues.
* realtek: separate lock of RTL8231 from phy driverINAGAKI Hiroshi2022-10-081-9/+10
| | | | | | | RTL8231 and ethernet phys are not on the same bus, so separate the lock to each own to cut off the unnecessary dependency. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
* ath79: fix model name of Extreme Networks WS-AP3805iTom Herbers2022-10-081-1/+1
| | | | | | | Everywhere else the device is referred to as WS-AP3805i, only the model name wrongly only said AP3805i. Signed-off-by: Tom Herbers <mail@tomherbers.de>
* mediatek: filogic: enable thermal, I2C and PWM of the BPi-R3Daniel Golle2022-10-072-1/+32
| | | | | | | Setup thermal zone, select pins and enabled drivers for I2C (on 26-pin GPIO bank) and PWM (1x fan and 1x GPIO bank). Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* mediatek: filogic: add support for hw i2c, pwm and thermalDaniel Golle2022-10-078-1/+524
| | | | | | | Add support for hardware I2C and PWM units found in the Filogic SoCs as well as the CPU thermal support. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* kernel: refresh backport-5.15 patchesDaniel Golle2022-10-0710-20/+0
| | | | | | | Refresh patches, removing unwanted git metadata from some backported commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* ath79: increase max tx ring buffer for ag71xxRobert Meijer2022-10-061-1/+1
| | | | | | | | | | | | This allows the user to specify a larger tx ring buffer size via ethtool. Having symmetrical ring buffer sizes increases throughput on high bandwidth (1 gbps tested) network connections. The default value is not changed so the same behaviour is saved. Signed-off-by: Robert Meijer <robert.s.meijer@gmail.com> [ improve title, commit description and wrap to 80 columns ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq40xx: pakedge_wr-1: convert to DSATomasz Maciej Nowak2022-10-053-2/+39
| | | | | | | | | Convert pakedge_wr-1 device to DSA and enable it. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Reviewed-by: Robert Marko <robimarko@gmail.com>i [ improve commit description ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* ipq40xx: luma_wrtq-329acn: convert to DSATomasz Maciej Nowak2022-10-053-18/+41
| | | | | | | | | Convert luma_wrtq-329acn device to DSA and enable it. Signed-off-by: Tomasz Maciej Nowak <tmn505@gmail.com> Reviewed-by: Robert Marko <robimarko@gmail.com> [ improve commit description ] Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
* qoriq: fix typo in FEATURESStijn Tintel2022-10-051-1/+1
| | | | | | | There is no root-part FEATURE. Reported-by: Karl Palsson <karlp@etactica.com> Signed-off-by: Stijn Tintel <stijn@linux-ipv6.be>
* kernel: fix possible mtd NULL pointer dereferenceRafał Miłecki2022-10-047-4/+65
| | | | | Fixes: 1a9ee367343ed ("kernel: backport mtd dynamic partition patch") Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
* ramips: fix switch setup for ASUS RT-AX53UMatthias Schiffer2022-10-032-5/+1
| | | | | | | The device has only 1 WAN + 3 LAN ports. Remove "lan4" interface corresponding to the non-existing port. Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
* ipq40xx: glinet-b1300: fix LAN and WAN MAC address assigmentsPetr Štetiar2022-10-031-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When testing the DSA changes with 5.15.60 kernel, I've noticed, that the MAC addresses are not properly configured, there is single MAC being used for LAN and WAN interfaces: eth0: 94:83:c4:XX:YY:4a (MAC on sticker) lan1@eth0: 94:83:c4:XX:YY:4a lan2@eth0: 94:83:c4:XX:YY:4a wan@eth0: 94:83:c4:XX:YY:4a wlan0: 94:83:c4:XX:YY:4a wlan1: 94:83:c4:XX:YY:4b The same config, prior to the DSA conversion: lan/eth0: 94:83:c4:XX:YY:4a (MAC on sticker) wan/eth1: 94:83:c4:XX:YY:4b wlan0: 94:83:c4:XX:YY:4a wlan1: 94:83:c4:XX:YY:4b Settings in ART partition: root@OpenWrt:/# hexdump -C /dev/mtd7 | grep '94 83' 00000000 94 83 c4 XX YY 4a 94 83 c4 0e YY 4b ff ff ff ff |.....J.....K....| 00001000 20 2f 8d 8c 01 01 94 83 c4 XX YY 4a 00 00 20 00 | /.........J.. .| 00005000 20 2f 5a 3a 01 01 94 83 c4 XX YY 4b 00 00 20 00 | /Z:.......K.. .| So let's fix it by keeping same MAC address assigment as was done before DSA conversion and while at it, define `label-mac-device` as well. Signed-off-by: Petr Štetiar <ynezz@true.cz>
* rockchip: switch to 5.15 kernelTomas Lara2022-10-021-2/+1
| | | | | | Run tested: NanoPI R4S Signed-off-by: Tomas Lara <tl849670@gmail.com>
* kernel: add missing config symbols for 5.15Tomas Lara2022-10-021-0/+4
| | | | | | Add missing symbols, needed when rockchip kernel 5.15 is compile with ALL_KMODS=y Signed-off-by: Tomas Lara <tl849670@gmail.com>
* rockchip: refresh kernel 5.15 configTomas Lara2022-10-021-10/+13
| | | | | | Refreshed using make kernel oldconfig CONFIG TARGET=rockchip . Signed-off-by: Tomas Lara <tl849670@gmail.com>
* ipq40xx: disable boards not converted to DSADavid Bauer2022-10-023-43/+86
| | | | Signed-off-by: David Bauer <mail@david-bauer.net>
* ipq40xx: remove non-converted network configsRobert Marko2022-10-021-96/+0
| | | | | | | Remove networking configs for non DSA converted boards in ipq40xx. Currently, they are just causing clutter. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: ipqess: enable threaded NAPIRobert Marko2022-10-021-2/+4
| | | | | | | | Enable threaded NAPI by default in IPQESS driver as it significantly improves network perfromance, in my testing about 100+ Mbps in WAN-LAN routing. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: Meraki MR33: convert MAC addresses to nvmemLech Perczak2022-10-023-9/+19
| | | | | | | | This fixes assigning random MAC to br-lan interface upon boot. While at that, rename at24@50 node to eeprom@50, to align with upstream device tree style. Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
* ipq40xx: convert some boards to DSARobert Marko2022-10-0232-99/+754
| | | | | | | | | | | | Convert IPQ40xx boards to DSA setup. Signed-off-by: Leon M. George <leon@georgemail.eu> Signed-off-by: Lech Perczak <lech.perczak@gmail.com> Signed-off-by: Nick Hainke <vincent@systemli.org> Signed-off-by: ChunAm See <z1250747241@gmail.com> Signed-off-by: Jeff Kletsky <git-commits@allycomm.com> Signed-off-by: Andrew Sim <andrewsimz@gmail.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: qca8k: introduce proper PSGMII calibrationSerhii Serhieiev2022-10-022-12/+331
| | | | | | | | | | | | Serhii and others have experienced PSGMII link degradation up to point that it actually does not pass packets at all or packets arrive as zeros. This usually happened after a couple of hot reboots. Serhii has managed to track it down to PSGMII calibration not being done properly and has fixed it, so all of the code is Serhii-s work. Signed-off-by: Serhii Serhieiev <adron@mstnt.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: qca807x: drop kernel version checksRobert Marko2022-10-021-16/+0
| | | | | | | Since kernel 5.4 has been droppped from IPQ40xx, there is no need to keep the version checks for kernels older than 5.10. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: qca807x: add suspend and resume opsSerhii Serhieiev2022-10-021-0/+4
| | | | | | | | | | Currently, suspend and resume ops are not present, this means that if user disables a DSA interface that the PHY-s remain alive and the link is up. Fix it by using generic PHY suspend and resume ops. Signed-off-by: Serhii Serhieiev <adron@mstnt.com> Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: sxtsq-5-ac: correct TCSR ESS typeRobert Marko2022-10-021-1/+1
| | | | | | | SXTsq 5 ac uses RGMII on the port 5 and not PSGMII, so correct the TCSR interface type property. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: enable ethernet and DSA driver comboRobert Marko2022-10-022-0/+16
| | | | | | | | Select the Ethernet driver, DSA tag driver and the DSA driver itself to be built in the kernel config. They automatically pull in switchdev and phylink. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: add DSA switch driverRobert Marko2022-10-0212-1190/+678
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Qualcomm IPQ40xx SoC-s have a variant of QCA8337N switch built-in. It shares most of the stuff with its external counterpart, however it is modified for the SoC. Namely, it doesn't have second CPU port (Port 6), so it has 6 ports instead of 7. It also has no built-in PHY-s but rather requires external PSGMII based companion PHY-s (QCA8072 and QCA8075) for which it first needs to carry out calibration before using them. PSGMII has a SoC built-in PHY that is used to connect to the PHY-s which unfortunately requires some magic values as the datasheet doesnt document the bits that are being set or the register at all. Since its built-in it is MMIO like other peripherals and doesn't have its own MDIO bus but depends on the SoC provided one. CPU connection is at Port 0 and it uses some kind of a internal connection and no traditional RGMII/SGMII. It also doesn't use in-band tagging like other qca8k switches so a shinfo based tagger is used. This is based on the current OpenWrt qca8k version that has been imported from generic target. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: import qca8k from genericRobert Marko2022-10-022-0/+2500
| | | | | | | | This is just importing the qca8k driver from the generic target. It will be used as the based for IPQ40xx version, this is just to be able to see the diff. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: add PSGMII PHY mode defineRobert Marko2022-10-022-0/+122
| | | | | | | | | | | PSGMII is a Qualcomm specific mode similar to QSGMII but it has 5 SGMII lines instead of 4 in QSGMII. This just adds the support for the PHY layer to be able to identify the mode for further use. It is required for the DSA driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
* ipq40xx: add IPQESS ethernet driverRobert Marko2022-10-029-1/+2296
| | | | | | | | | IPQESS is the EDMA replacement driver for the IPQ40xx SoC built-in ethernet controller. Unlike EDMA it is Phylink based and doesnt touch PHY-s directly. Signed-off-by: Robert Marko <robert.marko@sartura.hr>
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