diff options
Diffstat (limited to 'package/boot/uboot-mediatek')
99 files changed, 22980 insertions, 1441 deletions
diff --git a/package/boot/uboot-mediatek/Makefile b/package/boot/uboot-mediatek/Makefile index 37af42e6642..61aaf4de257 100644 --- a/package/boot/uboot-mediatek/Makefile +++ b/package/boot/uboot-mediatek/Makefile @@ -1,17 +1,87 @@ include $(TOPDIR)/rules.mk include $(INCLUDE_DIR)/kernel.mk -PKG_VERSION:=2021.04 -PKG_HASH:=0d438b1bb5cceb57a18ea2de4a0d51f7be5b05b98717df05938636e0aadfe11a -PKG_BUILD_DEPENDS:=arm-trusted-firmware-tools/host +PKG_VERSION:=2024.01 +PKG_HASH:=b99611f1ed237bf3541bdc8434b68c96a6e05967061f992443cb30aabebef5b3 +PKG_BUILD_DEPENDS:=!(TARGET_ramips||TARGET_mediatek_mt7623):arm-trusted-firmware-tools/host + +UBOOT_USE_INTREE_DTC:=1 include $(INCLUDE_DIR)/u-boot.mk include $(INCLUDE_DIR)/package.mk include $(INCLUDE_DIR)/host-build.mk +MT7621_LOWLEVEL_PRELOADER_URL:=https://raw.githubusercontent.com/mtk-openwrt/mt7621-lowlevel-preloader/a03b07c60bf1ba4add9b671d32caa102fe948180/ + +define Download/mt7621-stage-sram + FILE:=mt7621_stage_sram.bin + URL:=$(MT7621_LOWLEVEL_PRELOADER_URL) + HASH:=1dda68aa089f0ff262e01539b990dea478952e9fb68bcc0a8cd6f76f0135c62e +endef + +define Download/mt7621-stage-sram-noprint + FILE:=mt7621_stage_sram_noprint.bin + URL:=$(MT7621_LOWLEVEL_PRELOADER_URL) + HASH:=8ee419275144fc298e9444d413d98e965a55d283152a74ea6a1f8de79eb516b6 +endef + +ifdef CONFIG_TARGET_ramips_mt7621 +ifdef CONFIG_DEBUG +$(eval $(call Download,mt7621-stage-sram)) +else +$(eval $(call Download,mt7621-stage-sram-noprint)) +endif +endif + define U-Boot/Default BUILD_TARGET:=mediatek UBOOT_IMAGE:=u-boot-mtk.bin + HIDDEN:=1 +endef + +define U-Boot/mt7620_rfb + NAME:=MT7620 Reference Board + UBOOT_CONFIG:=mt7620_rfb + BUILD_DEVICES:=ralink_mt7620a-evb + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt7620 + UBOOT_IMAGE:=u-boot-with-spl.bin +endef + +define U-Boot/mt7620_mt7530_rfb + NAME:=MT7620+MT7530 Reference Board + UBOOT_CONFIG:=mt7620_mt7530_rfb + BUILD_DEVICES:=ralink_mt7620a-mt7530-evb + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt7620 + UBOOT_IMAGE:=u-boot-with-spl.bin +endef + +define U-Boot/mt7621_rfb + NAME:=MT7621 Reference Board + UBOOT_CONFIG:=mt7621_rfb + BUILD_DEVICES:=mediatek_mt7621-eval-board + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt7621 + UBOOT_IMAGE:=u-boot-mt7621.bin +endef + +define U-Boot/mt7621_nand_rfb + NAME:=MT7621 Reference Board (NAND) + UBOOT_CONFIG:=mt7621_nand_rfb + BUILD_DEVICES:=mediatek_mt7621-eval-board + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt7621 + UBOOT_IMAGE:=u-boot-mt7621.bin +endef + +define U-Boot/mt7621_zbtlink_zbt-wg3526-16m + NAME:=Zbtlink ZBT-WG3526-16m + UBOOT_CONFIG:=mt7621_zbtlink_zbt-wg3526-16m + BUILD_DEVICES:=zbtlink_zbt-wg3526-16m + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt7621 + UBOOT_IMAGE:=u-boot-mt7621.bin endef define U-Boot/mt7622_rfb1 @@ -27,9 +97,9 @@ define U-Boot/mt7622_linksys_e8450 BUILD_DEVICES:=linksys_e8450-ubi BUILD_SUBTARGET:=mt7622 UBOOT_IMAGE:=u-boot.fip - BL2_BOOTDEV:=snand + BL2_BOOTDEV:=snand-ubi BL2_DDRBLOB:=1 - DEPENDS:=+trusted-firmware-a-mt7622-snand-1ddr + DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-1ddr endef define U-Boot/mt7622_bananapi_bpi-r64-emmc @@ -60,25 +130,50 @@ define U-Boot/mt7622_bananapi_bpi-r64-snand BUILD_DEVICES:=bananapi_bpi-r64 BUILD_SUBTARGET:=mt7622 UBOOT_IMAGE:=u-boot.fip - BL2_BOOTDEV:=snand + BL2_BOOTDEV:=snand-ubi BL2_DDRBLOB:=2 - DEPENDS:=+trusted-firmware-a-mt7622-snand-2ddr + DEPENDS:=+trusted-firmware-a-mt7622-snand-ubi-2ddr endef -define U-Boot/mt7622_ubnt_unifi-6-lr +define U-Boot/mt7622_ubnt_unifi-6-lr-v1 NAME:=Ubiquiti UniFi 6 LR - UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr - BUILD_DEVICES:=ubnt_unifi-6-lr-ubootmod + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v1 + BUILD_DEVICES:=ubnt_unifi-6-lr-v1-ubootmod BUILD_SUBTARGET:=mt7622 UBOOT_IMAGE:=u-boot.fip BL2_BOOTDEV:=nor BL2_DDRBLOB:=2 DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7622_ubnt_unifi-6-lr-v2 + NAME:=Ubiquiti UniFi 6 LR v2 + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v2 + BUILD_DEVICES:=ubnt_unifi-6-lr-v2-ubootmod + BUILD_SUBTARGET:=mt7622 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_DDRBLOB:=2 + DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7622_ubnt_unifi-6-lr-v3 + NAME:=Ubiquiti UniFi 6 LR v3 + UBOOT_CONFIG:=mt7622_ubnt_unifi-6-lr-v3 + BUILD_DEVICES:=ubnt_unifi-6-lr-v3-ubootmod + BUILD_SUBTARGET:=mt7622 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_DDRBLOB:=2 + DEPENDS:=+trusted-firmware-a-mt7622-nor-2ddr + FIP_COMPRESS:=1 endef define U-Boot/mt7623a_unielec_u7623 NAME:=UniElec U7623 (mt7623) - BUILD_DEVICES:=unielec_u7623-emmc unielec_u7623-02-emmc-512m-legacy + BUILD_DEVICES:=unielec_u7623-02 BUILD_SUBTARGET:=mt7623 UBOOT_CONFIG:=mt7623a_unielec_u7623_02 endef @@ -91,6 +186,24 @@ define U-Boot/mt7623n_bpir2 UBOOT_CONFIG:=mt7623n_bpir2 endef +define U-Boot/mt7628_rfb + NAME:=MT7628 Reference Board + BUILD_DEVICES:=mediatek_mt7628an-eval-board + BUILD_TARGET:=ramips + BUILD_SUBTARGET:=mt76x8 + UBOOT_CONFIG:=mt7628_rfb + UBOOT_IMAGE:=u-boot-with-spl.bin +endef + +define U-Boot/mt7628_ravpower_rp-wd009 + NAME:=RAVPower RP-WD009 + BUILD_TARGET:=ramips + BUILD_DEVICES:=ravpower_rp-wd009 + BUILD_SUBTARGET:=mt76x8 + UBOOT_CONFIG:=ravpower-rp-wd009-ram + UBOOT_IMAGE:=u-boot.bin +endef + define U-Boot/mt7629_rfb NAME:=MT7629 Reference Board BUILD_SUBTARGET:=mt7629 @@ -98,38 +211,513 @@ define U-Boot/mt7629_rfb UBOOT_CONFIG:=mt7629_rfb endef +define U-Boot/mt7981_cmcc_rax3000m-emmc + NAME:=CMCC RAX3000M + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=cmcc_rax3000m + UBOOT_CONFIG:=mt7981_cmcc_rax3000m-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr4 +endef + +define U-Boot/mt7981_cmcc_rax3000m-nand + NAME:=CMCC RAX3000M + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=cmcc_rax3000m + UBOOT_CONFIG:=mt7981_cmcc_rax3000m-nand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr4 +endef + +define U-Boot/mt7981_h3c_magic-nx30-pro + NAME:=H3C Magic NX30 Pro + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=h3c_magic-nx30-pro + UBOOT_CONFIG:=mt7981_h3c_magic-nx30-pro + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7981_jcg_q30-pro + NAME:=JCG Q30 PRO + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=jcg_q30-pro + UBOOT_CONFIG:=mt7981_jcg_q30-pro + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7981_rfb-spim-nand + NAME:=MT7981 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7981-rfb + UBOOT_CONFIG:=mt7981_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7981_rfb-emmc + NAME:=MT7981 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7981-rfb + UBOOT_CONFIG:=mt7981_emmc_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-emmc-ddr3 +endef + +define U-Boot/mt7981_rfb-nor + NAME:=MT7981 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7981-rfb + UBOOT_CONFIG:=mt7981_nor_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-nor-ddr3 +endef + +define U-Boot/mt7981_rfb-sd + NAME:=MT7981 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7981-rfb + UBOOT_CONFIG:=mt7981_sd_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-sdmmc-ddr3 +endef + +define U-Boot/mt7981_rfb-snfi + NAME:=MT7981 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7981-rfb + UBOOT_CONFIG:=mt7981_snfi_nand_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=snand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-snand-ddr3 +endef + +define U-Boot/mt7981_qihoo_360t7 + NAME:=Qihoo 360T7 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=qihoo_360t7 + UBOOT_CONFIG:=mt7981_qihoo-360t7 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7981_xiaomi_mi-router-ax3000t + NAME:=Xiaomi Router AX3000T + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=xiaomi_mi-router-ax3000t-ubootmod + UBOOT_CONFIG:=mt7981_xiaomi_mi-router-ax3000t + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7981_xiaomi_mi-router-wr30u + NAME:=Xiaomi Router WR30U + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=xiaomi_mi-router-wr30u-ubootmod + UBOOT_CONFIG:=mt7981_xiaomi_mi-router-wr30u + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7981 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7981-spim-nand-ddr3 +endef + +define U-Boot/mt7986_rfb + NAME:=MT7986 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7986-rfb + UBOOT_CONFIG:=mt7986_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-sdmmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-emmc + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-sdmmc + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-sd + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-sdmmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-snand + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-snand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-ubi + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-nor + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3 + UBOOT_CONFIG:=mt7986a_bpi-r3-nor + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-nor-ddr4 + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-mini-emmc + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3-mini + UBOOT_CONFIG:=mt7986a_bpi-r3-mini-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + +define U-Boot/mt7986_bananapi_bpi-r3-mini-snand + NAME:=BananaPi BPi-R3 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r3-mini + UBOOT_CONFIG:=mt7986a_bpi-r3-mini-snand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-ubi + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ubi-ddr4 +endef + +define U-Boot/mt7986_glinet_gl-mt6000 + NAME:=GL.iNet GL-MT6000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=glinet_gl-mt6000 + UBOOT_CONFIG:=mt7986a_glinet_gl-mt6000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + +define U-Boot/mt7986_jdcloud_re-cp-03 + NAME:=JDCloud RE-CP-03 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=jdcloud_re-cp-03 + UBOOT_CONFIG:=mt7986a_jdcloud_re-cp-03 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-emmc-ddr4 +endef + +define U-Boot/mt7986_tplink_tl-xdr4288 + NAME:=TP-LINK TL-XDR4288 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=tplink_tl-xdr4288 + UBOOT_CONFIG:=mt7986_tplink_tl-xdr4288 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr3 +endef + +define U-Boot/mt7986_tplink_tl-xdr6086 + NAME:=TP-LINK TL-XDR6086 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=tplink_tl-xdr6086 + UBOOT_CONFIG:=mt7986_tplink_tl-xdr6086 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr3 +endef + +define U-Boot/mt7986_tplink_tl-xdr6088 + NAME:=TP-LINK TL-XDR6088 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=tplink_tl-xdr6088 + UBOOT_CONFIG:=mt7986_tplink_tl-xdr6088 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr3 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr3 +endef + +define U-Boot/mt7986_xiaomi_redmi-router-ax6000 + NAME:=Xiaomi Redmi AX6000 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=xiaomi_redmi-router-ax6000-ubootmod + UBOOT_CONFIG:=mt7986_xiaomi_redmi-ax6000 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-ddr4 +endef + +define U-Boot/mt7986_zyxel_ex5601-t0 + NAME:=Zyxel EX5601-T0 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=zyxel_ex5601-t0-ubootmod + UBOOT_CONFIG:=mt7986_zyxel_ex5601-t0 + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-4k + BL2_SOC:=mt7986 + BL2_DDRTYPE:=ddr4 + DEPENDS:=+trusted-firmware-a-mt7986-spim-nand-4k-ddr4 +endef + +define U-Boot/mt7988_bananapi_bpi-r4-emmc + NAME:=BananaPi BPi-R4 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4 + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-emmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb +endef + +define U-Boot/mt7988_bananapi_bpi-r4-sdmmc + NAME:=BananaPi BPi-R4 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4 + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-sdmmc + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb +endef + +define U-Boot/mt7988_bananapi_bpi-r4-snand + NAME:=BananaPi BPi-R4 + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=bananapi_bpi-r4 + UBOOT_CONFIG:=mt7988a_bananapi_bpi-r4-snand + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand-ubi + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-ubi-comb +endef + +define U-Boot/mt7988_rfb-spim-nand + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=spim-nand + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-spim-nand-comb +endef + +define U-Boot/mt7988_rfb-snand + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=snand + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-snand-comb +endef + +define U-Boot/mt7988_rfb-nor + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=nor + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-nor-comb + FIP_COMPRESS:=1 +endef + +define U-Boot/mt7988_rfb-emmc + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb + UBOOT_CONFIG:=mt7988_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=emmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-emmc-comb +endef + +define U-Boot/mt7988_rfb-sd + NAME:=MT7988 Reference Board + BUILD_SUBTARGET:=filogic + BUILD_DEVICES:=mediatek_mt7988a-rfb + UBOOT_CONFIG:=mt7988_sd_rfb + UBOOT_IMAGE:=u-boot.fip + BL2_BOOTDEV:=sdmmc + BL2_SOC:=mt7988 + BL2_DDRTYPE:=comb + DEPENDS:=+trusted-firmware-a-mt7988-sdmmc-comb +endef + UBOOT_TARGETS := \ + mt7620_mt7530_rfb \ + mt7620_rfb \ + mt7621_nand_rfb \ + mt7621_rfb \ + mt7621_zbtlink_zbt-wg3526-16m \ mt7622_bananapi_bpi-r64-emmc \ mt7622_bananapi_bpi-r64-sdmmc \ mt7622_bananapi_bpi-r64-snand \ mt7622_linksys_e8450 \ mt7622_rfb1 \ - mt7622_ubnt_unifi-6-lr \ + mt7622_ubnt_unifi-6-lr-v1 \ + mt7622_ubnt_unifi-6-lr-v2 \ + mt7622_ubnt_unifi-6-lr-v3 \ mt7623n_bpir2 \ mt7623a_unielec_u7623 \ - mt7629_rfb + mt7628_rfb \ + mt7628_ravpower_rp-wd009 \ + mt7629_rfb \ + mt7981_cmcc_rax3000m-emmc \ + mt7981_cmcc_rax3000m-nand \ + mt7981_h3c_magic-nx30-pro \ + mt7981_jcg_q30-pro \ + mt7981_rfb-spim-nand \ + mt7981_rfb-emmc \ + mt7981_rfb-nor \ + mt7981_rfb-sd \ + mt7981_rfb-snfi \ + mt7981_qihoo_360t7 \ + mt7981_xiaomi_mi-router-ax3000t \ + mt7981_xiaomi_mi-router-wr30u \ + mt7986_bananapi_bpi-r3-emmc \ + mt7986_bananapi_bpi-r3-sdmmc \ + mt7986_bananapi_bpi-r3-snand \ + mt7986_bananapi_bpi-r3-nor \ + mt7986_bananapi_bpi-r3-mini-emmc \ + mt7986_bananapi_bpi-r3-mini-snand \ + mt7986_glinet_gl-mt6000 \ + mt7986_jdcloud_re-cp-03 \ + mt7986_tplink_tl-xdr4288 \ + mt7986_tplink_tl-xdr6086 \ + mt7986_tplink_tl-xdr6088 \ + mt7986_xiaomi_redmi-router-ax6000 \ + mt7986_zyxel_ex5601-t0 \ + mt7986_rfb \ + mt7988_bananapi_bpi-r4-emmc \ + mt7988_bananapi_bpi-r4-sdmmc \ + mt7988_bananapi_bpi-r4-snand \ + mt7988_rfb-spim-nand \ + mt7988_rfb-snand \ + mt7988_rfb-nor \ + mt7988_rfb-emmc \ + mt7988_rfb-sd +ifdef CONFIG_TARGET_mediatek UBOOT_MAKE_FLAGS += $(UBOOT_IMAGE:.fip=.bin) - -Build/Exports:=$(Host/Exports) +endif define Build/fip-image + $(if $(FIP_COMPRESS),\ + xz -f -e -k -9 -C crc32 $(STAGING_DIR_IMAGE)/$(if $(BL2_SOC),$(BL2_SOC),$(BUILD_SUBTARGET))-$(BL2_BOOTDEV)-$(if $(BL2_DDRTYPE),$(BL2_DDRTYPE)-)$(if $(BL2_DDRBLOB),$(BL2_DDRBLOB)ddr-)bl31.bin ;\ + xz -f -e -k -9 -C crc32 $(PKG_BUILD_DIR)/u-boot.bin \ + ) $(STAGING_DIR_HOST)/bin/fiptool create \ - --soc-fw $(STAGING_DIR_IMAGE)/$(BUILD_SUBTARGET)-$(BL2_BOOTDEV)-$(BL2_DDRBLOB)ddr-bl31.bin \ - --nt-fw $(PKG_BUILD_DIR)/u-boot.bin \ + --soc-fw $(STAGING_DIR_IMAGE)/$(if $(BL2_SOC),$(BL2_SOC),$(BUILD_SUBTARGET))-$(BL2_BOOTDEV)-$(if $(BL2_DDRTYPE),$(BL2_DDRTYPE)-)$(if $(BL2_DDRBLOB),$(BL2_DDRBLOB)ddr-)bl31.bin$(if $(FIP_COMPRESS),.xz) \ + --nt-fw $(PKG_BUILD_DIR)/u-boot.bin$(if $(FIP_COMPRESS),.xz) \ $(PKG_BUILD_DIR)/u-boot.fip endef +ifdef CONFIG_TARGET_ramips_mt7621 +define Build/Prepare + $(call Build/Prepare/Default) +ifdef CONFIG_DEBUG + $(CP) $(DL_DIR)/mt7621_stage_sram.bin $(PKG_BUILD_DIR)/ +else + $(CP) $(DL_DIR)/mt7621_stage_sram_noprint.bin $(PKG_BUILD_DIR)/mt7621_stage_sram.bin +endif +endef +endif + +define Build/Configure + $(call Build/Configure/U-Boot) + sed -i 's/CONFIG_TOOLS_LIBCRYPTO=y/# CONFIG_TOOLS_LIBCRYPTO is not set/' $(PKG_BUILD_DIR)/.config +endef + define Build/Compile $(call Build/Compile/U-Boot) -ifeq ($(UBOOT_IMAGE),u-boot.fip)) +ifeq ($(UBOOT_IMAGE),u-boot.fip) $(call Build/fip-image) endif endef # don't stage files to bindir, let target/linux/mediatek/image/*.mk do that +ifdef CONFIG_TARGET_mediatek define Package/u-boot/install endef +endif define Build/InstallDev $(INSTALL_DIR) $(STAGING_DIR_IMAGE) diff --git a/package/boot/uboot-mediatek/patches/000-mtk-01-Revert-clk-Add-debugging-for-return-values.patch b/package/boot/uboot-mediatek/patches/000-mtk-01-Revert-clk-Add-debugging-for-return-values.patch deleted file mode 100644 index c398ae4ab7c..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-01-Revert-clk-Add-debugging-for-return-values.patch +++ /dev/null @@ -1,69 +0,0 @@ -From 5efb7855a9d33ac897d6e2a7117e4e3d35d433a5 Mon Sep 17 00:00:00 2001 -From: Daniel Golle <daniel@makrotopia.org> -Date: Thu, 11 Mar 2021 10:28:53 +0000 -Subject: [PATCH 01/21] Revert "clk: Add debugging for return values" - -This reverts commit 5c5992cb90cf9ca4d51e38d9a95a13c293904df5. ---- - drivers/clk/clk-uclass.c | 16 +++++----------- - 1 file changed, 5 insertions(+), 11 deletions(-) - ---- a/drivers/clk/clk-uclass.c -+++ b/drivers/clk/clk-uclass.c -@@ -84,7 +84,7 @@ static int clk_get_by_index_tail(int ret - if (ret) { - debug("%s: uclass_get_device_by_of_offset failed: err=%d\n", - __func__, ret); -- return log_msg_ret("get", ret); -+ return ret; - } - - clk->dev = dev_clk; -@@ -97,15 +97,14 @@ static int clk_get_by_index_tail(int ret - ret = clk_of_xlate_default(clk, args); - if (ret) { - debug("of_xlate() failed: %d\n", ret); -- return log_msg_ret("xlate", ret); -+ return ret; - } - - return clk_request(dev_clk, clk); - err: - debug("%s: Node '%s', property '%s', failed to request CLK index %d: %d\n", - __func__, ofnode_get_name(node), list_name, index, ret); -- -- return log_msg_ret("prop", ret); -+ return ret; - } - - static int clk_get_by_indexed_prop(struct udevice *dev, const char *prop_name, -@@ -124,7 +123,7 @@ static int clk_get_by_indexed_prop(struc - if (ret) { - debug("%s: fdtdec_parse_phandle_with_args failed: err=%d\n", - __func__, ret); -- return log_ret(ret); -+ return ret; - } - - -@@ -472,7 +471,6 @@ int clk_free(struct clk *clk) - ulong clk_get_rate(struct clk *clk) - { - const struct clk_ops *ops; -- int ret; - - debug("%s(clk=%p)\n", __func__, clk); - if (!clk_valid(clk)) -@@ -482,11 +480,7 @@ ulong clk_get_rate(struct clk *clk) - if (!ops->get_rate) - return -ENOSYS; - -- ret = ops->get_rate(clk); -- if (ret) -- return log_ret(ret); -- -- return 0; -+ return ops->get_rate(clk); - } - - struct clk *clk_get_parent(struct clk *clk) diff --git a/package/boot/uboot-mediatek/patches/000-mtk-03-pinctrl-mediatek-fix-wrong-assignment-in-mtk_get_pin.patch b/package/boot/uboot-mediatek/patches/000-mtk-03-pinctrl-mediatek-fix-wrong-assignment-in-mtk_get_pin.patch deleted file mode 100644 index 3aa6b6105f2..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-03-pinctrl-mediatek-fix-wrong-assignment-in-mtk_get_pin.patch +++ /dev/null @@ -1,25 +0,0 @@ -From 6f18e581a7e98db3675b4c111701263647b20781 Mon Sep 17 00:00:00 2001 -From: Sam Shih <sam.shih@mediatek.com> -Date: Thu, 17 Dec 2020 19:29:56 +0800 -Subject: [PATCH 03/21] pinctrl: mediatek: fix wrong assignment in - mtk_get_pin_name - -This is a bug fix for mtk pinctrl common part. Appearently pins should be -used instead of grps in mtk_get_pin_name(). - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -219,7 +219,7 @@ static const char *mtk_get_pin_name(stru - { - struct mtk_pinctrl_priv *priv = dev_get_priv(dev); - -- if (!priv->soc->grps[selector].name) -+ if (!priv->soc->pins[selector].name) - return mtk_pinctrl_dummy_name; - - return priv->soc->pins[selector].name; diff --git a/package/boot/uboot-mediatek/patches/000-mtk-04-pinctrl-mediatek-add-get_pin_muxing-ops-for-mediatek.patch b/package/boot/uboot-mediatek/patches/000-mtk-04-pinctrl-mediatek-add-get_pin_muxing-ops-for-mediatek.patch deleted file mode 100644 index 89b51f7e819..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-04-pinctrl-mediatek-add-get_pin_muxing-ops-for-mediatek.patch +++ /dev/null @@ -1,43 +0,0 @@ -From ca73da39ff0c9f599f75d7ccac0196030aa946b9 Mon Sep 17 00:00:00 2001 -From: Sam Shih <sam.shih@mediatek.com> -Date: Thu, 17 Dec 2020 19:32:48 +0800 -Subject: [PATCH 04/21] pinctrl: mediatek: add get_pin_muxing ops for mediatek - pinctrl - -This patch add get_pin_muxing support for mediatek pinctrl drivers - -Signed-off-by: Sam Shih <sam.shih@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 14 ++++++++++++++ - 1 file changed, 14 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -232,6 +232,19 @@ static int mtk_get_pins_count(struct ude - return priv->soc->npins; - } - -+static int mtk_get_pin_muxing(struct udevice *dev, -+ unsigned int selector, -+ char *buf, int size) -+{ -+ int val, err; -+ err = mtk_hw_get_value(dev, selector, PINCTRL_PIN_REG_MODE, &val); -+ if (err) -+ return err; -+ -+ snprintf(buf, size, "Aux Func.%d", val); -+ return 0; -+} -+ - static const char *mtk_get_group_name(struct udevice *dev, - unsigned int selector) - { -@@ -512,6 +525,7 @@ static int mtk_pinconf_group_set(struct - const struct pinctrl_ops mtk_pinctrl_ops = { - .get_pins_count = mtk_get_pins_count, - .get_pin_name = mtk_get_pin_name, -+ .get_pin_muxing = mtk_get_pin_muxing, - .get_groups_count = mtk_get_groups_count, - .get_group_name = mtk_get_group_name, - .get_functions_count = mtk_get_functions_count, diff --git a/package/boot/uboot-mediatek/patches/000-mtk-05-pinctrl-mediatek-do-not-probe-gpio-driver-if-not-ena.patch b/package/boot/uboot-mediatek/patches/000-mtk-05-pinctrl-mediatek-do-not-probe-gpio-driver-if-not-ena.patch deleted file mode 100644 index 7a98e888430..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-05-pinctrl-mediatek-do-not-probe-gpio-driver-if-not-ena.patch +++ /dev/null @@ -1,58 +0,0 @@ -From d3fbbef13853a695cdea75a980a3d6bd150a68c1 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Mon, 11 Jan 2021 10:17:15 +0800 -Subject: [PATCH 05/21] pinctrl: mediatek: do not probe gpio driver if not - enabled - -The mtk pinctrl driver is a combination driver with support for both -pinctrl and gpio. When this driver is used in SPL, gpio support may not be -enabled, and this will result in a compilation error. - -To fix this, macros are added to make sure gpio related code will only be -compiled when gpio support is enabled. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 12 ++++++++---- - 1 file changed, 8 insertions(+), 4 deletions(-) - ---- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c -@@ -540,6 +540,8 @@ const struct pinctrl_ops mtk_pinctrl_ops - .set_state = pinctrl_generic_set_state, - }; - -+#if CONFIG_IS_ENABLED(DM_GPIO) || \ -+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) - static int mtk_gpio_get(struct udevice *dev, unsigned int off) - { - int val, err; -@@ -647,12 +649,13 @@ static int mtk_gpiochip_register(struct - - return 0; - } -+#endif - - int mtk_pinctrl_common_probe(struct udevice *dev, - struct mtk_pinctrl_soc *soc) - { - struct mtk_pinctrl_priv *priv = dev_get_priv(dev); -- int ret; -+ int ret = 0; - - priv->base = dev_read_addr_ptr(dev); - if (!priv->base) -@@ -660,9 +663,10 @@ int mtk_pinctrl_common_probe(struct udev - - priv->soc = soc; - -+#if CONFIG_IS_ENABLED(DM_GPIO) || \ -+ (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_GPIO_SUPPORT)) - ret = mtk_gpiochip_register(dev); -- if (ret) -- return ret; -+#endif - -- return 0; -+ return ret; - } diff --git a/package/boot/uboot-mediatek/patches/000-mtk-06-pinctrl-mt7629-add-jtag-function-and-pin-group.patch b/package/boot/uboot-mediatek/patches/000-mtk-06-pinctrl-mt7629-add-jtag-function-and-pin-group.patch deleted file mode 100644 index f4cc1eb69d3..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-06-pinctrl-mt7629-add-jtag-function-and-pin-group.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 1c6d07abf7fc79bf3950dc9ac56e3b566c334d3d Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 13 Jan 2021 16:29:23 +0800 -Subject: [PATCH 06/21] pinctrl: mt7629: add jtag function and pin group - -The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin -group to the pinctrl driver. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/pinctrl/mediatek/pinctrl-mt7629.c | 7 +++++++ - 1 file changed, 7 insertions(+) - ---- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c -+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c -@@ -201,6 +201,10 @@ static int mt7629_wf2g_led_funcs[] = { 1 - static int mt7629_wf5g_led_pins[] = { 18, }; - static int mt7629_wf5g_led_funcs[] = { 1, }; - -+/* LED for EPHY used as JTAG */ -+static int mt7629_ephy_leds_jtag_pins[] = { 12, 13, 14, 15, 16, }; -+static int mt7629_ephy_leds_jtag_funcs[] = { 7, 7, 7, 7, 7, }; -+ - /* Watchdog */ - static int mt7629_watchdog_pins[] = { 11, }; - static int mt7629_watchdog_funcs[] = { 1, }; -@@ -297,6 +301,7 @@ static const struct mtk_group_desc mt762 - PINCTRL_PIN_GROUP("ephy_led2", mt7629_ephy_led2), - PINCTRL_PIN_GROUP("ephy_led3", mt7629_ephy_led3), - PINCTRL_PIN_GROUP("ephy_led4", mt7629_ephy_led4), -+ PINCTRL_PIN_GROUP("ephy_leds_jtag", mt7629_ephy_leds_jtag), - PINCTRL_PIN_GROUP("wf2g_led", mt7629_wf2g_led), - PINCTRL_PIN_GROUP("wf5g_led", mt7629_wf5g_led), - PINCTRL_PIN_GROUP("watchdog", mt7629_watchdog), -@@ -364,6 +369,7 @@ static const char *const mt7629_uart_gro - static const char *const mt7629_wdt_groups[] = { "watchdog", }; - static const char *const mt7629_wifi_groups[] = { "wf0_5g", "wf0_2g", }; - static const char *const mt7629_flash_groups[] = { "snfi", "spi_nor" }; -+static const char *const mt7629_jtag_groups[] = { "ephy_leds_jtag" }; - - static const struct mtk_function_desc mt7629_functions[] = { - {"eth", mt7629_ethernet_groups, ARRAY_SIZE(mt7629_ethernet_groups)}, -@@ -376,6 +382,7 @@ static const struct mtk_function_desc mt - {"watchdog", mt7629_wdt_groups, ARRAY_SIZE(mt7629_wdt_groups)}, - {"wifi", mt7629_wifi_groups, ARRAY_SIZE(mt7629_wifi_groups)}, - {"flash", mt7629_flash_groups, ARRAY_SIZE(mt7629_flash_groups)}, -+ {"jtag", mt7629_jtag_groups, ARRAY_SIZE(mt7629_jtag_groups)}, - }; - - static struct mtk_pinctrl_soc mt7629_data = { diff --git a/package/boot/uboot-mediatek/patches/000-mtk-07-configs-mt7622-use-ARMv8-Generic-Timer-instead-of-mt.patch b/package/boot/uboot-mediatek/patches/000-mtk-07-configs-mt7622-use-ARMv8-Generic-Timer-instead-of-mt.patch deleted file mode 100644 index 060c9aadbf7..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-07-configs-mt7622-use-ARMv8-Generic-Timer-instead-of-mt.patch +++ /dev/null @@ -1,25 +0,0 @@ -From c47a5b927787a463eff8f67339d91e60fe0381c4 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Tue, 2 Mar 2021 15:02:50 +0800 -Subject: [PATCH 07/21] configs: mt7622: use ARMv8 Generic Timer instead of - mtk_timer - -It's better to use the generic timer which is correctly initialized by -the ATF. The generic timer has higher resolution than the mtk_timer. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - configs/mt7622_rfb_defconfig | 2 -- - 1 file changed, 2 deletions(-) - ---- a/configs/mt7622_rfb_defconfig -+++ b/configs/mt7622_rfb_defconfig -@@ -51,8 +51,6 @@ CONFIG_SPI=y - CONFIG_DM_SPI=y - CONFIG_MTK_SNOR=y - CONFIG_SYSRESET_WATCHDOG=y --CONFIG_TIMER=y --CONFIG_MTK_TIMER=y - CONFIG_WDT_MTK=y - CONFIG_LZO=y - CONFIG_HEXDUMP=y diff --git a/package/boot/uboot-mediatek/patches/000-mtk-08-dts-mt7629-enable-JTAG-pins-by-default.patch b/package/boot/uboot-mediatek/patches/000-mtk-08-dts-mt7629-enable-JTAG-pins-by-default.patch deleted file mode 100644 index f9f783ef375..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-08-dts-mt7629-enable-JTAG-pins-by-default.patch +++ /dev/null @@ -1,50 +0,0 @@ -From 4bee3f9e285007ccf77ca9916fff3d93fc4d8a80 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Tue, 2 Mar 2021 15:43:27 +0800 -Subject: [PATCH 08/21] dts: mt7629: enable JTAG pins by default - -The EPHY LEDs belongs to the built-in FE switch of MT7629, which is barely -used. These LED pins on reference boards are used as JTAG socket. So it's -a good idea to change the default state to JTAG, and this will make it -convenience for debugging. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - arch/arm/dts/mt7629-rfb.dts | 10 ++++++++++ - arch/arm/dts/mt7629.dtsi | 6 ++++++ - 2 files changed, 16 insertions(+) - ---- a/arch/arm/dts/mt7629-rfb.dts -+++ b/arch/arm/dts/mt7629-rfb.dts -@@ -36,6 +36,16 @@ - }; - - &pinctrl { -+ state_default: pinmux_conf { -+ u-boot,dm-pre-reloc; -+ -+ mux { -+ function = "jtag"; -+ groups = "ephy_leds_jtag"; -+ u-boot,dm-pre-reloc; -+ }; -+ }; -+ - snfi_pins: snfi-pins { - mux { - function = "flash"; ---- a/arch/arm/dts/mt7629.dtsi -+++ b/arch/arm/dts/mt7629.dtsi -@@ -152,6 +152,12 @@ - compatible = "mediatek,mt7629-pinctrl"; - reg = <0x10217000 0x8000>; - -+ pinctrl-names = "default"; -+ pinctrl-0 = <&state_default>; -+ -+ state_default: pinmux_conf { -+ }; -+ - gpio: gpio-controller { - gpio-controller; - #gpio-cells = <2>; diff --git a/package/boot/uboot-mediatek/patches/000-mtk-09-board-mediatek-add-more-network-configurations.patch b/package/boot/uboot-mediatek/patches/000-mtk-09-board-mediatek-add-more-network-configurations.patch deleted file mode 100644 index 56a40ca0e12..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-09-board-mediatek-add-more-network-configurations.patch +++ /dev/null @@ -1,44 +0,0 @@ -From f3f320af7078a8c5647d870a31c1d3695dacd7cf Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Tue, 2 Mar 2021 15:47:45 +0800 -Subject: [PATCH 09/21] board: mediatek: add more network configurations - -Make the network configurations uniform for mediatek boards - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - include/configs/mt7622.h | 3 ++- - include/configs/mt7623.h | 1 + - include/configs/mt7629.h | 1 + - 3 files changed, 4 insertions(+), 1 deletion(-) - ---- a/include/configs/mt7622.h -+++ b/include/configs/mt7622.h -@@ -36,6 +36,7 @@ - - /* Ethernet */ - #define CONFIG_IPADDR 192.168.1.1 --#define CONFIG_SERVERIP 192.168.1.3 -+#define CONFIG_SERVERIP 192.168.1.2 -+#define CONFIG_NETMASK 255.255.255.0 - - #endif ---- a/include/configs/mt7623.h -+++ b/include/configs/mt7623.h -@@ -54,6 +54,7 @@ - /* Ethernet */ - #define CONFIG_IPADDR 192.168.1.1 - #define CONFIG_SERVERIP 192.168.1.2 -+#define CONFIG_NETMASK 255.255.255.0 - - #ifdef CONFIG_DISTRO_DEFAULTS - ---- a/include/configs/mt7629.h -+++ b/include/configs/mt7629.h -@@ -52,5 +52,6 @@ - /* Ethernet */ - #define CONFIG_IPADDR 192.168.1.1 - #define CONFIG_SERVERIP 192.168.1.2 -+#define CONFIG_NETMASK 255.255.255.0 - - #endif diff --git a/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch b/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch deleted file mode 100644 index c568ab99e1a..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-10-mmc-mtk-sd-increase-the-minimum-bus-frequency.patch +++ /dev/null @@ -1,38 +0,0 @@ -From ed880b7572e1135e3bd8382d4670a375f7d9c91b Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Tue, 2 Mar 2021 15:56:17 +0800 -Subject: [PATCH 10/21] mmc: mtk-sd: increase the minimum bus frequency - -With a 48MHz input clock, the lowest bus frequency can be as low as -48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause -the mmc framework take seconds to finish the initialization. - -Limiting the minimum bus frequency to a slightly higher value can solve the -issue without any side effects. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/mmc/mtk-sd.c | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/drivers/mmc/mtk-sd.c -+++ b/drivers/mmc/mtk-sd.c -@@ -232,6 +232,8 @@ - - #define SCLK_CYCLES_SHIFT 20 - -+#define MIN_BUS_CLK 260000 -+ - #define CMD_INTS_MASK \ - (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) - -@@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice - else - cfg->f_min = host->src_clk_freq / (4 * 4095); - -+ if (cfg->f_min < MIN_BUS_CLK) -+ cfg->f_min = MIN_BUS_CLK; -+ - if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) - cfg->f_max = host->src_clk_freq; - diff --git a/package/boot/uboot-mediatek/patches/000-mtk-11-serial-serial-mtk-rewrite-the-setbrg-function.patch b/package/boot/uboot-mediatek/patches/000-mtk-11-serial-serial-mtk-rewrite-the-setbrg-function.patch deleted file mode 100644 index 2ce77333141..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-11-serial-serial-mtk-rewrite-the-setbrg-function.patch +++ /dev/null @@ -1,141 +0,0 @@ -From d8bde59186dafdea5bbe8d29d3a6ae7cac98e9d0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Mon, 25 Jan 2021 11:19:08 +0800 -Subject: [PATCH 11/21] serial: serial-mtk: rewrite the setbrg function - -Currently the setbrg logic of serial-mtk is messy, and should be rewritten. -Also an option is added to make it possible to use highspeed=3 mode for all -bauds. - -The new logic is: -1. If baud clock > 12MHz - a) If baud <= 115200, highspeed=0 mode will be used (ns16550 compatible) - b) If baud <= 576000, highspeed=2 mode will be used - c) any baud > 576000, highspeed=3 mode will be used -2. If baud clock <= 12MHz - Always uses highspeed=3 mode - a) If baud <= 115200, calculates the divisor using DIV_ROUND_CLOSEST - b) any baud > 115200, the same as 1. c) - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - drivers/serial/serial_mtk.c | 74 +++++++++++++++++-------------------- - 1 file changed, 33 insertions(+), 41 deletions(-) - ---- a/drivers/serial/serial_mtk.c -+++ b/drivers/serial/serial_mtk.c -@@ -73,74 +73,64 @@ struct mtk_serial_regs { - struct mtk_serial_priv { - struct mtk_serial_regs __iomem *regs; - u32 clock; -+ bool force_highspeed; - }; - - static void _mtk_serial_setbrg(struct mtk_serial_priv *priv, int baud) - { -- bool support_clk12m_baud115200; -- u32 quot, samplecount, realbaud; -+ u32 quot, realbaud, samplecount = 1; - -- if ((baud <= 115200) && (priv->clock == 12000000)) -- support_clk12m_baud115200 = true; -- else -- support_clk12m_baud115200 = false; -+ /* Special case for low baud clock */ -+ if ((baud <= 115200) && (priv->clock == 12000000)) { -+ writel(3, &priv->regs->highspeed); -+ -+ quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud); -+ if (quot == 0) -+ quot = 1; -+ -+ samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud); -+ -+ realbaud = priv->clock / samplecount / quot; -+ if ((realbaud > BAUD_ALLOW_MAX(baud)) || -+ (realbaud < BAUD_ALLOW_MIX(baud))) { -+ pr_info("baud %d can't be handled\n", baud); -+ } -+ -+ goto set_baud; -+ } -+ -+ if (priv->force_highspeed) -+ goto use_hs3; - - if (baud <= 115200) { - writel(0, &priv->regs->highspeed); - quot = DIV_ROUND_CLOSEST(priv->clock, 16 * baud); -- -- if (support_clk12m_baud115200) { -- writel(3, &priv->regs->highspeed); -- quot = DIV_ROUND_CLOSEST(priv->clock, 256 * baud); -- if (quot == 0) -- quot = 1; -- -- samplecount = DIV_ROUND_CLOSEST(priv->clock, -- quot * baud); -- if (samplecount != 0) { -- realbaud = priv->clock / samplecount / quot; -- if ((realbaud > BAUD_ALLOW_MAX(baud)) || -- (realbaud < BAUD_ALLOW_MIX(baud))) { -- pr_info("baud %d can't be handled\n", -- baud); -- } -- } else { -- pr_info("samplecount is 0\n"); -- } -- } - } else if (baud <= 576000) { - writel(2, &priv->regs->highspeed); - - /* Set to next lower baudrate supported */ - if ((baud == 500000) || (baud == 576000)) - baud = 460800; -+ - quot = DIV_ROUND_UP(priv->clock, 4 * baud); - } else { -+use_hs3: - writel(3, &priv->regs->highspeed); -+ - quot = DIV_ROUND_UP(priv->clock, 256 * baud); -+ samplecount = DIV_ROUND_CLOSEST(priv->clock, quot * baud); - } - -+set_baud: - /* set divisor */ - writel(UART_LCR_WLS_8 | UART_LCR_DLAB, &priv->regs->lcr); - writel(quot & 0xff, &priv->regs->dll); - writel((quot >> 8) & 0xff, &priv->regs->dlm); - writel(UART_LCR_WLS_8, &priv->regs->lcr); - -- if (baud > 460800) { -- u32 tmp; -- -- tmp = DIV_ROUND_CLOSEST(priv->clock, quot * baud); -- writel(tmp - 1, &priv->regs->sample_count); -- writel((tmp - 2) >> 1, &priv->regs->sample_point); -- } else { -- writel(0, &priv->regs->sample_count); -- writel(0xff, &priv->regs->sample_point); -- } -- -- if (support_clk12m_baud115200) { -- writel(samplecount - 1, &priv->regs->sample_count); -- writel((samplecount - 2) >> 1, &priv->regs->sample_point); -- } -+ /* set highspeed mode sample count & point */ -+ writel(samplecount - 1, &priv->regs->sample_count); -+ writel((samplecount - 2) >> 1, &priv->regs->sample_point); - } - - static int _mtk_serial_putc(struct mtk_serial_priv *priv, const char ch) -@@ -248,6 +238,8 @@ static int mtk_serial_of_to_plat(struct - return -EINVAL; - } - -+ priv->force_highspeed = dev_read_bool(dev, "mediatek,force-highspeed"); -+ - return 0; - } - diff --git a/package/boot/uboot-mediatek/patches/000-mtk-12-board-mt7629-enable-compression-of-u-boot-to-reduce-.patch b/package/boot/uboot-mediatek/patches/000-mtk-12-board-mt7629-enable-compression-of-u-boot-to-reduce-.patch deleted file mode 100644 index c0dfad03c48..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-12-board-mt7629-enable-compression-of-u-boot-to-reduce-.patch +++ /dev/null @@ -1,94 +0,0 @@ -From a80ef99cb308904b82662deb66c5ed7a6ff59928 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 3 Mar 2021 11:13:36 +0800 -Subject: [PATCH 12/21] board: mt7629: enable compression of u-boot to reduce - the size of final image - -This patch makes use of the decompression mechanism implemented for mt7628 -previously to reduce the total image size. Binman will be also removed. - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - Makefile | 3 +++ - arch/arm/dts/mt7629-rfb-u-boot.dtsi | 18 ------------------ - arch/arm/mach-mediatek/Kconfig | 1 - - configs/mt7629_rfb_defconfig | 6 ++++++ - 4 files changed, 9 insertions(+), 19 deletions(-) - ---- a/Makefile -+++ b/Makefile -@@ -1666,6 +1666,9 @@ u-boot-elf.lds: arch/u-boot-elf.lds prep - - ifeq ($(CONFIG_SPL),y) - spl/u-boot-spl-mtk.bin: spl/u-boot-spl -+ -+u-boot-mtk.bin: u-boot-with-spl.bin -+ $(call if_changed,copy) - else - MKIMAGEFLAGS_u-boot-mtk.bin = -T mtk_image \ - -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) \ ---- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi -+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi -@@ -5,24 +5,6 @@ - * Author: Weijie Gao <weijie.gao@mediatek.com> - */ - --#include <config.h> --/ { -- binman { -- filename = "u-boot-mtk.bin"; -- pad-byte = <0xff>; -- --#ifdef CONFIG_SPL -- blob { -- filename = "spl/u-boot-spl-mtk.bin"; -- size = <CONFIG_SPL_PAD_TO>; -- }; -- -- u-boot-img { -- }; --#endif -- }; --}; -- - &infracfg { - u-boot,dm-pre-reloc; - }; ---- a/arch/arm/mach-mediatek/Kconfig -+++ b/arch/arm/mach-mediatek/Kconfig -@@ -36,7 +36,6 @@ config TARGET_MT7629 - bool "MediaTek MT7629 SoC" - select CPU_V7A - select SPL -- select BINMAN - help - The MediaTek MT7629 is a ARM-based SoC with a dual-core Cortex-A7 - including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet, ---- a/configs/mt7629_rfb_defconfig -+++ b/configs/mt7629_rfb_defconfig -@@ -10,7 +10,11 @@ CONFIG_SPL_TEXT_BASE=0x201000 - CONFIG_TARGET_MT7629=y - CONFIG_SPL_SERIAL_SUPPORT=y - CONFIG_SPL_DRIVERS_MISC_SUPPORT=y -+CONFIG_SPL_STACK_R_ADDR=0x40800000 -+CONFIG_SPL_PAYLOAD="u-boot-lzma.img" -+CONFIG_BUILD_TARGET="u-boot-mtk.bin" - CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" -+CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" - CONFIG_FIT=y - CONFIG_FIT_VERBOSE=y - CONFIG_BOOTDELAY=3 -@@ -18,6 +22,7 @@ CONFIG_DEFAULT_FDT_FILE="mt7629-rfb" - CONFIG_SYS_CONSOLE_IS_IN_ENV=y - # CONFIG_DISPLAY_BOARDINFO is not set - CONFIG_SPL_SYS_MALLOC_SIMPLE=y -+CONFIG_SPL_STACK_R=y - CONFIG_SPL_NOR_SUPPORT=y - CONFIG_SPL_WATCHDOG_SUPPORT=y - CONFIG_HUSH_PARSER=y -@@ -87,4 +92,5 @@ CONFIG_USB_STORAGE=y - CONFIG_USB_KEYBOARD=y - CONFIG_WDT_MTK=y - CONFIG_LZMA=y -+CONFIG_SPL_LZMA=y - # CONFIG_EFI_LOADER is not set diff --git a/package/boot/uboot-mediatek/patches/000-mtk-13-configs-mt7622-enable-debug-uart-for-mt7622_rfb_defc.patch b/package/boot/uboot-mediatek/patches/000-mtk-13-configs-mt7622-enable-debug-uart-for-mt7622_rfb_defc.patch deleted file mode 100644 index 6b832148b9d..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-13-configs-mt7622-enable-debug-uart-for-mt7622_rfb_defc.patch +++ /dev/null @@ -1,26 +0,0 @@ -From acd49b1549ff52286aace5e841420aa750325f8b Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 3 Mar 2021 10:53:14 +0800 -Subject: [PATCH 13/21] configs: mt7622: enable debug uart for - mt7622_rfb_defconfig - -Enable debug uart for mt7622_rfb_defconfig - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - configs/mt7622_rfb_defconfig | 3 +++ - 1 file changed, 3 insertions(+) - ---- a/configs/mt7622_rfb_defconfig -+++ b/configs/mt7622_rfb_defconfig -@@ -4,7 +4,10 @@ CONFIG_ARCH_MEDIATEK=y - CONFIG_SYS_TEXT_BASE=0x41e00000 - CONFIG_SYS_MALLOC_F_LEN=0x4000 - CONFIG_NR_DRAM_BANKS=1 -+CONFIG_DEBUG_UART_BASE=0x11002000 -+CONFIG_DEBUG_UART_CLOCK=25000000 - CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" -+CONFIG_DEBUG_UART=y - CONFIG_FIT=y - CONFIG_DEFAULT_FDT_FILE="mt7622-rfb" - CONFIG_LOGLEVEL=7 diff --git a/package/boot/uboot-mediatek/patches/000-mtk-19-configs-mt7629-remove-unused-options-and-add-dm-comm.patch b/package/boot/uboot-mediatek/patches/000-mtk-19-configs-mt7629-remove-unused-options-and-add-dm-comm.patch deleted file mode 100644 index fadb274bfdf..00000000000 --- a/package/boot/uboot-mediatek/patches/000-mtk-19-configs-mt7629-remove-unused-options-and-add-dm-comm.patch +++ /dev/null @@ -1,31 +0,0 @@ -From 2f7aaf3c2c127bd53d5e8bfe39e808fdd6eb99be Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Wed, 3 Mar 2021 12:12:39 +0800 -Subject: [PATCH 19/21] configs: mt7629: remove unused options and add dm - command - -Remove unused bootm options -Add dm command - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - configs/mt7629_rfb_defconfig | 5 +++++ - 1 file changed, 5 insertions(+) - ---- a/configs/mt7629_rfb_defconfig -+++ b/configs/mt7629_rfb_defconfig -@@ -28,9 +28,14 @@ CONFIG_SPL_WATCHDOG_SUPPORT=y - CONFIG_HUSH_PARSER=y - CONFIG_SYS_PROMPT="U-Boot> " - CONFIG_CMD_BOOTMENU=y -+# CONFIG_BOOTM_NETBSD is not set -+# CONFIG_BOOTM_PLAN9 is not set -+# CONFIG_BOOTM_RTEMS is not set -+# CONFIG_BOOTM_VXWORKS is not set - # CONFIG_CMD_ELF is not set - # CONFIG_CMD_XIMG is not set - CONFIG_CMD_BIND=y -+CONFIG_CMD_DM=y - # CONFIG_CMD_FLASH is not set - CONFIG_CMD_GPIO=y - CONFIG_CMD_SF_TEST=y diff --git a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch index 228c3351ca0..dcbf8b953fa 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch +++ b/package/boot/uboot-mediatek/patches/000-mtk-20-configs-mt7622-enable-environment-for-mt7622_rfb.patch @@ -1,7 +1,7 @@ -From e5a71a0eebadfb3d75d8619a8b317eec58b2bca2 Mon Sep 17 00:00:00 2001 +From 93d7086edb0db4b05149dfea21a2a82d8f160944 Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Sat, 6 Mar 2021 16:29:33 +0800 -Subject: [PATCH 20/21] configs: mt7622: enable environment for mt7622_rfb +Subject: [PATCH 10/12] configs: mt7622: enable environment for mt7622_rfb Enable environment vairables for mt7622_rfb @@ -12,16 +12,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -4,6 +4,8 @@ CONFIG_ARCH_MEDIATEK=y - CONFIG_SYS_TEXT_BASE=0x41e00000 +@@ -6,6 +6,8 @@ CONFIG_TEXT_BASE=0x41e00000 CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 + CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x280000 CONFIG_DEBUG_UART_BASE=0x11002000 CONFIG_DEBUG_UART_CLOCK=25000000 - CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb" -@@ -21,6 +23,9 @@ CONFIG_CMD_SF_TEST=y + CONFIG_SYS_LOAD_ADDR=0x4007ff28 +@@ -25,6 +27,9 @@ CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y CONFIG_CMD_SMC=y CONFIG_ENV_OVERWRITE=y @@ -30,4 +30,4 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +CONFIG_ENV_SIZE_REDUND=0x40000 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_NET_RANDOM_ETHADDR=y - CONFIG_REGMAP=y + CONFIG_USE_IPADDR=y diff --git a/package/boot/uboot-mediatek/patches/001-disk-part_dos.c-Fix-a-variable-typo-in-write_mbr_par.patch b/package/boot/uboot-mediatek/patches/001-disk-part_dos.c-Fix-a-variable-typo-in-write_mbr_par.patch deleted file mode 100644 index 8432053ea02..00000000000 --- a/package/boot/uboot-mediatek/patches/001-disk-part_dos.c-Fix-a-variable-typo-in-write_mbr_par.patch +++ /dev/null @@ -1,26 +0,0 @@ -From c7d1b1890880ee64786b92a1b95ba9ecb4694997 Mon Sep 17 00:00:00 2001 -From: Christian Melki <christian.melki@t2data.com> -Date: Mon, 7 Jun 2021 11:21:15 +0200 -Subject: [PATCH] disk/part_dos.c: Fix a variable typo in - write_mbr_partitions() - -This function is passed *dev not *dev_desc, so pass the right name to -part_init(). - -Fixes: f14c5ee5ab8b ("disk: part_dos: update partition table entries after write") -Signed-off-by: Christian Melki <christian.melki@t2data.com> ---- - disk/part_dos.c | 2 +- - 1 file changed, 1 insertion(+), 1 deletion(-) - ---- a/disk/part_dos.c -+++ b/disk/part_dos.c -@@ -424,7 +424,7 @@ int write_mbr_partitions(struct blk_desc - } - - /* Update the partition table entries*/ -- part_init(dev_desc); -+ part_init(dev); - - return 0; - } diff --git a/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch b/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch index 42d60c3f66c..601e394f5e4 100644 --- a/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch +++ b/package/boot/uboot-mediatek/patches/050-mt7622-enable-pstore.patch @@ -15,7 +15,7 @@ + ranges; + + /* 64 KiB reserved for ramoops/pstore */ -+ ramoops@0x42ff0000 { ++ ramoops@42ff0000 { + compatible = "ramoops"; + reg = <0 0x42ff0000 0 0x10000>; + record-size = <0x1000>; diff --git a/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch b/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch new file mode 100644 index 00000000000..d6ae7f0f139 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/051-mt7986-enable-pstore.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/dts/mt7986.dtsi ++++ b/arch/arm/dts/mt7986.dtsi +@@ -50,6 +50,35 @@ + }; + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x30000>; ++ no-map; ++ }; ++ ++ wmcpu_emi: wmcpu-reserved@4fc00000 { ++ no-map; ++ reg = <0 0x4fc00000 0 0x00100000>; ++ }; ++ }; ++ + dummy_clk: dummy12m { + compatible = "fixed-clock"; + clock-frequency = <12000000>; diff --git a/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch b/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch new file mode 100644 index 00000000000..9bfea8f7379 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/052-mt7981-enable-pstore.patch @@ -0,0 +1,38 @@ +--- a/arch/arm/dts/mt7981.dtsi ++++ b/arch/arm/dts/mt7981.dtsi +@@ -32,6 +32,35 @@ + }; + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x30000>; ++ no-map; ++ }; ++ ++ wmcpu_emi: wmcpu-reserved@4fc00000 { ++ no-map; ++ reg = <0 0x4fc00000 0 0x00100000>; ++ }; ++ }; ++ + gpt_clk: gpt_dummy20m { + compatible = "fixed-clock"; + clock-frequency = <13000000>; diff --git a/package/boot/uboot-mediatek/patches/000-mtk-14-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch index a01d9e2b177..05138d984e5 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-14-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch +++ b/package/boot/uboot-mediatek/patches/100-02-drivers-mtd-add-support-for-MediaTek-SPI-NAND-flash-.patch @@ -1,7 +1,7 @@ -From f22a055a9f589f1ec614045eba3cb0c5fd887feb Mon Sep 17 00:00:00 2001 +From f7704275957852cd4c4632d6da126979ef24b83a Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Tue, 2 Mar 2021 16:58:01 +0800 -Subject: [PATCH 14/21] drivers: mtd: add support for MediaTek SPI-NAND flash +Subject: [PATCH 36/71] drivers: mtd: add support for MediaTek SPI-NAND flash controller Add mtd driver for MediaTek SPI-NAND flash controller @@ -16,15 +16,15 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> drivers/mtd/Makefile | 2 + drivers/mtd/mtk-snand/Kconfig | 21 + drivers/mtd/mtk-snand/Makefile | 11 + - drivers/mtd/mtk-snand/mtk-snand-def.h | 266 ++++ - drivers/mtd/mtk-snand/mtk-snand-ecc.c | 264 ++++ - drivers/mtd/mtk-snand/mtk-snand-ids.c | 511 +++++++ - drivers/mtd/mtk-snand/mtk-snand-mtd.c | 526 ++++++++ + drivers/mtd/mtk-snand/mtk-snand-def.h | 271 ++++ + drivers/mtd/mtk-snand/mtk-snand-ecc.c | 411 ++++++ + drivers/mtd/mtk-snand/mtk-snand-ids.c | 515 +++++++ + drivers/mtd/mtk-snand/mtk-snand-mtd.c | 535 +++++++ drivers/mtd/mtk-snand/mtk-snand-os.c | 39 + drivers/mtd/mtk-snand/mtk-snand-os.h | 120 ++ - drivers/mtd/mtk-snand/mtk-snand.c | 1776 +++++++++++++++++++++++++ - drivers/mtd/mtk-snand/mtk-snand.h | 77 ++ - 12 files changed, 3615 insertions(+) + drivers/mtd/mtk-snand/mtk-snand.c | 1933 +++++++++++++++++++++++++ + drivers/mtd/mtk-snand/mtk-snand.h | 77 + + 12 files changed, 3937 insertions(+) create mode 100644 drivers/mtd/mtk-snand/Kconfig create mode 100644 drivers/mtd/mtk-snand/Makefile create mode 100644 drivers/mtd/mtk-snand/mtk-snand-def.h @@ -38,18 +38,18 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/drivers/mtd/Kconfig +++ b/drivers/mtd/Kconfig -@@ -108,6 +108,8 @@ config HBMC_AM654 - This is the driver for HyperBus controller on TI's AM65x and - other SoCs +@@ -238,6 +238,8 @@ config SYS_MAX_FLASH_BANKS_DETECT + to reduce the effective number of flash bank, between 0 and + CONFIG_SYS_MAX_FLASH_BANKS +source "drivers/mtd/mtk-snand/Kconfig" + source "drivers/mtd/nand/Kconfig" - source "drivers/mtd/spi/Kconfig" + config SYS_NAND_MAX_OOBFREE --- a/drivers/mtd/Makefile +++ b/drivers/mtd/Makefile -@@ -40,3 +40,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR +@@ -39,3 +39,5 @@ obj-$(CONFIG_$(SPL_TPL_)SPI_FLASH_SUPPOR obj-$(CONFIG_SPL_UBI) += ubispl/ endif @@ -95,7 +95,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +ccflags-y += -DPRIVATE_MTK_SNAND_HEADER --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand-def.h -@@ -0,0 +1,266 @@ +@@ -0,0 +1,271 @@ +/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -213,6 +213,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + const uint8_t *spare_sizes; + uint32_t num_spare_size; ++ ++ uint16_t latch_lat; ++ uint16_t sample_delay; +}; + +enum mtk_ecc_regs { @@ -272,6 +275,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + uint8_t *page_cache; /* Used by read/write page */ + uint8_t *buf_cache; /* Used by block bad/markbad & auto_oob */ ++ int *sect_bf; /* Used by ECC correction */ +}; + +enum mtk_snand_log_category { @@ -290,7 +294,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +int mtk_snand_ecc_decoder_start(struct mtk_snand *snf); +void mtk_snand_ecc_decoder_stop(struct mtk_snand *snf); +int mtk_ecc_wait_decoder_done(struct mtk_snand *snf); -+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page); ++int mtk_ecc_check_decode_error(struct mtk_snand *snf); ++int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect); + +int mtk_snand_mac_io(struct mtk_snand *snf, const uint8_t *out, uint32_t outlen, + uint8_t *in, uint32_t inlen); @@ -364,7 +369,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#endif /* _MTK_SNAND_DEF_H_ */ --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand-ecc.c -@@ -0,0 +1,264 @@ +@@ -0,0 +1,411 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -413,6 +418,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + +static const uint8_t mt7622_ecc_caps[] = { 4, 6, 8, 10, 12 }; + ++static const uint8_t mt7981_ecc_caps[] = { ++ 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 ++}; ++ +static const uint8_t mt7986_ecc_caps[] = { + 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24 +}; @@ -421,6 +430,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + [ECC_DECDONE] = 0x11c, +}; + ++static const uint32_t mt7981_ecc_regs[] = { ++ [ECC_DECDONE] = 0x124, ++}; ++ +static const uint32_t mt7986_ecc_regs[] = { + [ECC_DECDONE] = 0x124, +}; @@ -442,6 +455,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + .errnum_bits = 5, + .errnum_shift = 5, + }, ++ [SNAND_SOC_MT7981] = { ++ .ecc_caps = mt7981_ecc_caps, ++ .num_ecc_cap = ARRAY_SIZE(mt7981_ecc_caps), ++ .regs = mt7981_ecc_regs, ++ .mode_shift = 5, ++ .errnum_bits = 5, ++ .errnum_shift = 8, ++ }, + [SNAND_SOC_MT7986] = { + .ecc_caps = mt7986_ecc_caps, + .num_ecc_cap = ARRAY_SIZE(mt7986_ecc_caps), @@ -599,7 +620,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + return ret; +} + -+int mtk_ecc_check_decode_error(struct mtk_snand *snf, uint32_t page) ++int mtk_ecc_check_decode_error(struct mtk_snand *snf) +{ + uint32_t i, regi, fi, errnum; + uint32_t errnum_shift = snf->ecc_soc->errnum_shift; @@ -612,26 +633,157 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + errnum = ecc_read32(snf, ECC_DECENUM(regi)); + errnum = (errnum >> (fi * errnum_shift)) & errnum_mask; -+ if (!errnum) -+ continue; + + if (errnum <= snf->ecc_strength) { -+ if (ret >= 0) -+ ret += errnum; -+ continue; ++ snf->sect_bf[i] = errnum; ++ } else { ++ snf->sect_bf[i] = -1; ++ ret = -EBADMSG; + } -+ -+ snand_log_ecc(snf->pdev, -+ "Uncorrectable bitflips in page %u sect %u\n", -+ page, i); -+ ret = -EBADMSG; + } + + return ret; +} ++ ++static int mtk_ecc_check_buf_bitflips(struct mtk_snand *snf, const void *buf, ++ size_t len, uint32_t bitflips) ++{ ++ const uint8_t *buf8 = buf; ++ const uint32_t *buf32; ++ uint32_t d, weight; ++ ++ while (len && ((uintptr_t)buf8) % sizeof(uint32_t)) { ++ weight = hweight8(*buf8); ++ bitflips += BITS_PER_BYTE - weight; ++ buf8++; ++ len--; ++ ++ if (bitflips > snf->ecc_strength) ++ return -EBADMSG; ++ } ++ ++ buf32 = (const uint32_t *)buf8; ++ while (len >= sizeof(uint32_t)) { ++ d = *buf32; ++ ++ if (d != ~0) { ++ weight = hweight32(d); ++ bitflips += sizeof(uint32_t) * BITS_PER_BYTE - weight; ++ } ++ ++ buf32++; ++ len -= sizeof(uint32_t); ++ ++ if (bitflips > snf->ecc_strength) ++ return -EBADMSG; ++ } ++ ++ buf8 = (const uint8_t *)buf32; ++ while (len) { ++ weight = hweight8(*buf8); ++ bitflips += BITS_PER_BYTE - weight; ++ buf8++; ++ len--; ++ ++ if (bitflips > snf->ecc_strength) ++ return -EBADMSG; ++ } ++ ++ return bitflips; ++} ++ ++static int mtk_ecc_check_parity_bitflips(struct mtk_snand *snf, const void *buf, ++ uint32_t bits, uint32_t bitflips) ++{ ++ uint32_t len, i; ++ uint8_t b; ++ int rc; ++ ++ len = bits >> 3; ++ bits &= 7; ++ ++ rc = mtk_ecc_check_buf_bitflips(snf, buf, len, bitflips); ++ if (!bits || rc < 0) ++ return rc; ++ ++ bitflips = rc; ++ ++ /* We want a precise count of bits */ ++ b = ((const uint8_t *)buf)[len]; ++ for (i = 0; i < bits; i++) { ++ if (!(b & BIT(i))) ++ bitflips++; ++ } ++ ++ if (bitflips > snf->ecc_strength) ++ return -EBADMSG; ++ ++ return bitflips; ++} ++ ++static void mtk_ecc_reset_parity(void *buf, uint32_t bits) ++{ ++ uint32_t len; ++ ++ len = bits >> 3; ++ bits &= 7; ++ ++ memset(buf, 0xff, len); ++ ++ /* Only reset bits protected by ECC to 1 */ ++ if (bits) ++ ((uint8_t *)buf)[len] |= GENMASK(bits - 1, 0); ++} ++ ++int mtk_ecc_fixup_empty_sector(struct mtk_snand *snf, uint32_t sect) ++{ ++ uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; ++ uint8_t *oob = snf->page_cache + snf->writesize; ++ uint8_t *data_ptr, *fdm_ptr, *ecc_ptr; ++ int bitflips = 0, ecc_bits, parity_bits; ++ ++ parity_bits = fls(snf->nfi_soc->sector_size * 8); ++ ecc_bits = snf->ecc_strength * parity_bits; ++ ++ data_ptr = snf->page_cache + sect * snf->nfi_soc->sector_size; ++ fdm_ptr = oob + sect * snf->nfi_soc->fdm_size; ++ ecc_ptr = oob + snf->ecc_steps * snf->nfi_soc->fdm_size + ++ sect * ecc_bytes; ++ ++ /* ++ * Check whether DATA + FDM + ECC of a sector contains correctable ++ * bitflips ++ */ ++ bitflips = mtk_ecc_check_buf_bitflips(snf, data_ptr, ++ snf->nfi_soc->sector_size, ++ bitflips); ++ if (bitflips < 0) ++ return -EBADMSG; ++ ++ bitflips = mtk_ecc_check_buf_bitflips(snf, fdm_ptr, ++ snf->nfi_soc->fdm_ecc_size, ++ bitflips); ++ if (bitflips < 0) ++ return -EBADMSG; ++ ++ bitflips = mtk_ecc_check_parity_bitflips(snf, ecc_ptr, ecc_bits, ++ bitflips); ++ if (bitflips < 0) ++ return -EBADMSG; ++ ++ if (!bitflips) ++ return 0; ++ ++ /* Reset the data of this sector to 0xff */ ++ memset(data_ptr, 0xff, snf->nfi_soc->sector_size); ++ memset(fdm_ptr, 0xff, snf->nfi_soc->fdm_ecc_size); ++ mtk_ecc_reset_parity(ecc_ptr, ecc_bits); ++ ++ return bitflips; ++} --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand-ids.c -@@ -0,0 +1,511 @@ +@@ -0,0 +1,515 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -724,6 +876,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + &snand_cap_read_from_cache_quad, + &snand_cap_program_load_x4, + mtk_snand_winbond_select_die), ++ SNAND_INFO("W25N01KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xae, 0x21), ++ SNAND_MEMORG_1G_2K_64, ++ &snand_cap_read_from_cache_quad, ++ &snand_cap_program_load_x4), + SNAND_INFO("W25N02KV", SNAND_ID(SNAND_ID_DYMMY, 0xef, 0xaa, 0x22), + SNAND_MEMORG_2G_2K_128, + &snand_cap_read_from_cache_quad, @@ -767,7 +923,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + &snand_cap_program_load_x4), + SNAND_INFO("GD5F2GQ5UExxG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0x52), + SNAND_MEMORG_2G_2K_128, -+ &snand_cap_read_from_cache_quad_q2d, ++ &snand_cap_read_from_cache_quad_a8d, + &snand_cap_program_load_x4), + SNAND_INFO("GD5F4GQ4UCxIG", SNAND_ID(SNAND_ID_DYMMY, 0xc8, 0xb4), + SNAND_MEMORG_4G_4K_256, @@ -1145,7 +1301,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +} --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand-mtd.c -@@ -0,0 +1,526 @@ +@@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -1201,7 +1357,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + instr->state = MTD_ERASING; + + while (start_addr < end_addr) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (mtk_snand_block_isbad(msm->snf, start_addr)) { + if (!instr->scrub) { @@ -1220,15 +1376,12 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + start_addr += mtd->erasesize; + } + -+ if (ret) -+ instr->state = MTD_ERASE_FAILED; -+ else ++ if (!ret) { + instr->state = MTD_ERASE_DONE; -+ -+ if (!ret) -+ mtd_erase_callback(instr); -+ else ++ } else { ++ instr->state = MTD_ERASE_FAILED; + ret = -EIO; ++ } + + return ret; +} @@ -1240,8 +1393,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + size_t len, ooblen, maxooblen, chklen; + uint32_t col, ooboffs; + uint8_t *datcache, *oobcache; -+ bool raw = ops->mode == MTD_OPS_RAW ? true : false; -+ int ret; ++ bool ecc_failed = false, raw = ops->mode == MTD_OPS_RAW ? true : false; ++ int ret, max_bitflips = 0; + + col = addr & mtd->writesize_mask; + addr &= ~mtd->writesize_mask; @@ -1257,7 +1410,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (ops->mode == MTD_OPS_AUTO_OOB) + ret = mtk_snand_read_page_auto_oob(msm->snf, addr, @@ -1266,9 +1419,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + ret = mtk_snand_read_page(msm->snf, addr, datcache, + oobcache, raw); + -+ if (ret < 0) ++ if (ret < 0 && ret != -EBADMSG) + return ret; + ++ if (ret == -EBADMSG) { ++ mtd->ecc_stats.failed++; ++ ecc_failed = true; ++ } else { ++ mtd->ecc_stats.corrected += ret; ++ max_bitflips = max_t(int, ret, max_bitflips); ++ } ++ ++ mtd->ecc_stats.corrected += ret; ++ max_bitflips = max_t(int, ret, max_bitflips); ++ + if (len) { + /* Move data */ + chklen = mtd->writesize - col; @@ -1298,7 +1462,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + addr += mtd->writesize; + } + -+ return 0; ++ return ecc_failed ? -EBADMSG : max_bitflips; +} + +static int mtk_snand_mtd_read_oob(struct mtd_info *mtd, loff_t from, @@ -1374,7 +1538,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + ops->retlen = 0; + + while (len || ooblen) { -+ WATCHDOG_RESET(); ++ schedule(); + + if (len) { + /* Move data */ @@ -1622,7 +1786,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + mtd->ooblayout = &mtk_snand_ooblayout; + -+ mtd->ecc_strength = msm->cinfo.ecc_strength * msm->cinfo.num_sectors; ++ mtd->ecc_strength = msm->cinfo.ecc_strength; + mtd->bitflip_threshold = (mtd->ecc_strength * 3) / 4; + mtd->ecc_step_size = msm->cinfo.sector_size; + @@ -1661,6 +1825,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +static const struct udevice_id mtk_snand_ids[] = { + { .compatible = "mediatek,mt7622-snand", .data = SNAND_SOC_MT7622 }, + { .compatible = "mediatek,mt7629-snand", .data = SNAND_SOC_MT7629 }, ++ { .compatible = "mediatek,mt7981-snand", .data = SNAND_SOC_MT7981 }, + { .compatible = "mediatek,mt7986-snand", .data = SNAND_SOC_MT7986 }, + { /* sentinel */ }, +}; @@ -1839,7 +2004,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#endif /* _MTK_SNAND_OS_H_ */ --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand.c -@@ -0,0 +1,1776 @@ +@@ -0,0 +1,1933 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -1899,8 +2064,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#define FIFO_WR_REMAIN_S 8 +#define FIFO_RD_REMAIN_S 0 + ++#define NFI_ADDRCNTR 0x070 ++#define SEC_CNTR GENMASK(16, 12) ++#define SEC_CNTR_S 12 ++#define NFI_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) ++ +#define NFI_STRADDR 0x080 + ++#define NFI_BYTELEN 0x084 ++#define BUS_SEC_CNTR(val) (((val) & SEC_CNTR) >> SEC_CNTR_S) ++ +#define NFI_FDM0L 0x0a0 +#define NFI_FDM0M 0x0a4 +#define NFI_FDML(n) (NFI_FDM0L + (n) * 8) @@ -1917,6 +2090,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#define NFI_MASTERSTA_MASK_7622 (MAS_ADDR | MAS_RD | MAS_WR | MAS_RDDLY) +#define AHB_BUS_BUSY BIT(1) +#define BUS_BUSY BIT(0) ++#define NFI_MASTERSTA_MASK_7981 (AHB_BUS_BUSY | BUS_BUSY) +#define NFI_MASTERSTA_MASK_7986 (AHB_BUS_BUSY | BUS_BUSY) + +/* SNFI registers */ @@ -1952,6 +2126,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +#define DATA_READ_MODE_X4 2 +#define DATA_READ_MODE_DUAL 5 +#define DATA_READ_MODE_QUAD 6 ++#define LATCH_LAT_S 8 ++#define LATCH_LAT GENMASK(9, 8) +#define PG_LOAD_CUSTOM_EN BIT(7) +#define DATARD_CUSTOM_EN BIT(6) +#define CS_DESELECT_CYC_S 0 @@ -1979,6 +2155,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + +static const uint8_t mt7622_spare_sizes[] = { 16, 26, 27, 28 }; + ++static const uint8_t mt7981_spare_sizes[] = { ++ 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, ++ 67, 74 ++}; ++ +static const uint8_t mt7986_spare_sizes[] = { + 16, 26, 27, 28, 32, 36, 40, 44, 48, 49, 50, 51, 52, 62, 61, 63, 64, + 67, 74 @@ -1995,7 +2176,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + .empty_page_check = false, + .mastersta_mask = NFI_MASTERSTA_MASK_7622, + .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes), ++ .latch_lat = 0, ++ .sample_delay = 40 + }, + [SNAND_SOC_MT7629] = { + .sector_size = 512, @@ -2007,7 +2190,23 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + .empty_page_check = false, + .mastersta_mask = NFI_MASTERSTA_MASK_7622, + .spare_sizes = mt7622_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes) ++ .num_spare_size = ARRAY_SIZE(mt7622_spare_sizes), ++ .latch_lat = 0, ++ .sample_delay = 40 ++ }, ++ [SNAND_SOC_MT7981] = { ++ .sector_size = 1024, ++ .max_sectors = 16, ++ .fdm_size = 8, ++ .fdm_ecc_size = 1, ++ .fifo_size = 64, ++ .bbm_swap = true, ++ .empty_page_check = true, ++ .mastersta_mask = NFI_MASTERSTA_MASK_7981, ++ .spare_sizes = mt7981_spare_sizes, ++ .num_spare_size = ARRAY_SIZE(mt7981_spare_sizes), ++ .latch_lat = 0, ++ .sample_delay = 40 + }, + [SNAND_SOC_MT7986] = { + .sector_size = 1024, @@ -2019,7 +2218,9 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + .empty_page_check = true, + .mastersta_mask = NFI_MASTERSTA_MASK_7986, + .spare_sizes = mt7986_spare_sizes, -+ .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes) ++ .num_spare_size = ARRAY_SIZE(mt7986_spare_sizes), ++ .latch_lat = 0, ++ .sample_delay = 40 + }, +}; + @@ -2191,7 +2392,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + snand_log_snfi(snf->pdev, "Failed to reset SNFI MAC\n"); + + nfi_write32(snf, SNF_MISC_CTL, (2 << FIFO_RD_LTC_S) | -+ (10 << CS_DESELECT_CYC_S)); ++ (10 << CS_DESELECT_CYC_S) | (snf->nfi_soc->latch_lat << LATCH_LAT_S)); + + return ret; +} @@ -2487,9 +2688,77 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + } +} + ++static int mtk_snand_read_ecc_parity(struct mtk_snand *snf, uint32_t page, ++ uint32_t sect, uint8_t *oob) ++{ ++ uint32_t ecc_bytes = snf->spare_per_sector - snf->nfi_soc->fdm_size; ++ uint32_t coladdr, raw_offs, offs; ++ uint8_t op[4]; ++ ++ if (sizeof(op) + ecc_bytes > SNF_GPRAM_SIZE) { ++ snand_log_snfi(snf->pdev, ++ "ECC parity size does not fit the GPRAM\n"); ++ return -ENOTSUPP; ++ } ++ ++ raw_offs = sect * snf->raw_sector_size + snf->nfi_soc->sector_size + ++ snf->nfi_soc->fdm_size; ++ offs = snf->ecc_steps * snf->nfi_soc->fdm_size + sect * ecc_bytes; ++ ++ /* Column address with plane bit */ ++ coladdr = raw_offs | mtk_snand_get_plane_address(snf, page); ++ ++ op[0] = SNAND_CMD_READ_FROM_CACHE; ++ op[1] = (coladdr >> 8) & 0xff; ++ op[2] = coladdr & 0xff; ++ op[3] = 0; ++ ++ return mtk_snand_mac_io(snf, op, sizeof(op), oob + offs, ecc_bytes); ++} ++ ++static int mtk_snand_check_ecc_result(struct mtk_snand *snf, uint32_t page) ++{ ++ uint8_t *oob = snf->page_cache + snf->writesize; ++ int i, rc, ret = 0, max_bitflips = 0; ++ ++ for (i = 0; i < snf->ecc_steps; i++) { ++ if (snf->sect_bf[i] >= 0) { ++ if (snf->sect_bf[i] > max_bitflips) ++ max_bitflips = snf->sect_bf[i]; ++ continue; ++ } ++ ++ rc = mtk_snand_read_ecc_parity(snf, page, i, oob); ++ if (rc) ++ return rc; ++ ++ rc = mtk_ecc_fixup_empty_sector(snf, i); ++ if (rc < 0) { ++ ret = -EBADMSG; ++ ++ snand_log_ecc(snf->pdev, ++ "Uncorrectable bitflips in page %u sect %u\n", ++ page, i); ++ } else if (rc) { ++ snf->sect_bf[i] = rc; ++ ++ if (snf->sect_bf[i] > max_bitflips) ++ max_bitflips = snf->sect_bf[i]; ++ ++ snand_log_ecc(snf->pdev, ++ "%u bitflip%s corrected in page %u sect %u\n", ++ rc, rc > 1 ? "s" : "", page, i); ++ } else { ++ snf->sect_bf[i] = 0; ++ } ++ } ++ ++ return ret ? ret : max_bitflips; ++} ++ +static int mtk_snand_read_cache(struct mtk_snand *snf, uint32_t page, bool raw) +{ -+ uint32_t coladdr, rwbytes, mode, len; ++ uint32_t coladdr, rwbytes, mode, len, val; + uintptr_t dma_addr; + int ret; + @@ -2509,7 +2778,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Set read mode */ + mode = (uint32_t)snf->mode_rfc << DATA_READ_MODE_S; -+ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, mode | DATARD_CUSTOM_EN); ++ nfi_rmw32(snf, SNF_MISC_CTL, DATA_READ_MODE, ++ mode | DATARD_CUSTOM_EN | (snf->nfi_soc->latch_lat << LATCH_LAT_S)); + + /* Set bytes to read */ + rwbytes = snf->ecc_steps * snf->raw_sector_size; @@ -2557,6 +2827,26 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + goto cleanup; + } + ++ /* Wait for BUS_SEC_CNTR returning expected value */ ++ ret = read32_poll_timeout(snf->nfi_base + NFI_BYTELEN, val, ++ BUS_SEC_CNTR(val) >= snf->ecc_steps, ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ snand_log_nfi(snf->pdev, ++ "Timed out waiting for BUS_SEC_CNTR\n"); ++ goto cleanup; ++ } ++ ++ /* Wait for bus becoming idle */ ++ ret = read32_poll_timeout(snf->nfi_base + NFI_MASTERSTA, val, ++ !(val & snf->nfi_soc->mastersta_mask), ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ snand_log_nfi(snf->pdev, ++ "Timed out waiting for bus becoming idle\n"); ++ goto cleanup; ++ } ++ + if (!raw) { + ret = mtk_ecc_wait_decoder_done(snf); + if (ret) @@ -2564,17 +2854,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + mtk_snand_read_fdm(snf, snf->page_cache + snf->writesize); + -+ /* -+ * For new IPs, ecc error may occur on empty pages. -+ * Use an specific indication bit to check empty page. -+ */ -+ if (snf->nfi_soc->empty_page_check && -+ (nfi_read32(snf, NFI_STA) & READ_EMPTY)) -+ ret = 0; -+ else -+ ret = mtk_ecc_check_decode_error(snf, page); -+ ++ mtk_ecc_check_decode_error(snf); + mtk_snand_ecc_decoder_stop(snf); ++ ++ ret = mtk_snand_check_ecc_result(snf, page); + } + +cleanup: @@ -2583,6 +2866,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Stop read */ + nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); + + /* Clear SNF done flag */ + nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_READ_DONE); @@ -2592,7 +2876,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + nfi_read32(snf, NFI_INTR_STA); + nfi_write32(snf, NFI_INTR_EN, 0); + -+ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN, 0); ++ nfi_rmw32(snf, SNF_MISC_CTL, DATARD_CUSTOM_EN | LATCH_LAT, 0); + + return ret; +} @@ -2628,12 +2912,14 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + void *buf, void *oob, bool raw, bool format) +{ + uint64_t die_addr; -+ uint32_t page; -+ int ret; ++ uint32_t page, dly_ctrl3; ++ int ret, retry_cnt = 0; + + die_addr = mtk_snand_select_die_address(snf, addr); + page = die_addr >> snf->writesize_shift; + ++ dly_ctrl3 = nfi_read32(snf, SNF_DLY_CTL3); ++ + ret = mtk_snand_page_op(snf, page, SNAND_CMD_READ_TO_CACHE); + if (ret) + return ret; @@ -2644,10 +2930,30 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + return ret; + } + ++retry: + ret = mtk_snand_read_cache(snf, page, raw); + if (ret < 0 && ret != -EBADMSG) + return ret; + ++ if (ret == -EBADMSG && retry_cnt < 16) { ++ nfi_write32(snf, SNF_DLY_CTL3, retry_cnt * 2); ++ retry_cnt++; ++ goto retry; ++ } ++ ++ if (retry_cnt) { ++ if(ret == -EBADMSG) { ++ nfi_write32(snf, SNF_DLY_CTL3, dly_ctrl3); ++ snand_log_chip(snf->pdev, ++ "NFI calibration failed. Original sample delay: 0x%x\n", ++ dly_ctrl3); ++ } else { ++ snand_log_chip(snf->pdev, ++ "NFI calibration passed. New sample delay: 0x%x\n", ++ nfi_read32(snf, SNF_DLY_CTL3)); ++ } ++ } ++ + if (raw) { + if (format) { + mtk_snand_bm_swap_raw(snf); @@ -2721,7 +3027,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +static int mtk_snand_program_load(struct mtk_snand *snf, uint32_t page, + bool raw) +{ -+ uint32_t coladdr, rwbytes, mode, len; ++ uint32_t coladdr, rwbytes, mode, len, val; + uintptr_t dma_addr; + int ret; + @@ -2791,6 +3097,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + goto cleanup; + } + ++ /* Wait for NFI_SEC_CNTR returning expected value */ ++ ret = read32_poll_timeout(snf->nfi_base + NFI_ADDRCNTR, val, ++ NFI_SEC_CNTR(val) >= snf->ecc_steps, ++ 0, SNFI_POLL_INTERVAL); ++ if (ret) { ++ snand_log_nfi(snf->pdev, ++ "Timed out waiting for BUS_SEC_CNTR\n"); ++ goto cleanup; ++ } ++ + if (!raw) + mtk_snand_ecc_encoder_stop(snf); + @@ -2799,7 +3115,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + dma_mem_unmap(snf->pdev, dma_addr, len, true); + + /* Stop write */ -+ nfi_write16(snf, NFI_CON, 0); ++ nfi_write32(snf, NFI_CON, 0); ++ nfi_write16(snf, NFI_CNFG, 0); + + /* Clear SNF done flag */ + nfi_rmw32(snf, SNF_STA_CTL1, 0, CUS_PG_DONE); @@ -3456,7 +3773,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + + /* Tuning options */ + nfi_write16(snf, NFI_DEBUG_CON1, WBUF_EN); -+ nfi_write32(snf, SNF_DLY_CTL3, (40 << SFCK_SAM_DLY_S)); ++ nfi_write32(snf, SNF_DLY_CTL3, (snf->nfi_soc->sample_delay << SFCK_SAM_DLY_S)); + + /* Interrupts */ + nfi_read32(snf, NFI_INTR_STA); @@ -3525,8 +3842,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + struct mtk_snand **psnf) +{ + const struct snand_flash_info *snand_info; ++ uint32_t rawpage_size, sect_bf_size; + struct mtk_snand tmpsnf, *snf; -+ uint32_t rawpage_size; + int ret; + + if (!pdata || !psnf) @@ -3567,14 +3884,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + rawpage_size = snand_info->memorg.pagesize + + snand_info->memorg.sparesize; + ++ sect_bf_size = mtk_snand_socs[pdata->soc].max_sectors * ++ sizeof(*snf->sect_bf); ++ + /* Allocate memory for instance and cache */ -+ snf = generic_mem_alloc(dev, sizeof(*snf) + rawpage_size); ++ snf = generic_mem_alloc(dev, ++ sizeof(*snf) + rawpage_size + sect_bf_size); + if (!snf) { + snand_log_chip(dev, "Failed to allocate memory for instance\n"); + return -ENOMEM; + } + -+ snf->buf_cache = (uint8_t *)((uintptr_t)snf + sizeof(*snf)); ++ snf->sect_bf = (int *)((uintptr_t)snf + sizeof(*snf)); ++ snf->buf_cache = (uint8_t *)((uintptr_t)snf->sect_bf + sect_bf_size); + + /* Allocate memory for DMA buffer */ + snf->page_cache = dma_mem_alloc(dev, rawpage_size); @@ -3638,8 +3960,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +enum mtk_snand_soc { + SNAND_SOC_MT7622, + SNAND_SOC_MT7629, ++ SNAND_SOC_MT7981, + SNAND_SOC_MT7986, -+ + __SNAND_SOC_MAX +}; + diff --git a/package/boot/uboot-mediatek/patches/000-mtk-15-mtd-mtk-snand-add-support-for-SPL.patch b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch index 0ec20eb91c7..3d7c4a9bf60 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-15-mtd-mtk-snand-add-support-for-SPL.patch +++ b/package/boot/uboot-mediatek/patches/100-03-mtd-mtk-snand-add-support-for-SPL.patch @@ -1,7 +1,7 @@ -From 0c857d4c9cd9dc8e8ebba18cf9e9b10513ccb35d Mon Sep 17 00:00:00 2001 +From a347e374cb338213632c6dde88dd226d64bd8b27 Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Wed, 3 Mar 2021 08:57:29 +0800 -Subject: [PATCH 15/21] mtd: mtk-snand: add support for SPL +Subject: [PATCH 37/71] mtd: mtk-snand: add support for SPL Add support to initialize SPI-NAND in SPL. Add implementation for SPL NAND loader. @@ -10,8 +10,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- drivers/mtd/mtk-snand/Kconfig | 6 ++ drivers/mtd/mtk-snand/Makefile | 4 + - drivers/mtd/mtk-snand/mtk-snand-spl.c | 132 ++++++++++++++++++++++++++ - 3 files changed, 142 insertions(+) + drivers/mtd/mtk-snand/mtk-snand-spl.c | 133 ++++++++++++++++++++++++++ + 3 files changed, 143 insertions(+) create mode 100644 drivers/mtd/mtk-snand/mtk-snand-spl.c --- a/drivers/mtd/mtk-snand/Kconfig @@ -39,7 +39,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ccflags-y += -DPRIVATE_MTK_SNAND_HEADER --- /dev/null +++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c -@@ -0,0 +1,132 @@ +@@ -0,0 +1,133 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. @@ -74,7 +74,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + return -ENODEV; + + while (sizeremain) { -+ WATCHDOG_RESET(); ++ schedule(); + + leading = off & writesize_mask; + chunksize = cinfo.pagesize - leading; @@ -162,6 +162,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +static const struct udevice_id mtk_snand_ids[] = { + { .compatible = "mediatek,mt7622-snand", .data = SNAND_SOC_MT7622 }, + { .compatible = "mediatek,mt7629-snand", .data = SNAND_SOC_MT7629 }, ++ { .compatible = "mediatek,mt7981-snand", .data = SNAND_SOC_MT7981 }, + { .compatible = "mediatek,mt7986-snand", .data = SNAND_SOC_MT7986 }, + { /* sentinel */ }, +}; diff --git a/package/boot/uboot-mediatek/patches/000-mtk-16-env-add-support-for-generic-MTD-device.patch b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch index 932c4b736a0..9b02b4dc630 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-16-env-add-support-for-generic-MTD-device.patch +++ b/package/boot/uboot-mediatek/patches/100-04-env-add-support-for-generic-MTD-device.patch @@ -1,7 +1,7 @@ -From eaa9bc597e0bf8bcd1486ea49c8c7c070a37a8aa Mon Sep 17 00:00:00 2001 +From efc3e6f5d29f87a433b42f15a0b87e04b7cd498d Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Wed, 3 Mar 2021 10:11:32 +0800 -Subject: [PATCH 16/21] env: add support for generic MTD device +Subject: [PATCH 38/71] env: add support for generic MTD device Add an env driver for generic MTD device. @@ -17,39 +17,20 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> 7 files changed, 299 insertions(+), 3 deletions(-) create mode 100644 env/mtd.c ---- a/cmd/nvedit.c -+++ b/cmd/nvedit.c -@@ -50,6 +50,7 @@ DECLARE_GLOBAL_DATA_PTR; - defined(CONFIG_ENV_IS_IN_MMC) || \ - defined(CONFIG_ENV_IS_IN_FAT) || \ - defined(CONFIG_ENV_IS_IN_EXT4) || \ -+ defined(CONFIG_ENV_IS_IN_MTD) || \ - defined(CONFIG_ENV_IS_IN_NAND) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) || \ - defined(CONFIG_ENV_IS_IN_ONENAND) || \ -@@ -64,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR; - - #if !defined(ENV_IS_IN_DEVICE) && \ - !defined(CONFIG_ENV_IS_NOWHERE) --# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\ -+# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|MTD|\ - NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE - #endif - --- a/env/Kconfig +++ b/env/Kconfig -@@ -19,7 +19,7 @@ config ENV_IS_NOWHERE +@@ -61,7 +61,7 @@ config ENV_IS_DEFAULT !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ - !ENV_IS_IN_UBI + !ENV_IS_IN_UBI && !ENV_IS_IN_MTD - help - Define this if you don't want to or can't have an environment stored - on a storage medium. In this case the environment will still exist -@@ -207,6 +207,27 @@ config ENV_IS_IN_MMC - This value is also in units of bytes, but must also be aligned to - an MMC sector boundary. + select ENV_IS_NOWHERE + + config ENV_IS_NOWHERE +@@ -254,6 +254,27 @@ config ENV_IS_IN_MMC + offset: "u-boot,mmc-env-offset", "u-boot,mmc-env-offset-redundant". + CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND are not used. +config ENV_IS_IN_MTD + bool "Environment in a MTD device" @@ -75,7 +56,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> config ENV_IS_IN_NAND bool "Environment in a NAND device" depends on !CHAIN_OF_TRUST -@@ -513,10 +534,16 @@ config ENV_ADDR_REDUND +@@ -561,10 +582,16 @@ config ENV_ADDR_REDUND Offset from the start of the device (or partition) of the redundant environment location. @@ -92,8 +73,8 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> + ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH - default 0x88000 if ARCH_SUNXI -@@ -560,6 +587,12 @@ config ENV_SECT_SIZE + default 0xF0000 if ARCH_SUNXI +@@ -622,6 +649,12 @@ config ENV_SECT_SIZE help Size of the sector containing the environment. @@ -108,7 +89,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> depends on ENV_IS_IN_UBI --- a/env/Makefile +++ b/env/Makefile -@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) +@@ -24,6 +24,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MMC) += mmc.o obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) += fat.o obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o @@ -118,7 +99,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o --- a/env/env.c +++ b/env/env.c -@@ -69,6 +69,9 @@ static enum env_location env_locations[] +@@ -46,6 +46,9 @@ static enum env_location env_locations[] #ifdef CONFIG_ENV_IS_IN_MMC ENVL_MMC, #endif @@ -389,7 +370,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +}; --- a/include/env_internal.h +++ b/include/env_internal.h -@@ -131,6 +131,7 @@ enum env_location { +@@ -109,6 +109,7 @@ enum env_location { ENVL_FAT, ENVL_FLASH, ENVL_MMC, @@ -399,7 +380,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ENVL_ONENAND, --- a/tools/Makefile +++ b/tools/Makefile -@@ -22,6 +22,7 @@ ENVCRC-$(CONFIG_ENV_IS_EMBEDDED) = y +@@ -37,6 +37,7 @@ subdir-$(HOST_TOOLS_ALL) += gdb ENVCRC-$(CONFIG_ENV_IS_IN_EEPROM) = y ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y diff --git a/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch b/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch new file mode 100644 index 00000000000..d90ca647041 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-05-mtd-add-a-new-mtd-device-type-for-NMBM.patch @@ -0,0 +1,44 @@ +From d26a789c451068caf4bbb4d1ac7bc1f592b5493e Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:58:06 +0800 +Subject: [PATCH 39/71] mtd: add a new mtd device type for NMBM + +This patch adds a new mtd device type for NMBM so that mtdparts can be +correctly probed. And this also gives us an opportunity to add NMBM support +for filesystems in the future. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/mtdparts.c | 3 +++ + include/jffs2/load_kernel.h | 4 +++- + 2 files changed, 6 insertions(+), 1 deletion(-) + +--- a/cmd/mtdparts.c ++++ b/cmd/mtdparts.c +@@ -1057,6 +1057,9 @@ int mtd_id_parse(const char *id, const c + } else if (strncmp(p, "spi-nand", 8) == 0) { + *dev_type = MTD_DEV_TYPE_SPINAND; + p += 8; ++ } else if (strncmp(p, "nmbm", 4) == 0) { ++ *dev_type = MTD_DEV_TYPE_NMBM; ++ p += 4; + } else { + printf("incorrect device type in %s\n", id); + return 1; +--- a/include/jffs2/load_kernel.h ++++ b/include/jffs2/load_kernel.h +@@ -16,11 +16,13 @@ + #define MTD_DEV_TYPE_NAND 0x0002 + #define MTD_DEV_TYPE_ONENAND 0x0004 + #define MTD_DEV_TYPE_SPINAND 0x0008 ++#define MTD_DEV_TYPE_NMBM 0x0010 + + #define MTD_DEV_TYPE(type) (type == MTD_DEV_TYPE_NAND ? "nand" : \ + (type == MTD_DEV_TYPE_NOR ? "nor" : \ + (type == MTD_DEV_TYPE_ONENAND ? "onenand" : \ +- "spi-nand"))) \ ++ (type == MTD_DEV_TYPE_SPINAND ? "spi-nand" : \ ++ "nmbm")))) \ + + struct mtd_device { + struct list_head link; diff --git a/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch new file mode 100644 index 00000000000..23634e64253 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-06-mtd-add-core-facility-code-of-NMBM.patch @@ -0,0 +1,3422 @@ +From 690479081fb6a0c0f77f10fb457ad69e71390f15 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:26:35 +0800 +Subject: [PATCH 40/71] mtd: add core facility code of NMBM + +This patch adds a NAND bad block management named NMBM (NAND mapping block +management) which supports using a mapping table to deal with bad blocks +before factory shipping and during use. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/Kconfig | 2 + + drivers/mtd/Makefile | 1 + + drivers/mtd/nmbm/Kconfig | 29 + + drivers/mtd/nmbm/Makefile | 5 + + drivers/mtd/nmbm/nmbm-core.c | 2936 +++++++++++++++++++++++++++++++ + drivers/mtd/nmbm/nmbm-debug.h | 37 + + drivers/mtd/nmbm/nmbm-debug.inl | 39 + + drivers/mtd/nmbm/nmbm-private.h | 137 ++ + include/nmbm/nmbm-os.h | 66 + + include/nmbm/nmbm.h | 102 ++ + 10 files changed, 3354 insertions(+) + create mode 100644 drivers/mtd/nmbm/Kconfig + create mode 100644 drivers/mtd/nmbm/Makefile + create mode 100644 drivers/mtd/nmbm/nmbm-core.c + create mode 100644 drivers/mtd/nmbm/nmbm-debug.h + create mode 100644 drivers/mtd/nmbm/nmbm-debug.inl + create mode 100644 drivers/mtd/nmbm/nmbm-private.h + create mode 100644 include/nmbm/nmbm-os.h + create mode 100644 include/nmbm/nmbm.h + +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -274,4 +274,6 @@ source "drivers/mtd/ubi/Kconfig" + + source "drivers/mtd/nvmxip/Kconfig" + ++source "drivers/mtd/nmbm/Kconfig" ++ + endmenu +--- a/drivers/mtd/Makefile ++++ b/drivers/mtd/Makefile +@@ -41,3 +41,4 @@ obj-$(CONFIG_SPL_UBI) += ubispl/ + endif + + obj-$(CONFIG_MTK_SPI_NAND) += mtk-snand/ ++obj-$(CONFIG_NMBM) += nmbm/ +--- /dev/null ++++ b/drivers/mtd/nmbm/Kconfig +@@ -0,0 +1,29 @@ ++ ++config NMBM ++ bool "Enable NAND mapping block management" ++ default n ++ ++choice ++ prompt "Default log level" ++ depends on NMBM ++ default NMBM_LOG_LEVEL_INFO ++ ++config NMBM_LOG_LEVEL_DEBUG ++ bool "0 - Debug" ++ ++config NMBM_LOG_LEVEL_INFO ++ bool "1 - Info" ++ ++config NMBM_LOG_LEVEL_WARN ++ bool "2 - Warn" ++ ++config NMBM_LOG_LEVEL_ERR ++ bool "3 - Error" ++ ++config NMBM_LOG_LEVEL_EMERG ++ bool "4 - Emergency" ++ ++config NMBM_LOG_LEVEL_NONE ++ bool "5 - None" ++ ++endchoice +--- /dev/null ++++ b/drivers/mtd/nmbm/Makefile +@@ -0,0 +1,5 @@ ++# SPDX-License-Identifier: GPL-2.0 ++# ++# (C) Copyright 2020 MediaTek Inc. All rights reserved. ++ ++obj-$(CONFIG_NMBM) += nmbm-core.o +--- /dev/null ++++ b/drivers/mtd/nmbm/nmbm-core.c +@@ -0,0 +1,2936 @@ ++// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include "nmbm-private.h" ++ ++#include "nmbm-debug.h" ++ ++#define NMBM_VER_MAJOR 1 ++#define NMBM_VER_MINOR 0 ++#define NMBM_VER NMBM_VERSION_MAKE(NMBM_VER_MAJOR, \ ++ NMBM_VER_MINOR) ++ ++#define NMBM_ALIGN(v, a) (((v) + (a) - 1) & ~((a) - 1)) ++ ++/*****************************************************************************/ ++/* Logging related functions */ ++/*****************************************************************************/ ++ ++/* ++ * nmbm_log_lower - Print log using OS specific routine ++ * @nld: NMBM lower device structure ++ * @level: log level ++ * @fmt: format string ++ */ ++static void nmbm_log_lower(struct nmbm_lower_device *nld, ++ enum nmbm_log_category level, const char *fmt, ...) ++{ ++ va_list ap; ++ ++ if (!nld->logprint) ++ return; ++ ++ va_start(ap, fmt); ++ nld->logprint(nld->arg, level, fmt, ap); ++ va_end(ap); ++} ++ ++/* ++ * nmbm_log - Print log using OS specific routine ++ * @ni: NMBM instance structure ++ * @level: log level ++ * @fmt: format string ++ */ ++static void nmbm_log(struct nmbm_instance *ni, enum nmbm_log_category level, ++ const char *fmt, ...) ++{ ++ va_list ap; ++ ++ if (!ni) ++ return; ++ ++ if (!ni->lower.logprint || level < ni->log_display_level) ++ return; ++ ++ va_start(ap, fmt); ++ ni->lower.logprint(ni->lower.arg, level, fmt, ap); ++ va_end(ap); ++} ++ ++/* ++ * nmbm_set_log_level - Set log display level ++ * @ni: NMBM instance structure ++ * @level: log display level ++ */ ++enum nmbm_log_category nmbm_set_log_level(struct nmbm_instance *ni, ++ enum nmbm_log_category level) ++{ ++ enum nmbm_log_category old; ++ ++ if (!ni) ++ return __NMBM_LOG_MAX; ++ ++ old = ni->log_display_level; ++ ni->log_display_level = level; ++ return old; ++} ++ ++/* ++ * nlog_table_creation - Print log of table creation event ++ * @ni: NMBM instance structure ++ * @main_table: whether the table is main info table ++ * @start_ba: start block address of the table ++ * @end_ba: block address after the end of the table ++ */ ++static void nlog_table_creation(struct nmbm_instance *ni, bool main_table, ++ uint32_t start_ba, uint32_t end_ba) ++{ ++ if (start_ba == end_ba - 1) ++ nlog_info(ni, "%s info table has been written to block %u\n", ++ main_table ? "Main" : "Backup", start_ba); ++ else ++ nlog_info(ni, "%s info table has been written to block %u-%u\n", ++ main_table ? "Main" : "Backup", start_ba, end_ba - 1); ++ ++ nmbm_mark_block_color_info_table(ni, start_ba, end_ba - 1); ++} ++ ++/* ++ * nlog_table_update - Print log of table update event ++ * @ni: NMBM instance structure ++ * @main_table: whether the table is main info table ++ * @start_ba: start block address of the table ++ * @end_ba: block address after the end of the table ++ */ ++static void nlog_table_update(struct nmbm_instance *ni, bool main_table, ++ uint32_t start_ba, uint32_t end_ba) ++{ ++ if (start_ba == end_ba - 1) ++ nlog_debug(ni, "%s info table has been updated in block %u\n", ++ main_table ? "Main" : "Backup", start_ba); ++ else ++ nlog_debug(ni, "%s info table has been updated in block %u-%u\n", ++ main_table ? "Main" : "Backup", start_ba, end_ba - 1); ++ ++ nmbm_mark_block_color_info_table(ni, start_ba, end_ba - 1); ++} ++ ++/* ++ * nlog_table_found - Print log of table found event ++ * @ni: NMBM instance structure ++ * @first_table: whether the table is first found info table ++ * @write_count: write count of the info table ++ * @start_ba: start block address of the table ++ * @end_ba: block address after the end of the table ++ */ ++static void nlog_table_found(struct nmbm_instance *ni, bool first_table, ++ uint32_t write_count, uint32_t start_ba, ++ uint32_t end_ba) ++{ ++ if (start_ba == end_ba - 1) ++ nlog_info(ni, "%s info table with writecount %u found in block %u\n", ++ first_table ? "First" : "Second", write_count, ++ start_ba); ++ else ++ nlog_info(ni, "%s info table with writecount %u found in block %u-%u\n", ++ first_table ? "First" : "Second", write_count, ++ start_ba, end_ba - 1); ++ ++ nmbm_mark_block_color_info_table(ni, start_ba, end_ba - 1); ++} ++ ++/*****************************************************************************/ ++/* Address conversion functions */ ++/*****************************************************************************/ ++ ++/* ++ * addr2ba - Convert a linear address to block address ++ * @ni: NMBM instance structure ++ * @addr: Linear address ++ */ ++static uint32_t addr2ba(struct nmbm_instance *ni, uint64_t addr) ++{ ++ return addr >> ni->erasesize_shift; ++} ++ ++/* ++ * ba2addr - Convert a block address to linear address ++ * @ni: NMBM instance structure ++ * @ba: Block address ++ */ ++static uint64_t ba2addr(struct nmbm_instance *ni, uint32_t ba) ++{ ++ return (uint64_t)ba << ni->erasesize_shift; ++} ++/* ++ * size2blk - Get minimum required blocks for storing specific size of data ++ * @ni: NMBM instance structure ++ * @size: size for storing ++ */ ++static uint32_t size2blk(struct nmbm_instance *ni, uint64_t size) ++{ ++ return (size + ni->lower.erasesize - 1) >> ni->erasesize_shift; ++} ++ ++/*****************************************************************************/ ++/* High level NAND chip APIs */ ++/*****************************************************************************/ ++ ++/* ++ * nmbm_reset_chip - Reset NAND device ++ * @nld: Lower NAND chip structure ++ */ ++static void nmbm_reset_chip(struct nmbm_instance *ni) ++{ ++ if (ni->lower.reset_chip) ++ ni->lower.reset_chip(ni->lower.arg); ++} ++ ++/* ++ * nmbm_read_phys_page - Read page with retry ++ * @ni: NMBM instance structure ++ * @addr: linear address where the data will be read from ++ * @data: the main data to be read ++ * @oob: the oob data to be read ++ * @mode: mode for processing oob data ++ * ++ * Read a page for at most NMBM_TRY_COUNT times. ++ * ++ * Return 0 for success, positive value for corrected bitflip count, ++ * -EBADMSG for ecc error, other negative values for other errors ++ */ ++static int nmbm_read_phys_page(struct nmbm_instance *ni, uint64_t addr, ++ void *data, void *oob, enum nmbm_oob_mode mode) ++{ ++ int tries, ret; ++ ++ for (tries = 0; tries < NMBM_TRY_COUNT; tries++) { ++ ret = ni->lower.read_page(ni->lower.arg, addr, data, oob, mode); ++ if (ret >= 0) ++ return ret; ++ ++ nmbm_reset_chip(ni); ++ } ++ ++ if (ret != -EBADMSG) ++ nlog_err(ni, "Page read failed at address 0x%08llx\n", addr); ++ ++ return ret; ++} ++ ++/* ++ * nmbm_write_phys_page - Write page with retry ++ * @ni: NMBM instance structure ++ * @addr: linear address where the data will be written to ++ * @data: the main data to be written ++ * @oob: the oob data to be written ++ * @mode: mode for processing oob data ++ * ++ * Write a page for at most NMBM_TRY_COUNT times. ++ */ ++static bool nmbm_write_phys_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data, const void *oob, ++ enum nmbm_oob_mode mode) ++{ ++ int tries, ret; ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_err(ni, "%s called with NMBM_F_READ_ONLY set\n", addr); ++ return false; ++ } ++ ++ for (tries = 0; tries < NMBM_TRY_COUNT; tries++) { ++ ret = ni->lower.write_page(ni->lower.arg, addr, data, oob, mode); ++ if (!ret) ++ return true; ++ ++ nmbm_reset_chip(ni); ++ } ++ ++ nlog_err(ni, "Page write failed at address 0x%08llx\n", addr); ++ ++ return false; ++} ++ ++/* ++ * nmbm_erase_phys_block - Erase a block with retry ++ * @ni: NMBM instance structure ++ * @addr: Linear address ++ * ++ * Erase a block for at most NMBM_TRY_COUNT times. ++ */ ++static bool nmbm_erase_phys_block(struct nmbm_instance *ni, uint64_t addr) ++{ ++ int tries, ret; ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_err(ni, "%s called with NMBM_F_READ_ONLY set\n", addr); ++ return false; ++ } ++ ++ for (tries = 0; tries < NMBM_TRY_COUNT; tries++) { ++ ret = ni->lower.erase_block(ni->lower.arg, addr); ++ if (!ret) ++ return true; ++ ++ nmbm_reset_chip(ni); ++ } ++ ++ nlog_err(ni, "Block erasure failed at address 0x%08llx\n", addr); ++ ++ return false; ++} ++ ++/* ++ * nmbm_check_bad_phys_block - Check whether a block is marked bad in OOB ++ * @ni: NMBM instance structure ++ * @ba: block address ++ */ ++static bool nmbm_check_bad_phys_block(struct nmbm_instance *ni, uint32_t ba) ++{ ++ uint64_t addr = ba2addr(ni, ba); ++ int ret; ++ ++ if (ni->lower.is_bad_block) ++ return ni->lower.is_bad_block(ni->lower.arg, addr); ++ ++ /* Treat ECC error as read success */ ++ ret = nmbm_read_phys_page(ni, addr, NULL, ++ ni->page_cache + ni->lower.writesize, ++ NMBM_MODE_RAW); ++ if (ret < 0 && ret != -EBADMSG) ++ return true; ++ ++ return ni->page_cache[ni->lower.writesize] != 0xff; ++} ++ ++/* ++ * nmbm_mark_phys_bad_block - Mark a block bad ++ * @ni: NMBM instance structure ++ * @addr: Linear address ++ */ ++static int nmbm_mark_phys_bad_block(struct nmbm_instance *ni, uint32_t ba) ++{ ++ uint64_t addr = ba2addr(ni, ba); ++ enum nmbm_log_category level; ++ uint32_t off; ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_err(ni, "%s called with NMBM_F_READ_ONLY set\n", addr); ++ return false; ++ } ++ ++ nlog_info(ni, "Block %u [0x%08llx] will be marked bad\n", ba, addr); ++ ++ if (ni->lower.mark_bad_block) ++ return ni->lower.mark_bad_block(ni->lower.arg, addr); ++ ++ /* Whole page set to 0x00 */ ++ memset(ni->page_cache, 0, ni->rawpage_size); ++ ++ /* Write to all pages within this block, disable all errors */ ++ level = nmbm_set_log_level(ni, __NMBM_LOG_MAX); ++ ++ for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { ++ nmbm_write_phys_page(ni, addr + off, ni->page_cache, ++ ni->page_cache + ni->lower.writesize, ++ NMBM_MODE_RAW); ++ } ++ ++ nmbm_set_log_level(ni, level); ++ ++ return 0; ++} ++ ++/*****************************************************************************/ ++/* NMBM related functions */ ++/*****************************************************************************/ ++ ++/* ++ * nmbm_check_header - Check whether a NMBM structure is valid ++ * @data: pointer to a NMBM structure with a NMBM header at beginning ++ * @size: Size of the buffer pointed by @header ++ * ++ * The size of the NMBM structure may be larger than NMBM header, ++ * e.g. block mapping table and block state table. ++ */ ++static bool nmbm_check_header(const void *data, uint32_t size) ++{ ++ const struct nmbm_header *header = data; ++ struct nmbm_header nhdr; ++ uint32_t new_checksum; ++ ++ /* ++ * Make sure expected structure size is equal or smaller than ++ * buffer size. ++ */ ++ if (header->size > size) ++ return false; ++ ++ memcpy(&nhdr, data, sizeof(nhdr)); ++ ++ nhdr.checksum = 0; ++ new_checksum = nmbm_crc32(0, &nhdr, sizeof(nhdr)); ++ if (header->size > sizeof(nhdr)) ++ new_checksum = nmbm_crc32(new_checksum, ++ (const uint8_t *)data + sizeof(nhdr), ++ header->size - sizeof(nhdr)); ++ ++ if (header->checksum != new_checksum) ++ return false; ++ ++ return true; ++} ++ ++/* ++ * nmbm_update_checksum - Update checksum of a NMBM structure ++ * @header: pointer to a NMBM structure with a NMBM header at beginning ++ * ++ * The size of the NMBM structure must be specified by @header->size ++ */ ++static void nmbm_update_checksum(struct nmbm_header *header) ++{ ++ header->checksum = 0; ++ header->checksum = nmbm_crc32(0, header, header->size); ++} ++ ++/* ++ * nmbm_get_spare_block_count - Calculate number of blocks should be reserved ++ * @block_count: number of blocks of data ++ * ++ * Calculate number of blocks should be reserved for data ++ */ ++static uint32_t nmbm_get_spare_block_count(uint32_t block_count) ++{ ++ uint32_t val; ++ ++ val = (block_count + NMBM_SPARE_BLOCK_DIV / 2) / NMBM_SPARE_BLOCK_DIV; ++ val *= NMBM_SPARE_BLOCK_MULTI; ++ ++ if (val < NMBM_SPARE_BLOCK_MIN) ++ val = NMBM_SPARE_BLOCK_MIN; ++ ++ return val; ++} ++ ++/* ++ * nmbm_get_block_state_raw - Get state of a block from raw block state table ++ * @block_state: pointer to raw block state table (bitmap) ++ * @ba: block address ++ */ ++static uint32_t nmbm_get_block_state_raw(nmbm_bitmap_t *block_state, ++ uint32_t ba) ++{ ++ uint32_t unit, shift; ++ ++ unit = ba / NMBM_BITMAP_BLOCKS_PER_UNIT; ++ shift = (ba % NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_BITS_PER_BLOCK; ++ ++ return (block_state[unit] >> shift) & BLOCK_ST_MASK; ++} ++ ++/* ++ * nmbm_get_block_state - Get state of a block from block state table ++ * @ni: NMBM instance structure ++ * @ba: block address ++ */ ++static uint32_t nmbm_get_block_state(struct nmbm_instance *ni, uint32_t ba) ++{ ++ return nmbm_get_block_state_raw(ni->block_state, ba); ++} ++ ++/* ++ * nmbm_set_block_state - Set state of a block to block state table ++ * @ni: NMBM instance structure ++ * @ba: block address ++ * @state: block state ++ * ++ * Set state of a block. If the block state changed, ni->block_state_changed ++ * will be increased. ++ */ ++static bool nmbm_set_block_state(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t state) ++{ ++ uint32_t unit, shift, orig; ++ nmbm_bitmap_t uv; ++ ++ unit = ba / NMBM_BITMAP_BLOCKS_PER_UNIT; ++ shift = (ba % NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_BITS_PER_BLOCK; ++ ++ orig = (ni->block_state[unit] >> shift) & BLOCK_ST_MASK; ++ state &= BLOCK_ST_MASK; ++ ++ uv = ni->block_state[unit] & (~(BLOCK_ST_MASK << shift)); ++ uv |= state << shift; ++ ni->block_state[unit] = uv; ++ ++ if (state == BLOCK_ST_BAD) ++ nmbm_mark_block_color_bad(ni, ba); ++ ++ if (orig != state) { ++ ni->block_state_changed++; ++ return true; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_block_walk_asc - Skip specified number of good blocks, ascending addr. ++ * @ni: NMBM instance structure ++ * @ba: start physical block address ++ * @nba: return physical block address after walk ++ * @count: number of good blocks to be skipped ++ * @limit: highest block address allowed for walking ++ * ++ * Start from @ba, skipping any bad blocks, counting @count good blocks, and ++ * return the next good block address. ++ * ++ * If no enough good blocks counted while @limit reached, false will be returned. ++ * ++ * If @count == 0, nearest good block address will be returned. ++ * @limit is not counted in walking. ++ */ ++static bool nmbm_block_walk_asc(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t *nba, uint32_t count, ++ uint32_t limit) ++{ ++ int32_t nblock = count; ++ ++ if (limit >= ni->block_count) ++ limit = ni->block_count - 1; ++ ++ while (ba < limit) { ++ if (nmbm_get_block_state(ni, ba) == BLOCK_ST_GOOD) ++ nblock--; ++ ++ if (nblock < 0) { ++ *nba = ba; ++ return true; ++ } ++ ++ ba++; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_block_walk_desc - Skip specified number of good blocks, descending addr ++ * @ni: NMBM instance structure ++ * @ba: start physical block address ++ * @nba: return physical block address after walk ++ * @count: number of good blocks to be skipped ++ * @limit: lowest block address allowed for walking ++ * ++ * Start from @ba, skipping any bad blocks, counting @count good blocks, and ++ * return the next good block address. ++ * ++ * If no enough good blocks counted while @limit reached, false will be returned. ++ * ++ * If @count == 0, nearest good block address will be returned. ++ * @limit is not counted in walking. ++ */ ++static bool nmbm_block_walk_desc(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t *nba, uint32_t count, uint32_t limit) ++{ ++ int32_t nblock = count; ++ ++ if (limit >= ni->block_count) ++ limit = ni->block_count - 1; ++ ++ while (ba > limit) { ++ if (nmbm_get_block_state(ni, ba) == BLOCK_ST_GOOD) ++ nblock--; ++ ++ if (nblock < 0) { ++ *nba = ba; ++ return true; ++ } ++ ++ ba--; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_block_walk - Skip specified number of good blocks from curr. block addr ++ * @ni: NMBM instance structure ++ * @ascending: whether to walk ascending ++ * @ba: start physical block address ++ * @nba: return physical block address after walk ++ * @count: number of good blocks to be skipped ++ * @limit: highest/lowest block address allowed for walking ++ * ++ * Start from @ba, skipping any bad blocks, counting @count good blocks, and ++ * return the next good block address. ++ * ++ * If no enough good blocks counted while @limit reached, false will be returned. ++ * ++ * If @count == 0, nearest good block address will be returned. ++ * @limit can be set to negative if no limit required. ++ * @limit is not counted in walking. ++ */ ++static bool nmbm_block_walk(struct nmbm_instance *ni, bool ascending, ++ uint32_t ba, uint32_t *nba, int32_t count, ++ int32_t limit) ++{ ++ if (ascending) ++ return nmbm_block_walk_asc(ni, ba, nba, count, limit); ++ ++ return nmbm_block_walk_desc(ni, ba, nba, count, limit); ++} ++ ++/* ++ * nmbm_scan_badblocks - Scan and record all bad blocks ++ * @ni: NMBM instance structure ++ * ++ * Scan the entire lower NAND chip and record all bad blocks in to block state ++ * table. ++ */ ++static void nmbm_scan_badblocks(struct nmbm_instance *ni) ++{ ++ uint32_t ba; ++ ++ for (ba = 0; ba < ni->block_count; ba++) { ++ if (nmbm_check_bad_phys_block(ni, ba)) { ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ nlog_info(ni, "Bad block %u [0x%08llx]\n", ba, ++ ba2addr(ni, ba)); ++ } ++ } ++} ++ ++/* ++ * nmbm_build_mapping_table - Build initial block mapping table ++ * @ni: NMBM instance structure ++ * ++ * The initial mapping table will be compatible with the stratage of ++ * factory production. ++ */ ++static void nmbm_build_mapping_table(struct nmbm_instance *ni) ++{ ++ uint32_t pb, lb; ++ ++ for (pb = 0, lb = 0; pb < ni->mgmt_start_ba; pb++) { ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD) ++ continue; ++ ++ /* Always map to the next good block */ ++ ni->block_mapping[lb++] = pb; ++ } ++ ++ ni->data_block_count = lb; ++ ++ /* Unusable/Management blocks */ ++ for (pb = lb; pb < ni->block_count; pb++) ++ ni->block_mapping[pb] = -1; ++} ++ ++/* ++ * nmbm_erase_block_and_check - Erase a block and check its usability ++ * @ni: NMBM instance structure ++ * @ba: block address to be erased ++ * ++ * Erase a block anc check its usability ++ * ++ * Return true if the block is usable, false if erasure failure or the block ++ * has too many bitflips. ++ */ ++static bool nmbm_erase_block_and_check(struct nmbm_instance *ni, uint32_t ba) ++{ ++ uint64_t addr, off; ++ bool success; ++ int ret; ++ ++ success = nmbm_erase_phys_block(ni, ba2addr(ni, ba)); ++ if (!success) ++ return false; ++ ++ if (!(ni->lower.flags & NMBM_F_EMPTY_PAGE_ECC_OK)) ++ return true; ++ ++ /* Check every page to make sure there aren't too many bitflips */ ++ ++ addr = ba2addr(ni, ba); ++ ++ for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { ++ schedule(); ++ ++ ret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL, ++ NMBM_MODE_PLACE_OOB); ++ if (ret == -EBADMSG) { ++ /* ++ * NMBM_F_EMPTY_PAGE_ECC_OK means the empty page is ++ * still protected by ECC. So reading pages with ECC ++ * enabled and -EBADMSG means there are too many ++ * bitflips that can't be recovered, and the block ++ * containing the page should be marked bad. ++ */ ++ nlog_err(ni, ++ "Too many bitflips in empty page at 0x%llx\n", ++ addr + off); ++ return false; ++ } ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_erase_range - Erase a range of blocks ++ * @ni: NMBM instance structure ++ * @ba: block address where the erasure will start ++ * @limit: top block address allowed for erasure ++ * ++ * Erase blocks within the specific range. Newly-found bad blocks will be ++ * marked. ++ * ++ * @limit is not counted into the allowed erasure address. ++ */ ++static void nmbm_erase_range(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t limit) ++{ ++ bool success; ++ ++ while (ba < limit) { ++ schedule(); ++ ++ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) ++ goto next_block; ++ ++ /* Insurance to detect unexpected bad block marked by user */ ++ if (nmbm_check_bad_phys_block(ni, ba)) { ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ goto next_block; ++ } ++ ++ success = nmbm_erase_block_and_check(ni, ba); ++ if (success) ++ goto next_block; ++ ++ nmbm_mark_phys_bad_block(ni, ba); ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ ++ next_block: ++ ba++; ++ } ++} ++ ++/* ++ * nmbm_write_repeated_data - Write critical data to a block with retry ++ * @ni: NMBM instance structure ++ * @ba: block address where the data will be written to ++ * @data: the data to be written ++ * @size: size of the data ++ * ++ * Write data to every page of the block. Success only if all pages within ++ * this block have been successfully written. ++ * ++ * Make sure data size is not bigger than one page. ++ * ++ * This function will write and verify every page for at most ++ * NMBM_TRY_COUNT times. ++ */ ++static bool nmbm_write_repeated_data(struct nmbm_instance *ni, uint32_t ba, ++ const void *data, uint32_t size) ++{ ++ uint64_t addr, off; ++ bool success; ++ int ret; ++ ++ if (size > ni->lower.writesize) ++ return false; ++ ++ addr = ba2addr(ni, ba); ++ ++ for (off = 0; off < ni->lower.erasesize; off += ni->lower.writesize) { ++ schedule(); ++ ++ /* Prepare page data. fill 0xff to unused region */ ++ memcpy(ni->page_cache, data, size); ++ memset(ni->page_cache + size, 0xff, ni->rawpage_size - size); ++ ++ success = nmbm_write_phys_page(ni, addr + off, ni->page_cache, ++ NULL, NMBM_MODE_PLACE_OOB); ++ if (!success) ++ return false; ++ ++ /* Verify the data just written. ECC error indicates failure */ ++ ret = nmbm_read_phys_page(ni, addr + off, ni->page_cache, NULL, ++ NMBM_MODE_PLACE_OOB); ++ if (ret < 0) ++ return false; ++ ++ if (memcmp(ni->page_cache, data, size)) ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_write_signature - Write signature to NAND chip ++ * @ni: NMBM instance structure ++ * @limit: top block address allowed for writing ++ * @signature: the signature to be written ++ * @signature_ba: the actual block address where signature is written to ++ * ++ * Write signature within a specific range, from chip bottom to limit. ++ * At most one block will be written. ++ * ++ * @limit is not counted into the allowed write address. ++ */ ++static bool nmbm_write_signature(struct nmbm_instance *ni, uint32_t limit, ++ const struct nmbm_signature *signature, ++ uint32_t *signature_ba) ++{ ++ uint32_t ba = ni->block_count - 1; ++ bool success; ++ ++ while (ba > limit) { ++ schedule(); ++ ++ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) ++ goto next_block; ++ ++ /* Insurance to detect unexpected bad block marked by user */ ++ if (nmbm_check_bad_phys_block(ni, ba)) { ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ goto next_block; ++ } ++ ++ success = nmbm_erase_block_and_check(ni, ba); ++ if (!success) ++ goto skip_bad_block; ++ ++ success = nmbm_write_repeated_data(ni, ba, signature, ++ sizeof(*signature)); ++ if (success) { ++ *signature_ba = ba; ++ return true; ++ } ++ ++ skip_bad_block: ++ nmbm_mark_phys_bad_block(ni, ba); ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ ++ next_block: ++ ba--; ++ }; ++ ++ return false; ++} ++ ++/* ++ * nmbn_read_data - Read data ++ * @ni: NMBM instance structure ++ * @addr: linear address where the data will be read from ++ * @data: the data to be read ++ * @size: the size of data ++ * ++ * Read data range. ++ * Every page will be tried for at most NMBM_TRY_COUNT times. ++ * ++ * Return 0 for success, positive value for corrected bitflip count, ++ * -EBADMSG for ecc error, other negative values for other errors ++ */ ++static int nmbn_read_data(struct nmbm_instance *ni, uint64_t addr, void *data, ++ uint32_t size) ++{ ++ uint64_t off = addr; ++ uint8_t *ptr = data; ++ uint32_t sizeremain = size, chunksize, leading; ++ int ret; ++ ++ while (sizeremain) { ++ schedule(); ++ ++ leading = off & ni->writesize_mask; ++ chunksize = ni->lower.writesize - leading; ++ if (chunksize > sizeremain) ++ chunksize = sizeremain; ++ ++ if (chunksize == ni->lower.writesize) { ++ ret = nmbm_read_phys_page(ni, off - leading, ptr, NULL, ++ NMBM_MODE_PLACE_OOB); ++ if (ret < 0) ++ return ret; ++ } else { ++ ret = nmbm_read_phys_page(ni, off - leading, ++ ni->page_cache, NULL, ++ NMBM_MODE_PLACE_OOB); ++ if (ret < 0) ++ return ret; ++ ++ memcpy(ptr, ni->page_cache + leading, chunksize); ++ } ++ ++ off += chunksize; ++ ptr += chunksize; ++ sizeremain -= chunksize; ++ } ++ ++ return 0; ++} ++ ++/* ++ * nmbn_write_verify_data - Write data with validation ++ * @ni: NMBM instance structure ++ * @addr: linear address where the data will be written to ++ * @data: the data to be written ++ * @size: the size of data ++ * ++ * Write data and verify. ++ * Every page will be tried for at most NMBM_TRY_COUNT times. ++ */ ++static bool nmbn_write_verify_data(struct nmbm_instance *ni, uint64_t addr, ++ const void *data, uint32_t size) ++{ ++ uint64_t off = addr; ++ const uint8_t *ptr = data; ++ uint32_t sizeremain = size, chunksize, leading; ++ bool success; ++ int ret; ++ ++ while (sizeremain) { ++ schedule(); ++ ++ leading = off & ni->writesize_mask; ++ chunksize = ni->lower.writesize - leading; ++ if (chunksize > sizeremain) ++ chunksize = sizeremain; ++ ++ /* Prepare page data. fill 0xff to unused region */ ++ memset(ni->page_cache, 0xff, ni->rawpage_size); ++ memcpy(ni->page_cache + leading, ptr, chunksize); ++ ++ success = nmbm_write_phys_page(ni, off - leading, ++ ni->page_cache, NULL, ++ NMBM_MODE_PLACE_OOB); ++ if (!success) ++ return false; ++ ++ /* Verify the data just written. ECC error indicates failure */ ++ ret = nmbm_read_phys_page(ni, off - leading, ni->page_cache, ++ NULL, NMBM_MODE_PLACE_OOB); ++ if (ret < 0) ++ return false; ++ ++ if (memcmp(ni->page_cache + leading, ptr, chunksize)) ++ return false; ++ ++ off += chunksize; ++ ptr += chunksize; ++ sizeremain -= chunksize; ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_write_mgmt_range - Write management data into NAND within a range ++ * @ni: NMBM instance structure ++ * @addr: preferred start block address for writing ++ * @limit: highest block address allowed for writing ++ * @data: the data to be written ++ * @size: the size of data ++ * @actual_start_ba: actual start block address of data ++ * @actual_end_ba: block address after the end of data ++ * ++ * @limit is not counted into the allowed write address. ++ */ ++static bool nmbm_write_mgmt_range(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t limit, const void *data, ++ uint32_t size, uint32_t *actual_start_ba, ++ uint32_t *actual_end_ba) ++{ ++ const uint8_t *ptr = data; ++ uint32_t sizeremain = size, chunksize; ++ bool success; ++ ++ while (sizeremain && ba < limit) { ++ schedule(); ++ ++ chunksize = sizeremain; ++ if (chunksize > ni->lower.erasesize) ++ chunksize = ni->lower.erasesize; ++ ++ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) ++ goto next_block; ++ ++ /* Insurance to detect unexpected bad block marked by user */ ++ if (nmbm_check_bad_phys_block(ni, ba)) { ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ goto next_block; ++ } ++ ++ success = nmbm_erase_block_and_check(ni, ba); ++ if (!success) ++ goto skip_bad_block; ++ ++ success = nmbn_write_verify_data(ni, ba2addr(ni, ba), ptr, ++ chunksize); ++ if (!success) ++ goto skip_bad_block; ++ ++ if (sizeremain == size) ++ *actual_start_ba = ba; ++ ++ ptr += chunksize; ++ sizeremain -= chunksize; ++ ++ goto next_block; ++ ++ skip_bad_block: ++ nmbm_mark_phys_bad_block(ni, ba); ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ ++ next_block: ++ ba++; ++ } ++ ++ if (sizeremain) ++ return false; ++ ++ *actual_end_ba = ba; ++ ++ return true; ++} ++ ++/* ++ * nmbm_generate_info_table_cache - Generate info table cache data ++ * @ni: NMBM instance structure ++ * ++ * Generate info table cache data to be written into flash. ++ */ ++static bool nmbm_generate_info_table_cache(struct nmbm_instance *ni) ++{ ++ bool changed = false; ++ ++ memset(ni->info_table_cache, 0xff, ni->info_table_size); ++ ++ memcpy(ni->info_table_cache + ni->info_table.state_table_off, ++ ni->block_state, ni->state_table_size); ++ ++ memcpy(ni->info_table_cache + ni->info_table.mapping_table_off, ++ ni->block_mapping, ni->mapping_table_size); ++ ++ ni->info_table.header.magic = NMBM_MAGIC_INFO_TABLE; ++ ni->info_table.header.version = NMBM_VER; ++ ni->info_table.header.size = ni->info_table_size; ++ ++ if (ni->block_state_changed || ni->block_mapping_changed) { ++ ni->info_table.write_count++; ++ changed = true; ++ } ++ ++ memcpy(ni->info_table_cache, &ni->info_table, sizeof(ni->info_table)); ++ ++ nmbm_update_checksum((struct nmbm_header *)ni->info_table_cache); ++ ++ return changed; ++} ++ ++/* ++ * nmbm_write_info_table - Write info table into NAND within a range ++ * @ni: NMBM instance structure ++ * @ba: preferred start block address for writing ++ * @limit: highest block address allowed for writing ++ * @actual_start_ba: actual start block address of info table ++ * @actual_end_ba: block address after the end of info table ++ * ++ * @limit is counted into the allowed write address. ++ */ ++static bool nmbm_write_info_table(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t limit, uint32_t *actual_start_ba, ++ uint32_t *actual_end_ba) ++{ ++ return nmbm_write_mgmt_range(ni, ba, limit, ni->info_table_cache, ++ ni->info_table_size, actual_start_ba, ++ actual_end_ba); ++} ++ ++/* ++ * nmbm_mark_tables_clean - Mark info table `clean' ++ * @ni: NMBM instance structure ++ */ ++static void nmbm_mark_tables_clean(struct nmbm_instance *ni) ++{ ++ ni->block_state_changed = 0; ++ ni->block_mapping_changed = 0; ++} ++ ++/* ++ * nmbm_try_reserve_blocks - Reserve blocks with compromisation ++ * @ni: NMBM instance structure ++ * @ba: start physical block address ++ * @nba: return physical block address after reservation ++ * @count: number of good blocks to be skipped ++ * @min_count: minimum number of good blocks to be skipped ++ * @limit: highest/lowest block address allowed for walking ++ * ++ * Reserve specific blocks. If failed, try to reserve as many as possible. ++ */ ++static bool nmbm_try_reserve_blocks(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t *nba, uint32_t count, ++ int32_t min_count, int32_t limit) ++{ ++ int32_t nblocks = count; ++ bool success; ++ ++ while (nblocks >= min_count) { ++ success = nmbm_block_walk(ni, true, ba, nba, nblocks, limit); ++ if (success) ++ return true; ++ ++ nblocks--; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_rebuild_info_table - Build main & backup info table from scratch ++ * @ni: NMBM instance structure ++ * @allow_no_gap: allow no spare blocks between two tables ++ */ ++static bool nmbm_rebuild_info_table(struct nmbm_instance *ni) ++{ ++ uint32_t table_start_ba, table_end_ba, next_start_ba; ++ uint32_t main_table_end_ba; ++ bool success; ++ ++ /* Set initial value */ ++ ni->main_table_ba = 0; ++ ni->backup_table_ba = 0; ++ ni->mapping_blocks_ba = ni->mapping_blocks_top_ba; ++ ++ /* Write main table */ ++ success = nmbm_write_info_table(ni, ni->mgmt_start_ba, ++ ni->mapping_blocks_top_ba, ++ &table_start_ba, &table_end_ba); ++ if (!success) { ++ /* Failed to write main table, data will be lost */ ++ nlog_emerg(ni, "Unable to write at least one info table!\n"); ++ nlog_emerg(ni, "Please save your data before power off!\n"); ++ ni->protected = 1; ++ return false; ++ } ++ ++ /* Main info table is successfully written, record its offset */ ++ ni->main_table_ba = table_start_ba; ++ main_table_end_ba = table_end_ba; ++ ++ /* Adjust mapping_blocks_ba */ ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_table_creation(ni, true, table_start_ba, table_end_ba); ++ ++ /* Reserve spare blocks for main info table. */ ++ success = nmbm_try_reserve_blocks(ni, table_end_ba, ++ &next_start_ba, ++ ni->info_table_spare_blocks, 0, ++ ni->mapping_blocks_top_ba - ++ size2blk(ni, ni->info_table_size)); ++ if (!success) { ++ /* There is no spare block. */ ++ nlog_debug(ni, "No room for backup info table\n"); ++ return true; ++ } ++ ++ /* Write backup info table. */ ++ success = nmbm_write_info_table(ni, next_start_ba, ++ ni->mapping_blocks_top_ba, ++ &table_start_ba, &table_end_ba); ++ if (!success) { ++ /* There is no enough blocks for backup table. */ ++ nlog_debug(ni, "No room for backup info table\n"); ++ return true; ++ } ++ ++ /* Backup table is successfully written, record its offset */ ++ ni->backup_table_ba = table_start_ba; ++ ++ /* Adjust mapping_blocks_off */ ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ /* Erase spare blocks of main table to clean possible interference data */ ++ nmbm_erase_range(ni, main_table_end_ba, ni->backup_table_ba); ++ ++ nlog_table_creation(ni, false, table_start_ba, table_end_ba); ++ ++ return true; ++} ++ ++/* ++ * nmbm_rescue_single_info_table - Rescue when there is only one info table ++ * @ni: NMBM instance structure ++ * ++ * This function is called when there is only one info table exists. ++ * This function may fail if we can't write new info table ++ */ ++static bool nmbm_rescue_single_info_table(struct nmbm_instance *ni) ++{ ++ uint32_t table_start_ba, table_end_ba, write_ba; ++ bool success; ++ ++ /* Try to write new info table in front of existing table */ ++ success = nmbm_write_info_table(ni, ni->mgmt_start_ba, ++ ni->main_table_ba, ++ &table_start_ba, ++ &table_end_ba); ++ if (success) { ++ /* ++ * New table becomes the main table, existing table becomes ++ * the backup table. ++ */ ++ ni->backup_table_ba = ni->main_table_ba; ++ ni->main_table_ba = table_start_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ /* Erase spare blocks of main table to clean possible interference data */ ++ nmbm_erase_range(ni, table_end_ba, ni->backup_table_ba); ++ ++ nlog_table_creation(ni, true, table_start_ba, table_end_ba); ++ ++ return true; ++ } ++ ++ /* Try to reserve spare blocks for existing table */ ++ success = nmbm_try_reserve_blocks(ni, ni->mapping_blocks_ba, &write_ba, ++ ni->info_table_spare_blocks, 0, ++ ni->mapping_blocks_top_ba - ++ size2blk(ni, ni->info_table_size)); ++ if (!success) { ++ nlog_warn(ni, "Failed to rescue single info table\n"); ++ return false; ++ } ++ ++ /* Try to write new info table next to the existing table */ ++ while (write_ba >= ni->mapping_blocks_ba) { ++ schedule(); ++ ++ success = nmbm_write_info_table(ni, write_ba, ++ ni->mapping_blocks_top_ba, ++ &table_start_ba, ++ &table_end_ba); ++ if (success) ++ break; ++ ++ write_ba--; ++ } ++ ++ if (success) { ++ /* Erase spare blocks of main table to clean possible interference data */ ++ nmbm_erase_range(ni, ni->mapping_blocks_ba, table_start_ba); ++ ++ /* New table becomes the backup table */ ++ ni->backup_table_ba = table_start_ba; ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_table_creation(ni, false, table_start_ba, table_end_ba); ++ ++ return true; ++ } ++ ++ nlog_warn(ni, "Failed to rescue single info table\n"); ++ return false; ++} ++ ++/* ++ * nmbm_update_single_info_table - Update specific one info table ++ * @ni: NMBM instance structure ++ */ ++static bool nmbm_update_single_info_table(struct nmbm_instance *ni, ++ bool update_main_table) ++{ ++ uint32_t write_start_ba, write_limit, table_start_ba, table_end_ba; ++ bool success; ++ ++ /* Determine the write range */ ++ if (update_main_table) { ++ write_start_ba = ni->main_table_ba; ++ write_limit = ni->backup_table_ba; ++ } else { ++ write_start_ba = ni->backup_table_ba; ++ write_limit = ni->mapping_blocks_top_ba; ++ } ++ ++ nmbm_mark_block_color_mgmt(ni, write_start_ba, write_limit - 1); ++ ++ success = nmbm_write_info_table(ni, write_start_ba, write_limit, ++ &table_start_ba, &table_end_ba); ++ if (success) { ++ if (update_main_table) { ++ ni->main_table_ba = table_start_ba; ++ } else { ++ ni->backup_table_ba = table_start_ba; ++ ni->mapping_blocks_ba = table_end_ba; ++ } ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_table_update(ni, update_main_table, table_start_ba, ++ table_end_ba); ++ ++ return true; ++ } ++ ++ if (update_main_table) { ++ /* ++ * If failed to update main table, make backup table the new ++ * main table, and call nmbm_rescue_single_info_table() ++ */ ++ nlog_warn(ni, "Unable to update %s info table\n", ++ update_main_table ? "Main" : "Backup"); ++ ++ ni->main_table_ba = ni->backup_table_ba; ++ ni->backup_table_ba = 0; ++ return nmbm_rescue_single_info_table(ni); ++ } ++ ++ /* Only one table left */ ++ ni->mapping_blocks_ba = ni->backup_table_ba; ++ ni->backup_table_ba = 0; ++ ++ return false; ++} ++ ++/* ++ * nmbm_rescue_main_info_table - Rescue when failed to write main info table ++ * @ni: NMBM instance structure ++ * ++ * This function is called when main info table failed to be written, and ++ * backup info table exists. ++ */ ++static bool nmbm_rescue_main_info_table(struct nmbm_instance *ni) ++{ ++ uint32_t tmp_table_start_ba, tmp_table_end_ba, main_table_start_ba; ++ uint32_t main_table_end_ba, write_ba; ++ uint32_t info_table_erasesize = size2blk(ni, ni->info_table_size); ++ bool success; ++ ++ /* Try to reserve spare blocks for existing backup info table */ ++ success = nmbm_try_reserve_blocks(ni, ni->mapping_blocks_ba, &write_ba, ++ ni->info_table_spare_blocks, 0, ++ ni->mapping_blocks_top_ba - ++ info_table_erasesize); ++ if (!success) { ++ /* There is no spare block. Backup info table becomes the main table. */ ++ nlog_err(ni, "No room for temporary info table\n"); ++ ni->main_table_ba = ni->backup_table_ba; ++ ni->backup_table_ba = 0; ++ return true; ++ } ++ ++ /* Try to write temporary info table into spare unmapped blocks */ ++ while (write_ba >= ni->mapping_blocks_ba) { ++ schedule(); ++ ++ success = nmbm_write_info_table(ni, write_ba, ++ ni->mapping_blocks_top_ba, ++ &tmp_table_start_ba, ++ &tmp_table_end_ba); ++ if (success) ++ break; ++ ++ write_ba--; ++ } ++ ++ if (!success) { ++ /* Backup info table becomes the main table */ ++ nlog_err(ni, "Failed to update main info table\n"); ++ ni->main_table_ba = ni->backup_table_ba; ++ ni->backup_table_ba = 0; ++ return true; ++ } ++ ++ /* Adjust mapping_blocks_off */ ++ ni->mapping_blocks_ba = tmp_table_end_ba; ++ ++ nmbm_mark_block_color_mgmt(ni, ni->backup_table_ba, ++ tmp_table_end_ba - 1); ++ ++ /* ++ * Now write main info table at the beginning of management area. ++ * This operation will generally destroy the original backup info ++ * table. ++ */ ++ success = nmbm_write_info_table(ni, ni->mgmt_start_ba, ++ tmp_table_start_ba, ++ &main_table_start_ba, ++ &main_table_end_ba); ++ if (!success) { ++ /* Temporary info table becomes the main table */ ++ ni->main_table_ba = tmp_table_start_ba; ++ ni->backup_table_ba = 0; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_err(ni, "Failed to update main info table\n"); ++ nmbm_mark_block_color_info_table(ni, tmp_table_start_ba, ++ tmp_table_end_ba - 1); ++ ++ return true; ++ } ++ ++ /* Main info table has been successfully written, record its offset */ ++ ni->main_table_ba = main_table_start_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_table_creation(ni, true, main_table_start_ba, main_table_end_ba); ++ ++ /* ++ * Temporary info table becomes the new backup info table if it's ++ * not overwritten. ++ */ ++ if (main_table_end_ba <= tmp_table_start_ba) { ++ ni->backup_table_ba = tmp_table_start_ba; ++ ++ nlog_table_creation(ni, false, tmp_table_start_ba, ++ tmp_table_end_ba); ++ ++ return true; ++ } ++ ++ /* Adjust mapping_blocks_off */ ++ ni->mapping_blocks_ba = main_table_end_ba; ++ ++ /* Try to reserve spare blocks for new main info table */ ++ success = nmbm_try_reserve_blocks(ni, main_table_end_ba, &write_ba, ++ ni->info_table_spare_blocks, 0, ++ ni->mapping_blocks_top_ba - ++ info_table_erasesize); ++ if (!success) { ++ /* There is no spare block. Only main table exists. */ ++ nlog_err(ni, "No room for backup info table\n"); ++ ni->backup_table_ba = 0; ++ return true; ++ } ++ ++ /* Write new backup info table. */ ++ while (write_ba >= main_table_end_ba) { ++ schedule(); ++ ++ success = nmbm_write_info_table(ni, write_ba, ++ ni->mapping_blocks_top_ba, ++ &tmp_table_start_ba, ++ &tmp_table_end_ba); ++ if (success) ++ break; ++ ++ write_ba--; ++ } ++ ++ if (!success) { ++ nlog_err(ni, "No room for backup info table\n"); ++ ni->backup_table_ba = 0; ++ return true; ++ } ++ ++ /* Backup info table has been successfully written, record its offset */ ++ ni->backup_table_ba = tmp_table_start_ba; ++ ++ /* Adjust mapping_blocks_off */ ++ ni->mapping_blocks_ba = tmp_table_end_ba; ++ ++ /* Erase spare blocks of main table to clean possible interference data */ ++ nmbm_erase_range(ni, main_table_end_ba, ni->backup_table_ba); ++ ++ nlog_table_creation(ni, false, tmp_table_start_ba, tmp_table_end_ba); ++ ++ return true; ++} ++ ++/* ++ * nmbm_update_info_table_once - Update info table once ++ * @ni: NMBM instance structure ++ * @force: force update ++ * ++ * Update both main and backup info table. Return true if at least one info ++ * table has been successfully written. ++ * This function only try to update info table once regard less of the result. ++ */ ++static bool nmbm_update_info_table_once(struct nmbm_instance *ni, bool force) ++{ ++ uint32_t table_start_ba, table_end_ba; ++ uint32_t main_table_limit; ++ bool success; ++ ++ /* Do nothing if there is no change */ ++ if (!nmbm_generate_info_table_cache(ni) && !force) ++ return true; ++ ++ /* Check whether both two tables exist */ ++ if (!ni->backup_table_ba) { ++ main_table_limit = ni->mapping_blocks_top_ba; ++ goto write_main_table; ++ } ++ ++ nmbm_mark_block_color_mgmt(ni, ni->backup_table_ba, ++ ni->mapping_blocks_ba - 1); ++ ++ /* ++ * Write backup info table in its current range. ++ * Note that limit is set to mapping_blocks_top_off to provide as many ++ * spare blocks as possible for the backup table. If at last ++ * unmapped blocks are used by backup table, mapping_blocks_off will ++ * be adjusted. ++ */ ++ success = nmbm_write_info_table(ni, ni->backup_table_ba, ++ ni->mapping_blocks_top_ba, ++ &table_start_ba, &table_end_ba); ++ if (!success) { ++ /* ++ * There is nothing to do if failed to write backup table. ++ * Write the main table now. ++ */ ++ nlog_err(ni, "No room for backup table\n"); ++ ni->mapping_blocks_ba = ni->backup_table_ba; ++ ni->backup_table_ba = 0; ++ main_table_limit = ni->mapping_blocks_top_ba; ++ goto write_main_table; ++ } ++ ++ /* Backup table is successfully written, record its offset */ ++ ni->backup_table_ba = table_start_ba; ++ ++ /* Adjust mapping_blocks_off */ ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ /* The normal limit of main table */ ++ main_table_limit = ni->backup_table_ba; ++ ++ nlog_table_update(ni, false, table_start_ba, table_end_ba); ++ ++write_main_table: ++ if (!ni->main_table_ba) ++ goto rebuild_tables; ++ ++ if (!ni->backup_table_ba) ++ nmbm_mark_block_color_mgmt(ni, ni->mgmt_start_ba, ++ ni->mapping_blocks_ba - 1); ++ else ++ nmbm_mark_block_color_mgmt(ni, ni->mgmt_start_ba, ++ ni->backup_table_ba - 1); ++ ++ /* Write main info table in its current range */ ++ success = nmbm_write_info_table(ni, ni->main_table_ba, ++ main_table_limit, &table_start_ba, ++ &table_end_ba); ++ if (!success) { ++ /* If failed to write main table, go rescue procedure */ ++ if (!ni->backup_table_ba) ++ goto rebuild_tables; ++ ++ return nmbm_rescue_main_info_table(ni); ++ } ++ ++ /* Main info table is successfully written, record its offset */ ++ ni->main_table_ba = table_start_ba; ++ ++ /* Adjust mapping_blocks_off */ ++ if (!ni->backup_table_ba) ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ nmbm_mark_tables_clean(ni); ++ ++ nlog_table_update(ni, true, table_start_ba, table_end_ba); ++ ++ return true; ++ ++rebuild_tables: ++ return nmbm_rebuild_info_table(ni); ++} ++ ++/* ++ * nmbm_update_info_table - Update info table ++ * @ni: NMBM instance structure ++ * ++ * Update both main and backup info table. Return true if at least one table ++ * has been successfully written. ++ * This function will try to update info table repeatedly until no new bad ++ * block found during updating. ++ */ ++static bool nmbm_update_info_table(struct nmbm_instance *ni) ++{ ++ bool success; ++ ++ if (ni->protected) ++ return true; ++ ++ while (ni->block_state_changed || ni->block_mapping_changed) { ++ success = nmbm_update_info_table_once(ni, false); ++ if (!success) { ++ nlog_err(ni, "Failed to update info table\n"); ++ return false; ++ } ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_map_block - Map a bad block to a unused spare block ++ * @ni: NMBM instance structure ++ * @lb: logic block addr to map ++ */ ++static bool nmbm_map_block(struct nmbm_instance *ni, uint32_t lb) ++{ ++ uint32_t pb; ++ bool success; ++ ++ if (ni->mapping_blocks_ba == ni->mapping_blocks_top_ba) { ++ nlog_warn(ni, "No spare unmapped blocks.\n"); ++ return false; ++ } ++ ++ success = nmbm_block_walk(ni, false, ni->mapping_blocks_top_ba, &pb, 0, ++ ni->mapping_blocks_ba); ++ if (!success) { ++ nlog_warn(ni, "No spare unmapped blocks.\n"); ++ nmbm_update_info_table(ni); ++ ni->mapping_blocks_top_ba = ni->mapping_blocks_ba; ++ return false; ++ } ++ ++ ni->block_mapping[lb] = pb; ++ ni->mapping_blocks_top_ba--; ++ ni->block_mapping_changed++; ++ ++ nlog_info(ni, "Logic block %u mapped to physical blcok %u\n", lb, pb); ++ nmbm_mark_block_color_mapped(ni, pb); ++ ++ return true; ++} ++ ++/* ++ * nmbm_create_info_table - Create info table(s) ++ * @ni: NMBM instance structure ++ * ++ * This function assumes that the chip has no existing info table(s) ++ */ ++static bool nmbm_create_info_table(struct nmbm_instance *ni) ++{ ++ uint32_t lb; ++ bool success; ++ ++ /* Set initial mapping_blocks_top_off */ ++ success = nmbm_block_walk(ni, false, ni->signature_ba, ++ &ni->mapping_blocks_top_ba, 1, ++ ni->mgmt_start_ba); ++ if (!success) { ++ nlog_err(ni, "No room for spare blocks\n"); ++ return false; ++ } ++ ++ /* Generate info table cache */ ++ nmbm_generate_info_table_cache(ni); ++ ++ /* Write info table */ ++ success = nmbm_rebuild_info_table(ni); ++ if (!success) { ++ nlog_err(ni, "Failed to build info tables\n"); ++ return false; ++ } ++ ++ /* Remap bad block(s) at end of data area */ ++ for (lb = ni->data_block_count; lb < ni->mgmt_start_ba; lb++) { ++ success = nmbm_map_block(ni, lb); ++ if (!success) ++ break; ++ ++ ni->data_block_count++; ++ } ++ ++ /* If state table and/or mapping table changed, update info table. */ ++ success = nmbm_update_info_table(ni); ++ if (!success) ++ return false; ++ ++ return true; ++} ++ ++/* ++ * nmbm_create_new - Create NMBM on a new chip ++ * @ni: NMBM instance structure ++ */ ++static bool nmbm_create_new(struct nmbm_instance *ni) ++{ ++ bool success; ++ ++ /* Determine the boundary of management blocks */ ++ ni->mgmt_start_ba = ni->block_count * (NMBM_MGMT_DIV - ni->lower.max_ratio) / NMBM_MGMT_DIV; ++ ++ if (ni->lower.max_reserved_blocks && ni->block_count - ni->mgmt_start_ba > ni->lower.max_reserved_blocks) ++ ni->mgmt_start_ba = ni->block_count - ni->lower.max_reserved_blocks; ++ ++ nlog_info(ni, "NMBM management region starts at block %u [0x%08llx]\n", ++ ni->mgmt_start_ba, ba2addr(ni, ni->mgmt_start_ba)); ++ nmbm_mark_block_color_mgmt(ni, ni->mgmt_start_ba, ni->block_count - 1); ++ ++ /* Fill block state table & mapping table */ ++ nmbm_scan_badblocks(ni); ++ nmbm_build_mapping_table(ni); ++ ++ /* Write signature */ ++ ni->signature.header.magic = NMBM_MAGIC_SIGNATURE; ++ ni->signature.header.version = NMBM_VER; ++ ni->signature.header.size = sizeof(ni->signature); ++ ni->signature.nand_size = ni->lower.size; ++ ni->signature.block_size = ni->lower.erasesize; ++ ni->signature.page_size = ni->lower.writesize; ++ ni->signature.spare_size = ni->lower.oobsize; ++ ni->signature.mgmt_start_pb = ni->mgmt_start_ba; ++ ni->signature.max_try_count = NMBM_TRY_COUNT; ++ nmbm_update_checksum(&ni->signature.header); ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_info(ni, "NMBM has been initialized in read-only mode\n"); ++ return true; ++ } ++ ++ success = nmbm_write_signature(ni, ni->mgmt_start_ba, ++ &ni->signature, &ni->signature_ba); ++ if (!success) { ++ nlog_err(ni, "Failed to write signature to a proper offset\n"); ++ return false; ++ } ++ ++ nlog_info(ni, "Signature has been written to block %u [0x%08llx]\n", ++ ni->signature_ba, ba2addr(ni, ni->signature_ba)); ++ nmbm_mark_block_color_signature(ni, ni->signature_ba); ++ ++ /* Write info table(s) */ ++ success = nmbm_create_info_table(ni); ++ if (success) { ++ nlog_info(ni, "NMBM has been successfully created\n"); ++ return true; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_check_info_table_header - Check if a info table header is valid ++ * @ni: NMBM instance structure ++ * @data: pointer to the info table header ++ */ ++static bool nmbm_check_info_table_header(struct nmbm_instance *ni, void *data) ++{ ++ struct nmbm_info_table_header *ifthdr = data; ++ ++ if (ifthdr->header.magic != NMBM_MAGIC_INFO_TABLE) ++ return false; ++ ++ if (ifthdr->header.size != ni->info_table_size) ++ return false; ++ ++ if (ifthdr->mapping_table_off - ifthdr->state_table_off < ni->state_table_size) ++ return false; ++ ++ if (ni->info_table_size - ifthdr->mapping_table_off < ni->mapping_table_size) ++ return false; ++ ++ return true; ++} ++ ++/* ++ * nmbm_check_info_table - Check if a whole info table is valid ++ * @ni: NMBM instance structure ++ * @start_ba: start block address of this table ++ * @end_ba: end block address of this table ++ * @data: pointer to the info table header ++ * @mapping_blocks_top_ba: return the block address of top remapped block ++ */ ++static bool nmbm_check_info_table(struct nmbm_instance *ni, uint32_t start_ba, ++ uint32_t end_ba, void *data, ++ uint32_t *mapping_blocks_top_ba) ++{ ++ struct nmbm_info_table_header *ifthdr = data; ++ int32_t *block_mapping = (int32_t *)((uintptr_t)data + ifthdr->mapping_table_off); ++ nmbm_bitmap_t *block_state = (nmbm_bitmap_t *)((uintptr_t)data + ifthdr->state_table_off); ++ uint32_t minimum_mapping_pb = ni->signature_ba; ++ uint32_t ba; ++ ++ for (ba = 0; ba < ni->data_block_count; ba++) { ++ if ((block_mapping[ba] >= ni->data_block_count && block_mapping[ba] < end_ba) || ++ block_mapping[ba] == ni->signature_ba) ++ return false; ++ ++ if (block_mapping[ba] >= end_ba && block_mapping[ba] < minimum_mapping_pb) ++ minimum_mapping_pb = block_mapping[ba]; ++ } ++ ++ for (ba = start_ba; ba < end_ba; ba++) { ++ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) ++ continue; ++ ++ if (nmbm_get_block_state_raw(block_state, ba) != BLOCK_ST_GOOD) ++ return false; ++ } ++ ++ *mapping_blocks_top_ba = minimum_mapping_pb - 1; ++ ++ return true; ++} ++ ++/* ++ * nmbm_try_load_info_table - Try to load info table from a address ++ * @ni: NMBM instance structure ++ * @ba: start block address of the info table ++ * @eba: return the block address after end of the table ++ * @write_count: return the write count of this table ++ * @mapping_blocks_top_ba: return the block address of top remapped block ++ * @table_loaded: used to record whether ni->info_table has valid data ++ */ ++static bool nmbm_try_load_info_table(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t *eba, uint32_t *write_count, ++ uint32_t *mapping_blocks_top_ba, ++ bool table_loaded) ++{ ++ struct nmbm_info_table_header *ifthdr = (void *)ni->info_table_cache; ++ uint8_t *off = ni->info_table_cache; ++ uint32_t limit = ba + size2blk(ni, ni->info_table_size); ++ uint32_t start_ba = 0, chunksize, sizeremain = ni->info_table_size; ++ bool success, checkhdr = true; ++ int ret; ++ ++ while (sizeremain && ba < limit) { ++ schedule(); ++ ++ if (nmbm_get_block_state(ni, ba) != BLOCK_ST_GOOD) ++ goto next_block; ++ ++ if (nmbm_check_bad_phys_block(ni, ba)) { ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ goto next_block; ++ } ++ ++ chunksize = sizeremain; ++ if (chunksize > ni->lower.erasesize) ++ chunksize = ni->lower.erasesize; ++ ++ /* Assume block with ECC error has no info table data */ ++ ret = nmbn_read_data(ni, ba2addr(ni, ba), off, chunksize); ++ if (ret < 0) ++ goto skip_bad_block; ++ else if (ret > 0) ++ return false; ++ ++ if (checkhdr) { ++ success = nmbm_check_info_table_header(ni, off); ++ if (!success) ++ return false; ++ ++ start_ba = ba; ++ checkhdr = false; ++ } ++ ++ off += chunksize; ++ sizeremain -= chunksize; ++ ++ goto next_block; ++ ++ skip_bad_block: ++ /* Only mark bad in memory */ ++ nmbm_set_block_state(ni, ba, BLOCK_ST_BAD); ++ ++ next_block: ++ ba++; ++ } ++ ++ if (sizeremain) ++ return false; ++ ++ success = nmbm_check_header(ni->info_table_cache, ni->info_table_size); ++ if (!success) ++ return false; ++ ++ *eba = ba; ++ *write_count = ifthdr->write_count; ++ ++ success = nmbm_check_info_table(ni, start_ba, ba, ni->info_table_cache, ++ mapping_blocks_top_ba); ++ if (!success) ++ return false; ++ ++ if (!table_loaded || ifthdr->write_count > ni->info_table.write_count) { ++ memcpy(&ni->info_table, ifthdr, sizeof(ni->info_table)); ++ memcpy(ni->block_state, ++ (uint8_t *)ifthdr + ifthdr->state_table_off, ++ ni->state_table_size); ++ memcpy(ni->block_mapping, ++ (uint8_t *)ifthdr + ifthdr->mapping_table_off, ++ ni->mapping_table_size); ++ ni->info_table.write_count = ifthdr->write_count; ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_search_info_table - Search info table from specific address ++ * @ni: NMBM instance structure ++ * @ba: start block address to search ++ * @limit: highest block address allowed for searching ++ * @table_start_ba: return the start block address of this table ++ * @table_end_ba: return the block address after end of this table ++ * @write_count: return the write count of this table ++ * @mapping_blocks_top_ba: return the block address of top remapped block ++ * @table_loaded: used to record whether ni->info_table has valid data ++ */ ++static bool nmbm_search_info_table(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t limit, uint32_t *table_start_ba, ++ uint32_t *table_end_ba, ++ uint32_t *write_count, ++ uint32_t *mapping_blocks_top_ba, ++ bool table_loaded) ++{ ++ bool success; ++ ++ while (ba < limit - size2blk(ni, ni->info_table_size)) { ++ schedule(); ++ ++ success = nmbm_try_load_info_table(ni, ba, table_end_ba, ++ write_count, ++ mapping_blocks_top_ba, ++ table_loaded); ++ if (success) { ++ *table_start_ba = ba; ++ return true; ++ } ++ ++ ba++; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_load_info_table - Load info table(s) from a chip ++ * @ni: NMBM instance structure ++ * @ba: start block address to search info table ++ * @limit: highest block address allowed for searching ++ */ ++static bool nmbm_load_info_table(struct nmbm_instance *ni, uint32_t ba, ++ uint32_t limit) ++{ ++ uint32_t main_table_end_ba, backup_table_end_ba, table_end_ba; ++ uint32_t main_mapping_blocks_top_ba, backup_mapping_blocks_top_ba; ++ uint32_t main_table_write_count, backup_table_write_count; ++ uint32_t i; ++ bool success; ++ ++ /* Set initial value */ ++ ni->main_table_ba = 0; ++ ni->backup_table_ba = 0; ++ ni->info_table.write_count = 0; ++ ni->mapping_blocks_top_ba = ni->signature_ba - 1; ++ ni->data_block_count = ni->signature.mgmt_start_pb; ++ ++ /* Find first info table */ ++ success = nmbm_search_info_table(ni, ba, limit, &ni->main_table_ba, ++ &main_table_end_ba, &main_table_write_count, ++ &main_mapping_blocks_top_ba, false); ++ if (!success) { ++ nlog_warn(ni, "No valid info table found\n"); ++ return false; ++ } ++ ++ table_end_ba = main_table_end_ba; ++ ++ nlog_table_found(ni, true, main_table_write_count, ni->main_table_ba, ++ main_table_end_ba); ++ ++ /* Find second info table */ ++ success = nmbm_search_info_table(ni, main_table_end_ba, limit, ++ &ni->backup_table_ba, &backup_table_end_ba, ++ &backup_table_write_count, &backup_mapping_blocks_top_ba, true); ++ if (!success) { ++ nlog_warn(ni, "Second info table not found\n"); ++ } else { ++ table_end_ba = backup_table_end_ba; ++ ++ nlog_table_found(ni, false, backup_table_write_count, ++ ni->backup_table_ba, backup_table_end_ba); ++ } ++ ++ /* Pick mapping_blocks_top_ba */ ++ if (!ni->backup_table_ba) { ++ ni->mapping_blocks_top_ba= main_mapping_blocks_top_ba; ++ } else { ++ if (main_table_write_count >= backup_table_write_count) ++ ni->mapping_blocks_top_ba = main_mapping_blocks_top_ba; ++ else ++ ni->mapping_blocks_top_ba = backup_mapping_blocks_top_ba; ++ } ++ ++ /* Set final mapping_blocks_ba */ ++ ni->mapping_blocks_ba = table_end_ba; ++ ++ /* Set final data_block_count */ ++ for (i = ni->signature.mgmt_start_pb; i > 0; i--) { ++ if (ni->block_mapping[i - 1] >= 0) { ++ ni->data_block_count = i; ++ break; ++ } ++ } ++ ++ /* Debug purpose: mark mapped blocks and bad blocks */ ++ for (i = 0; i < ni->data_block_count; i++) { ++ if (ni->block_mapping[i] > ni->mapping_blocks_top_ba) ++ nmbm_mark_block_color_mapped(ni, ni->block_mapping[i]); ++ } ++ ++ for (i = 0; i < ni->block_count; i++) { ++ if (nmbm_get_block_state(ni, i) == BLOCK_ST_BAD) ++ nmbm_mark_block_color_bad(ni, i); ++ } ++ ++ /* Regenerate the info table cache from the final selected info table */ ++ nmbm_generate_info_table_cache(ni); ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) ++ return true; ++ ++ /* ++ * If only one table exists, try to write another table. ++ * If two tables have different write count, try to update info table ++ */ ++ if (!ni->backup_table_ba) { ++ success = nmbm_rescue_single_info_table(ni); ++ } else if (main_table_write_count != backup_table_write_count) { ++ /* Mark state & mapping tables changed */ ++ ni->block_state_changed = 1; ++ ni->block_mapping_changed = 1; ++ ++ success = nmbm_update_single_info_table(ni, ++ main_table_write_count < backup_table_write_count); ++ } else { ++ success = true; ++ } ++ ++ /* ++ * If there is no spare unmapped blocks, or still only one table ++ * exists, set the chip to read-only ++ */ ++ if (ni->mapping_blocks_ba == ni->mapping_blocks_top_ba) { ++ nlog_warn(ni, "No spare unmapped blocks. Device is now read-only\n"); ++ ni->protected = 1; ++ } else if (!success) { ++ nlog_warn(ni, "Only one info table found. Device is now read-only\n"); ++ ni->protected = 1; ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_load_existing - Load NMBM from a new chip ++ * @ni: NMBM instance structure ++ */ ++static bool nmbm_load_existing(struct nmbm_instance *ni) ++{ ++ bool success; ++ ++ /* Calculate the boundary of management blocks */ ++ ni->mgmt_start_ba = ni->signature.mgmt_start_pb; ++ ++ nlog_debug(ni, "NMBM management region starts at block %u [0x%08llx]\n", ++ ni->mgmt_start_ba, ba2addr(ni, ni->mgmt_start_ba)); ++ nmbm_mark_block_color_mgmt(ni, ni->mgmt_start_ba, ++ ni->signature_ba - 1); ++ ++ /* Look for info table(s) */ ++ success = nmbm_load_info_table(ni, ni->mgmt_start_ba, ++ ni->signature_ba); ++ if (success) { ++ nlog_info(ni, "NMBM has been successfully attached %s\n", ++ (ni->lower.flags & NMBM_F_READ_ONLY) ? "in read-only mode" : ""); ++ return true; ++ } ++ ++ if (!(ni->lower.flags & NMBM_F_CREATE)) ++ return false; ++ ++ /* Fill block state table & mapping table */ ++ nmbm_scan_badblocks(ni); ++ nmbm_build_mapping_table(ni); ++ ++ if (ni->lower.flags & NMBM_F_READ_ONLY) { ++ nlog_info(ni, "NMBM has been initialized in read-only mode\n"); ++ return true; ++ } ++ ++ /* Write info table(s) */ ++ success = nmbm_create_info_table(ni); ++ if (success) { ++ nlog_info(ni, "NMBM has been successfully created\n"); ++ return true; ++ } ++ ++ return false; ++} ++ ++/* ++ * nmbm_find_signature - Find signature in the lower NAND chip ++ * @ni: NMBM instance structure ++ * @signature_ba: used for storing block address of the signature ++ * @signature_ba: return the actual block address of signature block ++ * ++ * Find a valid signature from a specific range in the lower NAND chip, ++ * from bottom (highest address) to top (lowest address) ++ * ++ * Return true if found. ++ */ ++static bool nmbm_find_signature(struct nmbm_instance *ni, ++ struct nmbm_signature *signature, ++ uint32_t *signature_ba) ++{ ++ struct nmbm_signature sig; ++ uint64_t off, addr; ++ uint32_t block_count, ba, limit; ++ bool success; ++ int ret; ++ ++ /* Calculate top and bottom block address */ ++ block_count = ni->lower.size >> ni->erasesize_shift; ++ ba = block_count; ++ limit = (block_count / NMBM_MGMT_DIV) * (NMBM_MGMT_DIV - ni->lower.max_ratio); ++ if (ni->lower.max_reserved_blocks && block_count - limit > ni->lower.max_reserved_blocks) ++ limit = block_count - ni->lower.max_reserved_blocks; ++ ++ while (ba >= limit) { ++ schedule(); ++ ++ ba--; ++ addr = ba2addr(ni, ba); ++ ++ if (nmbm_check_bad_phys_block(ni, ba)) ++ continue; ++ ++ /* Check every page. ++ * As long as at leaset one page contains valid signature, ++ * the block is treated as a valid signature block. ++ */ ++ for (off = 0; off < ni->lower.erasesize; ++ off += ni->lower.writesize) { ++ schedule(); ++ ++ ret = nmbn_read_data(ni, addr + off, &sig, ++ sizeof(sig)); ++ if (ret) ++ continue; ++ ++ /* Check for header size and checksum */ ++ success = nmbm_check_header(&sig, sizeof(sig)); ++ if (!success) ++ continue; ++ ++ /* Check for header magic */ ++ if (sig.header.magic == NMBM_MAGIC_SIGNATURE) { ++ /* Found it */ ++ memcpy(signature, &sig, sizeof(sig)); ++ *signature_ba = ba; ++ return true; ++ } ++ } ++ }; ++ ++ return false; ++} ++ ++/* ++ * is_power_of_2_u64 - Check whether a 64-bit integer is power of 2 ++ * @n: number to check ++ */ ++static bool is_power_of_2_u64(uint64_t n) ++{ ++ return (n != 0 && ((n & (n - 1)) == 0)); ++} ++ ++/* ++ * nmbm_check_lower_members - Validate the members of lower NAND device ++ * @nld: Lower NAND chip structure ++ */ ++static bool nmbm_check_lower_members(struct nmbm_lower_device *nld) ++{ ++ ++ if (!nld->size || !is_power_of_2_u64(nld->size)) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "Chip size %llu is not valid\n", nld->size); ++ return false; ++ } ++ ++ if (!nld->erasesize || !is_power_of_2(nld->erasesize)) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "Block size %u is not valid\n", nld->erasesize); ++ return false; ++ } ++ ++ if (!nld->writesize || !is_power_of_2(nld->writesize)) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "Page size %u is not valid\n", nld->writesize); ++ return false; ++ } ++ ++ if (!nld->oobsize || !is_power_of_2(nld->oobsize)) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "Page spare size %u is not valid\n", nld->oobsize); ++ return false; ++ } ++ ++ if (!nld->read_page) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, "read_page() is required\n"); ++ return false; ++ } ++ ++ if (!(nld->flags & NMBM_F_READ_ONLY) && (!nld->write_page || !nld->erase_block)) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "write_page() and erase_block() are required\n"); ++ return false; ++ } ++ ++ /* Data sanity check */ ++ if (!nld->max_ratio) ++ nld->max_ratio = 1; ++ ++ if (nld->max_ratio >= NMBM_MGMT_DIV - 1) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "max ratio %u is invalid\n", nld->max_ratio); ++ return false; ++ } ++ ++ if (nld->max_reserved_blocks && nld->max_reserved_blocks < NMBM_MGMT_BLOCKS_MIN) { ++ nmbm_log_lower(nld, NMBM_LOG_ERR, ++ "max reserved blocks %u is too small\n", nld->max_reserved_blocks); ++ return false; ++ } ++ ++ return true; ++} ++ ++/* ++ * nmbm_calc_structure_size - Calculate the instance structure size ++ * @nld: NMBM lower device structure ++ */ ++size_t nmbm_calc_structure_size(struct nmbm_lower_device *nld) ++{ ++ uint32_t state_table_size, mapping_table_size, info_table_size; ++ uint32_t block_count; ++ ++ block_count = nmbm_lldiv(nld->size, nld->erasesize); ++ ++ /* Calculate info table size */ ++ state_table_size = ((block_count + NMBM_BITMAP_BLOCKS_PER_UNIT - 1) / ++ NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_UNIT_SIZE; ++ mapping_table_size = block_count * sizeof(int32_t); ++ ++ info_table_size = NMBM_ALIGN(sizeof(struct nmbm_info_table_header), ++ nld->writesize); ++ info_table_size += NMBM_ALIGN(state_table_size, nld->writesize); ++ info_table_size += NMBM_ALIGN(mapping_table_size, nld->writesize); ++ ++ return info_table_size + state_table_size + mapping_table_size + ++ nld->writesize + nld->oobsize + sizeof(struct nmbm_instance); ++} ++ ++/* ++ * nmbm_init_structure - Initialize members of instance structure ++ * @ni: NMBM instance structure ++ */ ++static void nmbm_init_structure(struct nmbm_instance *ni) ++{ ++ uint32_t pages_per_block, blocks_per_chip; ++ uintptr_t ptr; ++ ++ pages_per_block = ni->lower.erasesize / ni->lower.writesize; ++ blocks_per_chip = nmbm_lldiv(ni->lower.size, ni->lower.erasesize); ++ ++ ni->rawpage_size = ni->lower.writesize + ni->lower.oobsize; ++ ni->rawblock_size = pages_per_block * ni->rawpage_size; ++ ni->rawchip_size = blocks_per_chip * ni->rawblock_size; ++ ++ ni->writesize_mask = ni->lower.writesize - 1; ++ ni->erasesize_mask = ni->lower.erasesize - 1; ++ ++ ni->writesize_shift = ffs(ni->lower.writesize) - 1; ++ ni->erasesize_shift = ffs(ni->lower.erasesize) - 1; ++ ++ /* Calculate number of block this chip */ ++ ni->block_count = ni->lower.size >> ni->erasesize_shift; ++ ++ /* Calculate info table size */ ++ ni->state_table_size = ((ni->block_count + NMBM_BITMAP_BLOCKS_PER_UNIT - 1) / ++ NMBM_BITMAP_BLOCKS_PER_UNIT) * NMBM_BITMAP_UNIT_SIZE; ++ ni->mapping_table_size = ni->block_count * sizeof(*ni->block_mapping); ++ ++ ni->info_table_size = NMBM_ALIGN(sizeof(ni->info_table), ++ ni->lower.writesize); ++ ni->info_table.state_table_off = ni->info_table_size; ++ ++ ni->info_table_size += NMBM_ALIGN(ni->state_table_size, ++ ni->lower.writesize); ++ ni->info_table.mapping_table_off = ni->info_table_size; ++ ++ ni->info_table_size += NMBM_ALIGN(ni->mapping_table_size, ++ ni->lower.writesize); ++ ++ ni->info_table_spare_blocks = nmbm_get_spare_block_count( ++ size2blk(ni, ni->info_table_size)); ++ ++ /* Assign memory to members */ ++ ptr = (uintptr_t)ni + sizeof(*ni); ++ ++ ni->info_table_cache = (void *)ptr; ++ ptr += ni->info_table_size; ++ ++ ni->block_state = (void *)ptr; ++ ptr += ni->state_table_size; ++ ++ ni->block_mapping = (void *)ptr; ++ ptr += ni->mapping_table_size; ++ ++ ni->page_cache = (uint8_t *)ptr; ++ ++ /* Initialize block state table */ ++ ni->block_state_changed = 0; ++ memset(ni->block_state, 0xff, ni->state_table_size); ++ ++ /* Initialize block mapping table */ ++ ni->block_mapping_changed = 0; ++} ++ ++/* ++ * nmbm_attach - Attach to a lower device ++ * @nld: NMBM lower device structure ++ * @ni: NMBM instance structure ++ */ ++int nmbm_attach(struct nmbm_lower_device *nld, struct nmbm_instance *ni) ++{ ++ bool success; ++ ++ if (!nld || !ni) ++ return -EINVAL; ++ ++ /* Set default log level */ ++ ni->log_display_level = NMBM_DEFAULT_LOG_LEVEL; ++ ++ /* Check lower members */ ++ success = nmbm_check_lower_members(nld); ++ if (!success) ++ return -EINVAL; ++ ++ /* Initialize NMBM instance */ ++ memcpy(&ni->lower, nld, sizeof(struct nmbm_lower_device)); ++ nmbm_init_structure(ni); ++ ++ success = nmbm_find_signature(ni, &ni->signature, &ni->signature_ba); ++ if (!success) { ++ if (!(nld->flags & NMBM_F_CREATE)) { ++ nlog_err(ni, "Signature not found\n"); ++ return -ENODEV; ++ } ++ ++ success = nmbm_create_new(ni); ++ if (!success) ++ return -ENODEV; ++ ++ return 0; ++ } ++ ++ nlog_info(ni, "Signature found at block %u [0x%08llx]\n", ++ ni->signature_ba, ba2addr(ni, ni->signature_ba)); ++ nmbm_mark_block_color_signature(ni, ni->signature_ba); ++ ++ if (ni->signature.header.version != NMBM_VER) { ++ nlog_err(ni, "NMBM version %u.%u is not supported\n", ++ NMBM_VERSION_MAJOR_GET(ni->signature.header.version), ++ NMBM_VERSION_MINOR_GET(ni->signature.header.version)); ++ return -EINVAL; ++ } ++ ++ if (ni->signature.nand_size != nld->size || ++ ni->signature.block_size != nld->erasesize || ++ ni->signature.page_size != nld->writesize || ++ ni->signature.spare_size != nld->oobsize) { ++ nlog_err(ni, "NMBM configuration mismatch\n"); ++ return -EINVAL; ++ } ++ ++ success = nmbm_load_existing(ni); ++ if (!success) ++ return -ENODEV; ++ ++ return 0; ++} ++ ++/* ++ * nmbm_detach - Detach from a lower device, and save all tables ++ * @ni: NMBM instance structure ++ */ ++int nmbm_detach(struct nmbm_instance *ni) ++{ ++ if (!ni) ++ return -EINVAL; ++ ++ if (!(ni->lower.flags & NMBM_F_READ_ONLY)) ++ nmbm_update_info_table(ni); ++ ++ nmbm_mark_block_color_normal(ni, 0, ni->block_count - 1); ++ ++ return 0; ++} ++ ++/* ++ * nmbm_erase_logic_block - Erase a logic block ++ * @ni: NMBM instance structure ++ * @nmbm_erase_logic_block: logic block address ++ * ++ * Logic block will be mapped to physical block before erasing. ++ * Bad block found during erasinh will be remapped to a good block if there is ++ * still at least one good spare block available. ++ */ ++static int nmbm_erase_logic_block(struct nmbm_instance *ni, uint32_t block_addr) ++{ ++ uint32_t pb; ++ bool success; ++ ++retry: ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[block_addr]; ++ ++ /* Whether the logic block is good (has valid mapping) */ ++ if ((int32_t)pb < 0) { ++ nlog_debug(ni, "Logic block %u is a bad block\n", block_addr); ++ return -EIO; ++ } ++ ++ /* Remap logic block if current physical block is a bad block */ ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD || ++ nmbm_get_block_state(ni, pb) == BLOCK_ST_NEED_REMAP) ++ goto remap_logic_block; ++ ++ /* Insurance to detect unexpected bad block marked by user */ ++ if (nmbm_check_bad_phys_block(ni, pb)) { ++ nlog_warn(ni, "Found unexpected bad block possibly marked by user\n"); ++ nmbm_set_block_state(ni, pb, BLOCK_ST_BAD); ++ goto remap_logic_block; ++ } ++ ++ success = nmbm_erase_block_and_check(ni, pb); ++ if (success) ++ return 0; ++ ++ /* Mark bad block */ ++ nmbm_mark_phys_bad_block(ni, pb); ++ nmbm_set_block_state(ni, pb, BLOCK_ST_BAD); ++ ++remap_logic_block: ++ /* Try to assign a new block */ ++ success = nmbm_map_block(ni, block_addr); ++ if (!success) { ++ /* Mark logic block unusable, and update info table */ ++ ni->block_mapping[block_addr] = -1; ++ if (nmbm_get_block_state(ni, pb) != BLOCK_ST_NEED_REMAP) ++ nmbm_set_block_state(ni, pb, BLOCK_ST_BAD); ++ nmbm_update_info_table(ni); ++ return -EIO; ++ } ++ ++ /* Update info table before erasing */ ++ if (nmbm_get_block_state(ni, pb) != BLOCK_ST_NEED_REMAP) ++ nmbm_set_block_state(ni, pb, BLOCK_ST_BAD); ++ nmbm_update_info_table(ni); ++ ++ goto retry; ++} ++ ++/* ++ * nmbm_erase_block_range - Erase logic blocks ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @size: erase range ++ * @failed_addr: return failed block address if error occurs ++ */ ++int nmbm_erase_block_range(struct nmbm_instance *ni, uint64_t addr, ++ uint64_t size, uint64_t *failed_addr) ++{ ++ uint32_t start_ba, end_ba; ++ int ret; ++ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ if (addr + size > ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Erase range 0xllxu is too large\n", size); ++ return -EINVAL; ++ } ++ ++ if (!size) { ++ nlog_warn(ni, "No blocks to be erased\n"); ++ return 0; ++ } ++ ++ start_ba = addr2ba(ni, addr); ++ end_ba = addr2ba(ni, addr + size - 1); ++ ++ while (start_ba <= end_ba) { ++ schedule(); ++ ++ ret = nmbm_erase_logic_block(ni, start_ba); ++ if (ret) { ++ if (failed_addr) ++ *failed_addr = ba2addr(ni, start_ba); ++ return ret; ++ } ++ ++ start_ba++; ++ } ++ ++ return 0; ++} ++ ++/* ++ * nmbm_read_logic_page - Read page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer to store main data. optional. ++ * @oob: buffer to store oob data. optional. ++ * @mode: read mode ++ * ++ * Return 0 for success, positive value for corrected bitflip count, ++ * -EBADMSG for ecc error, other negative values for other errors ++ */ ++static int nmbm_read_logic_page(struct nmbm_instance *ni, uint64_t addr, ++ void *data, void *oob, enum nmbm_oob_mode mode) ++{ ++ uint32_t lb, pb, offset; ++ uint64_t paddr; ++ ++ /* Extract block address and in-block offset */ ++ lb = addr2ba(ni, addr); ++ offset = addr & ni->erasesize_mask; ++ ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[lb]; ++ ++ /* Whether the logic block is good (has valid mapping) */ ++ if ((int32_t)pb < 0) { ++ nlog_debug(ni, "Logic block %u is a bad block\n", lb); ++ return -EIO; ++ } ++ ++ /* Fail if physical block is marked bad */ ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD) ++ return -EIO; ++ ++ /* Assemble new address */ ++ paddr = ba2addr(ni, pb) + offset; ++ ++ return nmbm_read_phys_page(ni, paddr, data, oob, mode); ++} ++ ++/* ++ * nmbm_read_single_page - Read one page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer to store main data. optional. ++ * @oob: buffer to store oob data. optional. ++ * @mode: read mode ++ * ++ * Return 0 for success, positive value for corrected bitflip count, ++ * -EBADMSG for ecc error, other negative values for other errors ++ */ ++int nmbm_read_single_page(struct nmbm_instance *ni, uint64_t addr, void *data, ++ void *oob, enum nmbm_oob_mode mode) ++{ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ return nmbm_read_logic_page(ni, addr, data, oob, mode); ++} ++ ++/* ++ * nmbm_read_range - Read data without oob ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @size: data size to read ++ * @data: buffer to store main data to be read ++ * @mode: read mode ++ * @retlen: return actual data size read ++ * ++ * Return 0 for success, positive value for corrected bitflip count, ++ * -EBADMSG for ecc error, other negative values for other errors ++ */ ++int nmbm_read_range(struct nmbm_instance *ni, uint64_t addr, size_t size, ++ void *data, enum nmbm_oob_mode mode, size_t *retlen) ++{ ++ uint64_t off = addr; ++ uint8_t *ptr = data; ++ size_t sizeremain = size, chunksize, leading; ++ bool has_ecc_err = false; ++ int ret, max_bitflips = 0; ++ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ if (addr + size > ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Read range 0x%llx is too large\n", size); ++ return -EINVAL; ++ } ++ ++ if (!size) { ++ nlog_warn(ni, "No data to be read\n"); ++ return 0; ++ } ++ ++ while (sizeremain) { ++ schedule(); ++ ++ leading = off & ni->writesize_mask; ++ chunksize = ni->lower.writesize - leading; ++ if (chunksize > sizeremain) ++ chunksize = sizeremain; ++ ++ if (chunksize == ni->lower.writesize) { ++ ret = nmbm_read_logic_page(ni, off - leading, ptr, ++ NULL, mode); ++ if (ret < 0 && ret != -EBADMSG) ++ break; ++ } else { ++ ret = nmbm_read_logic_page(ni, off - leading, ++ ni->page_cache, NULL, ++ mode); ++ if (ret < 0 && ret != -EBADMSG) ++ break; ++ ++ memcpy(ptr, ni->page_cache + leading, chunksize); ++ } ++ ++ if (ret == -EBADMSG) ++ has_ecc_err = true; ++ ++ if (ret > max_bitflips) ++ max_bitflips = ret; ++ ++ off += chunksize; ++ ptr += chunksize; ++ sizeremain -= chunksize; ++ } ++ ++ if (retlen) ++ *retlen = size - sizeremain; ++ ++ if (ret < 0 && ret != -EBADMSG) ++ return ret; ++ ++ if (has_ecc_err) ++ return -EBADMSG; ++ ++ return max_bitflips; ++} ++ ++/* ++ * nmbm_write_logic_page - Read page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer contains main data. optional. ++ * @oob: buffer contains oob data. optional. ++ * @mode: write mode ++ */ ++static int nmbm_write_logic_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data, const void *oob, ++ enum nmbm_oob_mode mode) ++{ ++ uint32_t lb, pb, offset; ++ uint64_t paddr; ++ bool success; ++ ++ /* Extract block address and in-block offset */ ++ lb = addr2ba(ni, addr); ++ offset = addr & ni->erasesize_mask; ++ ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[lb]; ++ ++ /* Whether the logic block is good (has valid mapping) */ ++ if ((int32_t)pb < 0) { ++ nlog_debug(ni, "Logic block %u is a bad block\n", lb); ++ return -EIO; ++ } ++ ++ /* Fail if physical block is marked bad */ ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD) ++ return -EIO; ++ ++ /* Assemble new address */ ++ paddr = ba2addr(ni, pb) + offset; ++ ++ success = nmbm_write_phys_page(ni, paddr, data, oob, mode); ++ if (success) ++ return 0; ++ ++ /* ++ * Do not remap bad block here. Just mark this block in state table. ++ * Remap this block on erasing. ++ */ ++ nmbm_set_block_state(ni, pb, BLOCK_ST_NEED_REMAP); ++ nmbm_update_info_table(ni); ++ ++ return -EIO; ++} ++ ++/* ++ * nmbm_write_single_page - Write one page based on logic address ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @data: buffer contains main data. optional. ++ * @oob: buffer contains oob data. optional. ++ * @mode: write mode ++ */ ++int nmbm_write_single_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data, const void *oob, ++ enum nmbm_oob_mode mode) ++{ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ return nmbm_write_logic_page(ni, addr, data, oob, mode); ++} ++ ++/* ++ * nmbm_write_range - Write data without oob ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ * @size: data size to write ++ * @data: buffer contains data to be written ++ * @mode: write mode ++ * @retlen: return actual data size written ++ */ ++int nmbm_write_range(struct nmbm_instance *ni, uint64_t addr, size_t size, ++ const void *data, enum nmbm_oob_mode mode, ++ size_t *retlen) ++{ ++ uint64_t off = addr; ++ const uint8_t *ptr = data; ++ size_t sizeremain = size, chunksize, leading; ++ int ret; ++ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ if (addr + size > ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Write size 0x%zx is too large\n", size); ++ return -EINVAL; ++ } ++ ++ if (!size) { ++ nlog_warn(ni, "No data to be written\n"); ++ return 0; ++ } ++ ++ while (sizeremain) { ++ schedule(); ++ ++ leading = off & ni->writesize_mask; ++ chunksize = ni->lower.writesize - leading; ++ if (chunksize > sizeremain) ++ chunksize = sizeremain; ++ ++ if (chunksize == ni->lower.writesize) { ++ ret = nmbm_write_logic_page(ni, off - leading, ptr, ++ NULL, mode); ++ if (ret) ++ break; ++ } else { ++ memset(ni->page_cache, 0xff, leading); ++ memcpy(ni->page_cache + leading, ptr, chunksize); ++ ++ ret = nmbm_write_logic_page(ni, off - leading, ++ ni->page_cache, NULL, ++ mode); ++ if (ret) ++ break; ++ } ++ ++ off += chunksize; ++ ptr += chunksize; ++ sizeremain -= chunksize; ++ } ++ ++ if (retlen) ++ *retlen = size - sizeremain; ++ ++ return ret; ++} ++ ++/* ++ * nmbm_check_bad_block - Check whether a logic block is usable ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ */ ++int nmbm_check_bad_block(struct nmbm_instance *ni, uint64_t addr) ++{ ++ uint32_t lb, pb; ++ ++ if (!ni) ++ return -EINVAL; ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ lb = addr2ba(ni, addr); ++ ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[lb]; ++ ++ if ((int32_t)pb < 0) ++ return 1; ++ ++ if (nmbm_get_block_state(ni, pb) == BLOCK_ST_BAD) ++ return 1; ++ ++ return 0; ++} ++ ++/* ++ * nmbm_mark_bad_block - Mark a logic block unusable ++ * @ni: NMBM instance structure ++ * @addr: logic linear address ++ */ ++int nmbm_mark_bad_block(struct nmbm_instance *ni, uint64_t addr) ++{ ++ uint32_t lb, pb; ++ ++ if (!ni) ++ return -EINVAL; ++ ++ /* Sanity check */ ++ if (ni->protected || (ni->lower.flags & NMBM_F_READ_ONLY)) { ++ nlog_debug(ni, "Device is forced read-only\n"); ++ return -EROFS; ++ } ++ ++ if (addr >= ba2addr(ni, ni->data_block_count)) { ++ nlog_err(ni, "Address 0x%llx is invalid\n", addr); ++ return -EINVAL; ++ } ++ ++ lb = addr2ba(ni, addr); ++ ++ /* Map logic block to physical block */ ++ pb = ni->block_mapping[lb]; ++ ++ if ((int32_t)pb < 0) ++ return 0; ++ ++ ni->block_mapping[lb] = -1; ++ nmbm_mark_phys_bad_block(ni, pb); ++ nmbm_set_block_state(ni, pb, BLOCK_ST_BAD); ++ nmbm_update_info_table(ni); ++ ++ return 0; ++} ++ ++/* ++ * nmbm_get_avail_size - Get available user data size ++ * @ni: NMBM instance structure ++ */ ++uint64_t nmbm_get_avail_size(struct nmbm_instance *ni) ++{ ++ if (!ni) ++ return 0; ++ ++ return (uint64_t)ni->data_block_count << ni->erasesize_shift; ++} ++ ++/* ++ * nmbm_get_lower_device - Get lower device structure ++ * @ni: NMBM instance structure ++ * @nld: pointer to hold the data of lower device structure ++ */ ++int nmbm_get_lower_device(struct nmbm_instance *ni, struct nmbm_lower_device *nld) ++{ ++ if (!ni) ++ return -EINVAL; ++ ++ if (nld) ++ memcpy(nld, &ni->lower, sizeof(*nld)); ++ ++ return 0; ++} ++ ++#include "nmbm-debug.inl" +--- /dev/null ++++ b/drivers/mtd/nmbm/nmbm-debug.h +@@ -0,0 +1,37 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Debug addons for NAND Mapped-block Management (NMBM) ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#ifndef _NMBM_DEBUG_H_ ++#define _NMBM_DEBUG_H_ ++ ++#include "nmbm-private.h" ++ ++#define nmbm_mark_block_color_normal(ni, start_ba, end_ba) ++#define nmbm_mark_block_color_bad(ni, ba) ++#define nmbm_mark_block_color_mgmt(ni, start_ba, end_ba) ++#define nmbm_mark_block_color_signature(ni, ba) ++#define nmbm_mark_block_color_info_table(ni, start_ba, end_ba) ++#define nmbm_mark_block_color_mapped(ni, ba) ++ ++uint32_t nmbm_debug_get_block_state(struct nmbm_instance *ni, uint32_t ba); ++char nmbm_debug_get_phys_block_type(struct nmbm_instance *ni, uint32_t ba); ++ ++enum nmmb_block_type { ++ NMBM_BLOCK_GOOD_DATA, ++ NMBM_BLOCK_GOOD_MGMT, ++ NMBM_BLOCK_BAD, ++ NMBM_BLOCK_MAIN_INFO_TABLE, ++ NMBM_BLOCK_BACKUP_INFO_TABLE, ++ NMBM_BLOCK_REMAPPED, ++ NMBM_BLOCK_SIGNATURE, ++ ++ __NMBM_BLOCK_TYPE_MAX ++}; ++ ++#endif /* _NMBM_DEBUG_H_ */ +--- /dev/null ++++ b/drivers/mtd/nmbm/nmbm-debug.inl +@@ -0,0 +1,39 @@ ++ ++uint32_t nmbm_debug_get_block_state(struct nmbm_instance *ni, uint32_t ba) ++{ ++ return nmbm_get_block_state(ni, ba); ++} ++ ++char nmbm_debug_get_phys_block_type(struct nmbm_instance *ni, uint32_t ba) ++{ ++ uint32_t eba, limit; ++ bool success; ++ ++ if (nmbm_get_block_state(ni, ba) == BLOCK_ST_BAD) ++ return NMBM_BLOCK_BAD; ++ ++ if (ba < ni->data_block_count) ++ return NMBM_BLOCK_GOOD_DATA; ++ ++ if (ba == ni->signature_ba) ++ return NMBM_BLOCK_SIGNATURE; ++ ++ if (ni->main_table_ba) { ++ limit = ni->backup_table_ba ? ni->backup_table_ba : ++ ni->mapping_blocks_ba; ++ ++ success = nmbm_block_walk_asc(ni, ni->main_table_ba, &eba, ++ size2blk(ni, ni->info_table_size), limit); ++ ++ if (success && ba >= ni->main_table_ba && ba < eba) ++ return NMBM_BLOCK_MAIN_INFO_TABLE; ++ } ++ ++ if (ba >= ni->backup_table_ba && ba < ni->mapping_blocks_ba) ++ return NMBM_BLOCK_BACKUP_INFO_TABLE; ++ ++ if (ba > ni->mapping_blocks_top_ba && ba < ni->signature_ba) ++ return NMBM_BLOCK_REMAPPED; ++ ++ return NMBM_BLOCK_GOOD_MGMT; ++} +--- /dev/null ++++ b/drivers/mtd/nmbm/nmbm-private.h +@@ -0,0 +1,137 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Definitions for NAND Mapped-block Management (NMBM) ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#ifndef _NMBM_PRIVATE_H_ ++#define _NMBM_PRIVATE_H_ ++ ++#include <nmbm/nmbm.h> ++ ++#define NMBM_MAGIC_SIGNATURE 0x304d4d4e /* NMM0 */ ++#define NMBM_MAGIC_INFO_TABLE 0x314d4d4e /* NMM1 */ ++ ++#define NMBM_VERSION_MAJOR_S 0 ++#define NMBM_VERSION_MAJOR_M 0xffff ++#define NMBM_VERSION_MINOR_S 16 ++#define NMBM_VERSION_MINOR_M 0xffff ++#define NMBM_VERSION_MAKE(major, minor) (((major) & NMBM_VERSION_MAJOR_M) | \ ++ (((minor) & NMBM_VERSION_MINOR_M) << \ ++ NMBM_VERSION_MINOR_S)) ++#define NMBM_VERSION_MAJOR_GET(ver) (((ver) >> NMBM_VERSION_MAJOR_S) & \ ++ NMBM_VERSION_MAJOR_M) ++#define NMBM_VERSION_MINOR_GET(ver) (((ver) >> NMBM_VERSION_MINOR_S) & \ ++ NMBM_VERSION_MINOR_M) ++ ++typedef uint32_t nmbm_bitmap_t; ++#define NMBM_BITMAP_UNIT_SIZE (sizeof(nmbm_bitmap_t)) ++#define NMBM_BITMAP_BITS_PER_BLOCK 2 ++#define NMBM_BITMAP_BITS_PER_UNIT (8 * sizeof(nmbm_bitmap_t)) ++#define NMBM_BITMAP_BLOCKS_PER_UNIT (NMBM_BITMAP_BITS_PER_UNIT / \ ++ NMBM_BITMAP_BITS_PER_BLOCK) ++ ++#define NMBM_SPARE_BLOCK_MULTI 1 ++#define NMBM_SPARE_BLOCK_DIV 2 ++#define NMBM_SPARE_BLOCK_MIN 2 ++ ++#define NMBM_MGMT_DIV 16 ++#define NMBM_MGMT_BLOCKS_MIN 32 ++ ++#define NMBM_TRY_COUNT 3 ++ ++#define BLOCK_ST_BAD 0 ++#define BLOCK_ST_NEED_REMAP 2 ++#define BLOCK_ST_GOOD 3 ++#define BLOCK_ST_MASK 3 ++ ++struct nmbm_header { ++ uint32_t magic; ++ uint32_t version; ++ uint32_t size; ++ uint32_t checksum; ++}; ++ ++struct nmbm_signature { ++ struct nmbm_header header; ++ uint64_t nand_size; ++ uint32_t block_size; ++ uint32_t page_size; ++ uint32_t spare_size; ++ uint32_t mgmt_start_pb; ++ uint8_t max_try_count; ++ uint8_t padding[3]; ++}; ++ ++struct nmbm_info_table_header { ++ struct nmbm_header header; ++ uint32_t write_count; ++ uint32_t state_table_off; ++ uint32_t mapping_table_off; ++ uint32_t padding; ++}; ++ ++struct nmbm_instance { ++ struct nmbm_lower_device lower; ++ ++ uint32_t rawpage_size; ++ uint32_t rawblock_size; ++ uint32_t rawchip_size; ++ ++ uint32_t writesize_mask; ++ uint32_t erasesize_mask; ++ uint16_t writesize_shift; ++ uint16_t erasesize_shift; ++ ++ struct nmbm_signature signature; ++ ++ uint8_t *info_table_cache; ++ uint32_t info_table_size; ++ uint32_t info_table_spare_blocks; ++ struct nmbm_info_table_header info_table; ++ ++ nmbm_bitmap_t *block_state; ++ uint32_t block_state_changed; ++ uint32_t state_table_size; ++ ++ int32_t *block_mapping; ++ uint32_t block_mapping_changed; ++ uint32_t mapping_table_size; ++ ++ uint8_t *page_cache; ++ ++ int protected; ++ ++ uint32_t block_count; ++ uint32_t data_block_count; ++ ++ uint32_t mgmt_start_ba; ++ uint32_t main_table_ba; ++ uint32_t backup_table_ba; ++ uint32_t mapping_blocks_ba; ++ uint32_t mapping_blocks_top_ba; ++ uint32_t signature_ba; ++ ++ enum nmbm_log_category log_display_level; ++}; ++ ++/* Log utilities */ ++#define nlog_debug(ni, fmt, ...) \ ++ nmbm_log(ni, NMBM_LOG_DEBUG, fmt, ##__VA_ARGS__) ++ ++#define nlog_info(ni, fmt, ...) \ ++ nmbm_log(ni, NMBM_LOG_INFO, fmt, ##__VA_ARGS__) ++ ++#define nlog_warn(ni, fmt, ...) \ ++ nmbm_log(ni, NMBM_LOG_WARN, fmt, ##__VA_ARGS__) ++ ++#define nlog_err(ni, fmt, ...) \ ++ nmbm_log(ni, NMBM_LOG_ERR, fmt, ##__VA_ARGS__) ++ ++#define nlog_emerg(ni, fmt, ...) \ ++ nmbm_log(ni, NMBM_LOG_EMERG, fmt, ##__VA_ARGS__) ++ ++#endif /* _NMBM_PRIVATE_H_ */ +--- /dev/null ++++ b/include/nmbm/nmbm-os.h +@@ -0,0 +1,66 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * OS-dependent definitions for NAND Mapped-block Management (NMBM) ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#ifndef _NMBM_OS_H_ ++#define _NMBM_OS_H_ ++ ++#include <div64.h> ++#include <stdbool.h> ++#include <watchdog.h> ++#include <u-boot/crc.h> ++#include <linux/errno.h> ++#include <linux/log2.h> ++#include <linux/types.h> ++ ++static inline uint32_t nmbm_crc32(uint32_t crcval, const void *buf, size_t size) ++{ ++ uint chksz; ++ const unsigned char *p = buf; ++ ++ while (size) { ++ if (size > UINT_MAX) ++ chksz = UINT_MAX; ++ else ++ chksz = (uint)size; ++ ++ crcval = crc32_no_comp(crcval, p, chksz); ++ size -= chksz; ++ p += chksz; ++ } ++ ++ return crcval; ++} ++ ++static inline uint32_t nmbm_lldiv(uint64_t dividend, uint32_t divisor) ++{ ++#if BITS_PER_LONG == 64 ++ return dividend / divisor; ++#else ++ __div64_32(÷nd, divisor); ++ return dividend; ++#endif ++} ++ ++#ifdef CONFIG_NMBM_LOG_LEVEL_DEBUG ++#define NMBM_DEFAULT_LOG_LEVEL 0 ++#elif defined(NMBM_LOG_LEVEL_INFO) ++#define NMBM_DEFAULT_LOG_LEVEL 1 ++#elif defined(NMBM_LOG_LEVEL_WARN) ++#define NMBM_DEFAULT_LOG_LEVEL 2 ++#elif defined(NMBM_LOG_LEVEL_ERR) ++#define NMBM_DEFAULT_LOG_LEVEL 3 ++#elif defined(NMBM_LOG_LEVEL_EMERG) ++#define NMBM_DEFAULT_LOG_LEVEL 4 ++#elif defined(NMBM_LOG_LEVEL_NONE) ++#define NMBM_DEFAULT_LOG_LEVEL 5 ++#else ++#define NMBM_DEFAULT_LOG_LEVEL 1 ++#endif ++ ++#endif /* _NMBM_OS_H_ */ +--- /dev/null ++++ b/include/nmbm/nmbm.h +@@ -0,0 +1,102 @@ ++/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Definitions for NAND Mapped-block Management (NMBM) ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#ifndef _NMBM_H_ ++#define _NMBM_H_ ++ ++#include <nmbm/nmbm-os.h> ++ ++enum nmbm_log_category { ++ NMBM_LOG_DEBUG, ++ NMBM_LOG_INFO, ++ NMBM_LOG_WARN, ++ NMBM_LOG_ERR, ++ NMBM_LOG_EMERG, ++ ++ __NMBM_LOG_MAX ++}; ++ ++enum nmbm_oob_mode { ++ NMBM_MODE_PLACE_OOB, ++ NMBM_MODE_AUTO_OOB, ++ NMBM_MODE_RAW, ++ ++ __NMBM_MODE_MAX ++}; ++ ++struct nmbm_lower_device { ++ uint32_t max_ratio; ++ uint32_t max_reserved_blocks; ++ int flags; ++ ++ uint64_t size; ++ uint32_t erasesize; ++ uint32_t writesize; ++ uint32_t oobsize; ++ uint32_t oobavail; ++ ++ void *arg; ++ int (*reset_chip)(void *arg); ++ ++ /* ++ * read_page: ++ * return 0 if succeeds ++ * return positive number for ecc error ++ * return negative number for other errors ++ */ ++ int (*read_page)(void *arg, uint64_t addr, void *buf, void *oob, enum nmbm_oob_mode mode); ++ int (*write_page)(void *arg, uint64_t addr, const void *buf, const void *oob, enum nmbm_oob_mode mode); ++ int (*erase_block)(void *arg, uint64_t addr); ++ ++ int (*is_bad_block)(void *arg, uint64_t addr); ++ int (*mark_bad_block)(void *arg, uint64_t addr); ++ ++ /* OS-dependent logging function */ ++ void (*logprint)(void *arg, enum nmbm_log_category level, const char *fmt, va_list ap); ++}; ++ ++struct nmbm_instance; ++ ++/* Create NMBM if management area not found, or not complete */ ++#define NMBM_F_CREATE 0x01 ++ ++/* Empty page is also protected by ECC, and bitflip(s) can be corrected */ ++#define NMBM_F_EMPTY_PAGE_ECC_OK 0x02 ++ ++/* Do not write anything back to flash */ ++#define NMBM_F_READ_ONLY 0x04 ++ ++size_t nmbm_calc_structure_size(struct nmbm_lower_device *nld); ++int nmbm_attach(struct nmbm_lower_device *nld, struct nmbm_instance *ni); ++int nmbm_detach(struct nmbm_instance *ni); ++ ++enum nmbm_log_category nmbm_set_log_level(struct nmbm_instance *ni, ++ enum nmbm_log_category level); ++ ++int nmbm_erase_block_range(struct nmbm_instance *ni, uint64_t addr, ++ uint64_t size, uint64_t *failed_addr); ++int nmbm_read_single_page(struct nmbm_instance *ni, uint64_t addr, void *data, ++ void *oob, enum nmbm_oob_mode mode); ++int nmbm_read_range(struct nmbm_instance *ni, uint64_t addr, size_t size, ++ void *data, enum nmbm_oob_mode mode, size_t *retlen); ++int nmbm_write_single_page(struct nmbm_instance *ni, uint64_t addr, ++ const void *data, const void *oob, ++ enum nmbm_oob_mode mode); ++int nmbm_write_range(struct nmbm_instance *ni, uint64_t addr, size_t size, ++ const void *data, enum nmbm_oob_mode mode, ++ size_t *retlen); ++ ++int nmbm_check_bad_block(struct nmbm_instance *ni, uint64_t addr); ++int nmbm_mark_bad_block(struct nmbm_instance *ni, uint64_t addr); ++ ++uint64_t nmbm_get_avail_size(struct nmbm_instance *ni); ++ ++int nmbm_get_lower_device(struct nmbm_instance *ni, struct nmbm_lower_device *nld); ++ ++#endif /* _NMBM_H_ */ diff --git a/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch b/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch new file mode 100644 index 00000000000..718f00e7641 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-07-mtd-nmbm-add-support-for-mtd.patch @@ -0,0 +1,958 @@ +From 0524995f07fcd216a1a7e267fdb5cf2b0ede8489 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:42:12 +0800 +Subject: [PATCH 41/71] mtd: nmbm: add support for mtd + +Add support to create NMBM based on MTD devices + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/nmbm/Kconfig | 5 + + drivers/mtd/nmbm/Makefile | 1 + + drivers/mtd/nmbm/nmbm-mtd.c | 890 ++++++++++++++++++++++++++++++++++++ + include/nmbm/nmbm-mtd.h | 27 ++ + 4 files changed, 923 insertions(+) + create mode 100644 drivers/mtd/nmbm/nmbm-mtd.c + create mode 100644 include/nmbm/nmbm-mtd.h + +--- a/drivers/mtd/nmbm/Kconfig ++++ b/drivers/mtd/nmbm/Kconfig +@@ -27,3 +27,8 @@ config NMBM_LOG_LEVEL_NONE + bool "5 - None" + + endchoice ++ ++config NMBM_MTD ++ bool "Enable MTD based NAND mapping block management" ++ default n ++ depends on NMBM +--- a/drivers/mtd/nmbm/Makefile ++++ b/drivers/mtd/nmbm/Makefile +@@ -3,3 +3,4 @@ + # (C) Copyright 2020 MediaTek Inc. All rights reserved. + + obj-$(CONFIG_NMBM) += nmbm-core.o ++obj-$(CONFIG_NMBM_MTD) += nmbm-mtd.o +--- /dev/null ++++ b/drivers/mtd/nmbm/nmbm-mtd.c +@@ -0,0 +1,890 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include <linux/list.h> ++#include <linux/bitops.h> ++#include <linux/kernel.h> ++#include <linux/types.h> ++#include <linux/mtd/mtd.h> ++#include <jffs2/load_kernel.h> ++#include <watchdog.h> ++ ++#include "nmbm-debug.h" ++ ++#define NMBM_UPPER_MTD_NAME "nmbm" ++ ++static uint32_t nmbm_id_cnt; ++static LIST_HEAD(nmbm_devs); ++ ++struct nmbm_mtd { ++ struct mtd_info upper; ++ char *name; ++ uint32_t id; ++ ++ struct mtd_info *lower; ++ ++ struct nmbm_instance *ni; ++ uint8_t *page_cache; ++ ++ struct list_head node; ++}; ++ ++static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob, ++ enum nmbm_oob_mode mode) ++{ ++ struct nmbm_mtd *nm = arg; ++ struct mtd_oob_ops ops; ++ int ret; ++ ++ memset(&ops, 0, sizeof(ops)); ++ ++ switch (mode) { ++ case NMBM_MODE_PLACE_OOB: ++ ops.mode = MTD_OPS_PLACE_OOB; ++ break; ++ case NMBM_MODE_AUTO_OOB: ++ ops.mode = MTD_OPS_AUTO_OOB; ++ break; ++ case NMBM_MODE_RAW: ++ ops.mode = MTD_OPS_RAW; ++ break; ++ default: ++ pr_debug("%s: unsupported NMBM mode: %u\n", __func__, mode); ++ return -ENOTSUPP; ++ } ++ ++ if (buf) { ++ ops.datbuf = buf; ++ ops.len = nm->lower->writesize; ++ } ++ ++ if (oob) { ++ ops.oobbuf = oob; ++ ops.ooblen = mtd_oobavail(nm->lower, &ops); ++ } ++ ++ ret = mtd_read_oob(nm->lower, addr, &ops); ++ nm->upper.ecc_stats.corrected = nm->lower->ecc_stats.corrected; ++ nm->upper.ecc_stats.failed = nm->lower->ecc_stats.failed; ++ ++ /* Report error on failure (including ecc error) */ ++ if (ret < 0 && ret != -EUCLEAN) ++ return ret; ++ ++ /* ++ * Since mtd_read_oob() won't report exact bitflips, what we can know ++ * is whether bitflips exceeds the threshold. ++ * We want the -EUCLEAN to be passed to the upper layer, but not the ++ * error value itself. To achieve this, report bitflips above the ++ * threshold. ++ */ ++ ++ if (ret == -EUCLEAN) { ++ return min_t(u32, nm->lower->bitflip_threshold + 1, ++ nm->lower->ecc_strength); ++ } ++ ++ /* For bitflips less than the threshold, return 0 */ ++ ++ return 0; ++} ++ ++static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf, ++ const void *oob, enum nmbm_oob_mode mode) ++{ ++ struct nmbm_mtd *nm = arg; ++ struct mtd_oob_ops ops; ++ ++ memset(&ops, 0, sizeof(ops)); ++ ++ switch (mode) { ++ case NMBM_MODE_PLACE_OOB: ++ ops.mode = MTD_OPS_PLACE_OOB; ++ break; ++ case NMBM_MODE_AUTO_OOB: ++ ops.mode = MTD_OPS_AUTO_OOB; ++ break; ++ case NMBM_MODE_RAW: ++ ops.mode = MTD_OPS_RAW; ++ break; ++ default: ++ pr_debug("%s: unsupported NMBM mode: %u\n", __func__, mode); ++ return -ENOTSUPP; ++ } ++ ++ if (buf) { ++ ops.datbuf = (uint8_t *)buf; ++ ops.len = nm->lower->writesize; ++ } ++ ++ if (oob) { ++ ops.oobbuf = (uint8_t *)oob; ++ ops.ooblen = mtd_oobavail(nm->lower, &ops); ++ } ++ ++ return mtd_write_oob(nm->lower, addr, &ops); ++} ++ ++static int nmbm_lower_erase_block(void *arg, uint64_t addr) ++{ ++ struct nmbm_mtd *nm = arg; ++ struct erase_info ei; ++ ++ memset(&ei, 0, sizeof(ei)); ++ ++ ei.mtd = nm->lower; ++ ei.addr = addr; ++ ei.len = nm->lower->erasesize; ++ ++ return mtd_erase(nm->lower, &ei); ++} ++ ++static int nmbm_lower_is_bad_block(void *arg, uint64_t addr) ++{ ++ struct nmbm_mtd *nm = arg; ++ ++ return mtd_block_isbad(nm->lower, addr); ++} ++ ++static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr) ++{ ++ struct nmbm_mtd *nm = arg; ++ ++ return mtd_block_markbad(nm->lower, addr); ++} ++ ++static void nmbm_lower_log(void *arg, enum nmbm_log_category level, ++ const char *fmt, va_list ap) ++{ ++ vprintf(fmt, ap); ++} ++ ++static int nmbm_mtd_read(struct mtd_info *mtd, loff_t from, size_t len, ++ size_t *retlen, u_char *buf) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ ++ /* Do not allow read past end of device */ ++ if ((from + len) > mtd->size) { ++ pr_debug("%s: attempt to write beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ return nmbm_read_range(nm->ni, from, len, buf, MTD_OPS_PLACE_OOB, ++ retlen); ++} ++ ++static int nmbm_mtd_write(struct mtd_info *mtd, loff_t to, size_t len, ++ size_t *retlen, const u_char *buf) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ ++ /* Do not allow write past end of device */ ++ if ((to + len) > mtd->size) { ++ pr_debug("%s: attempt to write beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ return nmbm_write_range(nm->ni, to, len, buf, MTD_OPS_PLACE_OOB, ++ retlen); ++} ++ ++static int nmbm_mtd_erase(struct mtd_info *mtd, struct erase_info *instr) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ int ret; ++ ++ instr->state = MTD_ERASING; ++ ++ ret = nmbm_erase_block_range(nm->ni, instr->addr, instr->len, ++ &instr->fail_addr); ++ if (ret) ++ instr->state = MTD_ERASE_FAILED; ++ else ++ instr->state = MTD_ERASE_DONE; ++ ++ if (!ret) ++ /* FIXME */ ++ /* mtd_erase_callback(instr); */ ++ return ret; ++ else ++ ret = -EIO; ++ ++ return ret; ++} ++ ++static int nmbm_mtd_read_data(struct nmbm_mtd *nm, uint64_t addr, ++ struct mtd_oob_ops *ops, enum nmbm_oob_mode mode) ++{ ++ size_t len, ooblen, maxooblen, chklen; ++ uint32_t col, ooboffs; ++ uint8_t *datcache, *oobcache; ++ bool has_ecc_err = false; ++ int ret, max_bitflips = 0; ++ ++ col = addr & nm->lower->writesize_mask; ++ addr &= ~nm->lower->writesize_mask; ++ maxooblen = mtd_oobavail(nm->lower, ops); ++ ooboffs = ops->ooboffs; ++ ooblen = ops->ooblen; ++ len = ops->len; ++ ++ datcache = len ? nm->page_cache : NULL; ++ oobcache = ooblen ? nm->page_cache + nm->lower->writesize : NULL; ++ ++ ops->oobretlen = 0; ++ ops->retlen = 0; ++ ++ while (len || ooblen) { ++ schedule(); ++ ++ ret = nmbm_read_single_page(nm->ni, addr, datcache, oobcache, ++ mode); ++ if (ret < 0 && ret != -EBADMSG) ++ return ret; ++ ++ /* Continue reading on ecc error */ ++ if (ret == -EBADMSG) ++ has_ecc_err = true; ++ ++ /* Record the maximum bitflips between pages */ ++ if (ret > max_bitflips) ++ max_bitflips = ret; ++ ++ if (len) { ++ /* Move data */ ++ chklen = nm->lower->writesize - col; ++ if (chklen > len) ++ chklen = len; ++ ++ memcpy(ops->datbuf + ops->retlen, datcache + col, ++ chklen); ++ len -= chklen; ++ col = 0; /* (col + chklen) % */ ++ ops->retlen += chklen; ++ } ++ ++ if (ooblen) { ++ /* Move oob */ ++ chklen = maxooblen - ooboffs; ++ if (chklen > ooblen) ++ chklen = ooblen; ++ ++ memcpy(ops->oobbuf + ops->oobretlen, oobcache + ooboffs, ++ chklen); ++ ooblen -= chklen; ++ ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ ++ ops->oobretlen += chklen; ++ } ++ ++ addr += nm->lower->writesize; ++ } ++ ++ if (has_ecc_err) ++ return -EBADMSG; ++ ++ return max_bitflips; ++} ++ ++static int nmbm_mtd_read_oob(struct mtd_info *mtd, loff_t from, ++ struct mtd_oob_ops *ops) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ uint32_t maxooblen; ++ enum nmbm_oob_mode mode; ++ ++ if (!ops->oobbuf && !ops->datbuf) { ++ if (ops->ooblen || ops->len) ++ return -EINVAL; ++ ++ return 0; ++ } ++ ++ switch (ops->mode) { ++ case MTD_OPS_PLACE_OOB: ++ mode = NMBM_MODE_PLACE_OOB; ++ break; ++ case MTD_OPS_AUTO_OOB: ++ mode = NMBM_MODE_AUTO_OOB; ++ break; ++ case MTD_OPS_RAW: ++ mode = NMBM_MODE_RAW; ++ break; ++ default: ++ pr_debug("%s: unsupported oob mode: %u\n", __func__, ops->mode); ++ return -ENOTSUPP; ++ } ++ ++ maxooblen = mtd_oobavail(mtd, ops); ++ ++ /* Do not allow read past end of device */ ++ if (ops->datbuf && (from + ops->len) > mtd->size) { ++ pr_debug("%s: attempt to read beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ if (!ops->oobbuf) { ++ /* Optimized for reading data only */ ++ return nmbm_read_range(nm->ni, from, ops->len, ops->datbuf, ++ mode, &ops->retlen); ++ } ++ ++ if (unlikely(ops->ooboffs >= maxooblen)) { ++ pr_debug("%s: attempt to start read outside oob\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely(from >= mtd->size || ++ ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) - ++ (from >> mtd->writesize_shift)) * maxooblen)) { ++ pr_debug("%s: attempt to read beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ return nmbm_mtd_read_data(nm, from, ops, mode); ++} ++ ++static int nmbm_mtd_write_data(struct nmbm_mtd *nm, uint64_t addr, ++ struct mtd_oob_ops *ops, enum nmbm_oob_mode mode) ++{ ++ size_t len, ooblen, maxooblen, chklen; ++ uint32_t col, ooboffs; ++ uint8_t *datcache, *oobcache; ++ int ret; ++ ++ col = addr & nm->lower->writesize_mask; ++ addr &= ~nm->lower->writesize_mask; ++ maxooblen = mtd_oobavail(nm->lower, ops); ++ ooboffs = ops->ooboffs; ++ ooblen = ops->ooblen; ++ len = ops->len; ++ ++ datcache = len ? nm->page_cache : NULL; ++ oobcache = ooblen ? nm->page_cache + nm->lower->writesize : NULL; ++ ++ ops->oobretlen = 0; ++ ops->retlen = 0; ++ ++ while (len || ooblen) { ++ schedule(); ++ ++ if (len) { ++ /* Move data */ ++ chklen = nm->lower->writesize - col; ++ if (chklen > len) ++ chklen = len; ++ ++ memset(datcache, 0xff, col); ++ memcpy(datcache + col, ops->datbuf + ops->retlen, ++ chklen); ++ memset(datcache + col + chklen, 0xff, ++ nm->lower->writesize - col - chklen); ++ len -= chklen; ++ col = 0; /* (col + chklen) % */ ++ ops->retlen += chklen; ++ } ++ ++ if (ooblen) { ++ /* Move oob */ ++ chklen = maxooblen - ooboffs; ++ if (chklen > ooblen) ++ chklen = ooblen; ++ ++ memset(oobcache, 0xff, ooboffs); ++ memcpy(oobcache + ooboffs, ++ ops->oobbuf + ops->oobretlen, chklen); ++ memset(oobcache + ooboffs + chklen, 0xff, ++ nm->lower->oobsize - ooboffs - chklen); ++ ooblen -= chklen; ++ ooboffs = 0; /* (ooboffs + chklen) % maxooblen; */ ++ ops->oobretlen += chklen; ++ } ++ ++ ret = nmbm_write_single_page(nm->ni, addr, datcache, oobcache, ++ mode); ++ if (ret) ++ return ret; ++ ++ addr += nm->lower->writesize; ++ } ++ ++ return 0; ++} ++ ++static int nmbm_mtd_write_oob(struct mtd_info *mtd, loff_t to, ++ struct mtd_oob_ops *ops) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ enum nmbm_oob_mode mode; ++ uint32_t maxooblen; ++ ++ if (!ops->oobbuf && !ops->datbuf) { ++ if (ops->ooblen || ops->len) ++ return -EINVAL; ++ ++ return 0; ++ } ++ ++ switch (ops->mode) { ++ case MTD_OPS_PLACE_OOB: ++ mode = NMBM_MODE_PLACE_OOB; ++ break; ++ case MTD_OPS_AUTO_OOB: ++ mode = NMBM_MODE_AUTO_OOB; ++ break; ++ case MTD_OPS_RAW: ++ mode = NMBM_MODE_RAW; ++ break; ++ default: ++ pr_debug("%s: unsupported oob mode: %u\n", __func__, ++ ops->mode); ++ return -ENOTSUPP; ++ } ++ ++ maxooblen = mtd_oobavail(mtd, ops); ++ ++ /* Do not allow write past end of device */ ++ if (ops->datbuf && (to + ops->len) > mtd->size) { ++ pr_debug("%s: attempt to write beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ if (!ops->oobbuf) { ++ /* Optimized for writing data only */ ++ return nmbm_write_range(nm->ni, to, ops->len, ops->datbuf, ++ mode, &ops->retlen); ++ } ++ ++ if (unlikely(ops->ooboffs >= maxooblen)) { ++ pr_debug("%s: attempt to start write outside oob\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ if (unlikely(to >= mtd->size || ++ ops->ooboffs + ops->ooblen > ((mtd->size >> mtd->writesize_shift) - ++ (to >> mtd->writesize_shift)) * maxooblen)) { ++ pr_debug("%s: attempt to write beyond end of device\n", ++ __func__); ++ return -EINVAL; ++ } ++ ++ return nmbm_mtd_write_data(nm, to, ops, mode); ++} ++ ++static int nmbm_mtd_block_isbad(struct mtd_info *mtd, loff_t offs) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ ++ return nmbm_check_bad_block(nm->ni, offs); ++} ++ ++static int nmbm_mtd_block_markbad(struct mtd_info *mtd, loff_t offs) ++{ ++ struct nmbm_mtd *nm = container_of(mtd, struct nmbm_mtd, upper); ++ ++ return nmbm_mark_bad_block(nm->ni, offs); ++} ++ ++int nmbm_attach_mtd(struct mtd_info *lower, int flags, uint32_t max_ratio, ++ uint32_t max_reserved_blocks, struct mtd_info **upper) ++{ ++ struct nmbm_lower_device nld; ++ struct nmbm_instance *ni; ++ struct mtd_info *mtd; ++ struct nmbm_mtd *nm; ++ size_t namelen, alloc_size; ++ int ret; ++ ++ if (!lower) ++ return -EINVAL; ++ ++ if (lower->type != MTD_NANDFLASH || lower->flags != MTD_CAP_NANDFLASH) ++ return -ENOTSUPP; ++ ++ namelen = strlen(NMBM_UPPER_MTD_NAME) + 16; ++ ++ nm = calloc(sizeof(*nm) + lower->writesize + lower->oobsize + namelen + 1, 1); ++ if (!nm) ++ return -ENOMEM; ++ ++ nm->lower = lower; ++ nm->name = (char *)nm + sizeof(*nm); ++ nm->page_cache = (uint8_t *)nm->name + namelen + 1; ++ ++ nm->id = nmbm_id_cnt++; ++ snprintf(nm->name, namelen + 1, "%s%u", NMBM_UPPER_MTD_NAME, nm->id); ++ ++ memset(&nld, 0, sizeof(nld)); ++ ++ nld.flags = flags; ++ nld.max_ratio = max_ratio; ++ nld.max_reserved_blocks = max_reserved_blocks; ++ ++ nld.size = lower->size; ++ nld.erasesize = lower->erasesize; ++ nld.writesize = lower->writesize; ++ nld.oobsize = lower->oobsize; ++ nld.oobavail = lower->oobavail; ++ ++ nld.arg = nm; ++ nld.read_page = nmbm_lower_read_page; ++ nld.write_page = nmbm_lower_write_page; ++ nld.erase_block = nmbm_lower_erase_block; ++ nld.is_bad_block = nmbm_lower_is_bad_block; ++ nld.mark_bad_block = nmbm_lower_mark_bad_block; ++ ++ nld.logprint = nmbm_lower_log; ++ ++ alloc_size = nmbm_calc_structure_size(&nld); ++ ni = calloc(alloc_size, 1); ++ if (!ni) { ++ free(nm); ++ return -ENOMEM; ++ } ++ ++ ret = nmbm_attach(&nld, ni); ++ if (ret) { ++ free(ni); ++ free(nm); ++ return ret; ++ } ++ ++ nm->ni = ni; ++ ++ /* Initialize upper mtd */ ++ mtd = &nm->upper; ++ ++ mtd->name = nm->name; ++ mtd->type = MTD_DEV_TYPE_NMBM; ++ mtd->flags = lower->flags; ++ ++ mtd->size = (uint64_t)ni->data_block_count * ni->lower.erasesize; ++ mtd->erasesize = lower->erasesize; ++ mtd->writesize = lower->writesize; ++ mtd->writebufsize = lower->writesize; ++ mtd->oobsize = lower->oobsize; ++ mtd->oobavail = lower->oobavail; ++ ++ mtd->erasesize_shift = lower->erasesize_shift; ++ mtd->writesize_shift = lower->writesize_shift; ++ mtd->erasesize_mask = lower->erasesize_mask; ++ mtd->writesize_mask = lower->writesize_mask; ++ ++ mtd->bitflip_threshold = lower->bitflip_threshold; ++ ++ /* XXX: should this be duplicated? */ ++ mtd->ooblayout = lower->ooblayout; ++ mtd->ecclayout = lower->ecclayout; ++ ++ mtd->ecc_step_size = lower->ecc_step_size; ++ mtd->ecc_strength = lower->ecc_strength; ++ ++ mtd->numeraseregions = lower->numeraseregions; ++ mtd->eraseregions = lower->eraseregions; ++ ++ mtd->_read = nmbm_mtd_read; ++ mtd->_write = nmbm_mtd_write; ++ mtd->_erase = nmbm_mtd_erase; ++ mtd->_read_oob = nmbm_mtd_read_oob; ++ mtd->_write_oob = nmbm_mtd_write_oob; ++ mtd->_block_isbad = nmbm_mtd_block_isbad; ++ mtd->_block_markbad = nmbm_mtd_block_markbad; ++ ++ *upper = mtd; ++ ++ list_add_tail(&nm->node, &nmbm_devs); ++ ++ return 0; ++} ++ ++int nmbm_free_mtd(struct mtd_info *upper) ++{ ++ struct nmbm_mtd *pos; ++ ++ if (!upper) ++ return -EINVAL; ++ ++ list_for_each_entry(pos, &nmbm_devs, node) { ++ if (&pos->upper == upper) { ++ list_del(&pos->node); ++ ++ nmbm_detach(pos->ni); ++ free(pos->ni); ++ free(pos); ++ ++ return 0; ++ } ++ } ++ ++ return -ENODEV; ++} ++ ++struct mtd_info *nmbm_mtd_get_upper_by_index(uint32_t index) ++{ ++ struct nmbm_mtd *nm; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (nm->id == index) ++ return &nm->upper; ++ } ++ ++ return NULL; ++} ++ ++struct mtd_info *nmbm_mtd_get_upper(struct mtd_info *lower) ++{ ++ struct nmbm_mtd *nm; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (nm->lower == lower) ++ return &nm->upper; ++ } ++ ++ return NULL; ++} ++ ++void nmbm_mtd_list_devices(void) ++{ ++ struct nmbm_mtd *nm; ++ ++ printf("Index NMBM device Lower device\n"); ++ printf("========================================\n"); ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ printf("%-8u%-20s%s\n", nm->id, nm->name, nm->lower->name); ++ } ++} ++ ++int nmbm_mtd_print_info(const char *name) ++{ ++ struct nmbm_mtd *nm; ++ bool found = false; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (!strcmp(nm->name, name)) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ printf("Error: NMBM device '%s' not found\n", name); ++ return -ENODEV; ++ } ++ ++ printf("%s:\n", name); ++ printf("Total blocks: %u\n", nm->ni->block_count); ++ printf("Data blocks: %u\n", nm->ni->data_block_count); ++ printf("Management start block: %u\n", nm->ni->mgmt_start_ba); ++ printf("Info table size: 0x%x\n", nm->ni->info_table_size); ++ ++ if (nm->ni->main_table_ba) ++ printf("Main info table start block: %u\n", nm->ni->main_table_ba); ++ else ++ printf("Main info table start block: Not exist\n"); ++ ++ if (nm->ni->backup_table_ba) ++ printf("Backup info table start block: %u\n", nm->ni->backup_table_ba); ++ else ++ printf("Backup info table start block: Not exist\n"); ++ ++ printf("Signature block: %u\n", nm->ni->signature_ba); ++ printf("Mapping blocks top address: %u\n", nm->ni->mapping_blocks_top_ba); ++ printf("Mapping blocks limit address: %u\n", nm->ni->mapping_blocks_ba); ++ ++ return 0; ++} ++ ++static const char nmbm_block_legends[] = { ++ [NMBM_BLOCK_GOOD_DATA] = '-', ++ [NMBM_BLOCK_GOOD_MGMT] = '+', ++ [NMBM_BLOCK_BAD] = 'B', ++ [NMBM_BLOCK_MAIN_INFO_TABLE] = 'I', ++ [NMBM_BLOCK_BACKUP_INFO_TABLE] = 'i', ++ [NMBM_BLOCK_REMAPPED] = 'M', ++ [NMBM_BLOCK_SIGNATURE] = 'S', ++}; ++ ++int nmbm_mtd_print_states(const char *name) ++{ ++ struct nmbm_mtd *nm; ++ enum nmmb_block_type bt; ++ bool found = false; ++ uint32_t i; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (!strcmp(nm->name, name)) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ printf("Error: NMBM device '%s' not found\n", name); ++ return -ENODEV; ++ } ++ ++ printf("Physical blocks:\n"); ++ printf("\n"); ++ ++ printf("Legends:\n"); ++ printf(" - Good data block\n"); ++ printf(" + Good management block\n"); ++ printf(" B Bad block\n"); ++ printf(" I Main info table\n"); ++ printf(" i Backup info table\n"); ++ printf(" M Remapped spare block\n"); ++ printf(" S Signature block\n"); ++ printf("\n"); ++ ++ for (i = 0; i < nm->ni->block_count; i++) { ++ if (i % 64 == 0) ++ printf(" "); ++ ++ bt = nmbm_debug_get_phys_block_type(nm->ni, i); ++ if (bt < __NMBM_BLOCK_TYPE_MAX) ++ putc(nmbm_block_legends[bt]); ++ else ++ putc('?'); ++ ++ if (i % 64 == 63) ++ printf("\n"); ++ } ++ ++ printf("\n"); ++ printf("Logical blocks:\n"); ++ printf("\n"); ++ ++ printf("Legends:\n"); ++ printf(" - Good block\n"); ++ printf(" + Initially remapped block\n"); ++ printf(" M Remapped block\n"); ++ printf(" B Bad/Unmapped block\n"); ++ printf("\n"); ++ ++ for (i = 0; i < nm->ni->data_block_count; i++) { ++ if (i % 64 == 0) ++ printf(" "); ++ ++ if (nm->ni->block_mapping[i] < 0) ++ putc('B'); ++ else if (nm->ni->block_mapping[i] == i) ++ putc('-'); ++ else if (nm->ni->block_mapping[i] < nm->ni->data_block_count) ++ putc('+'); ++ else if (nm->ni->block_mapping[i] > nm->ni->mapping_blocks_top_ba && ++ nm->ni->block_mapping[i] < nm->ni->signature_ba) ++ putc('M'); ++ else ++ putc('?'); ++ ++ if (i % 64 == 63) ++ printf("\n"); ++ } ++ ++ return 0; ++} ++ ++int nmbm_mtd_print_bad_blocks(const char *name) ++{ ++ struct nmbm_mtd *nm; ++ bool found = false; ++ uint32_t i; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (!strcmp(nm->name, name)) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ printf("Error: NMBM device '%s' not found\n", name); ++ return -ENODEV; ++ } ++ ++ printf("Physical blocks:\n"); ++ ++ for (i = 0; i < nm->ni->block_count; i++) { ++ switch (nmbm_debug_get_block_state(nm->ni, i)) { ++ case BLOCK_ST_BAD: ++ printf("%-12u [0x%08llx] - Bad\n", i, ++ (uint64_t)i << nm->ni->erasesize_shift); ++ break; ++ case BLOCK_ST_NEED_REMAP: ++ printf("%-12u [0x%08llx] - Awaiting remapping\n", i, ++ (uint64_t)i << nm->ni->erasesize_shift); ++ break; ++ } ++ } ++ ++ printf("\n"); ++ printf("Logical blocks:\n"); ++ ++ for (i = 0; i < nm->ni->data_block_count; i++) { ++ if (nm->ni->block_mapping[i] < 0) { ++ printf("%-12u [0x%08llx] - Bad\n", i, ++ (uint64_t)i << nm->ni->erasesize_shift); ++ } ++ } ++ ++ return 0; ++} ++ ++int nmbm_mtd_print_mappings(const char *name, int printall) ++{ ++ struct nmbm_mtd *nm; ++ bool found = false; ++ int32_t pb; ++ uint32_t i; ++ ++ list_for_each_entry(nm, &nmbm_devs, node) { ++ if (!strcmp(nm->name, name)) { ++ found = true; ++ break; ++ } ++ } ++ ++ if (!found) { ++ printf("Error: NMBM device '%s' not found\n", name); ++ return -ENODEV; ++ } ++ ++ printf("Logical Block Physical Block\n"); ++ printf("==================================\n"); ++ ++ if (!printall) { ++ for (i = 0; i < nm->ni->data_block_count; i++) { ++ pb = nm->ni->block_mapping[i]; ++ if (pb < 0) ++ printf("%-20uUnmapped\n", i); ++ else if ((uint32_t)pb > nm->ni->mapping_blocks_top_ba && ++ (uint32_t)pb < nm->ni->signature_ba) ++ printf("%-20u%u\n", i, pb); ++ } ++ ++ return 0; ++ } ++ ++ for (i = 0; i < nm->ni->data_block_count; i++) { ++ pb = nm->ni->block_mapping[i]; ++ ++ if (pb >= 0) ++ printf("%-20u%u\n", i, pb); ++ else ++ printf("%-20uUnmapped\n", i); ++ } ++ ++ return 0; ++} +--- /dev/null ++++ b/include/nmbm/nmbm-mtd.h +@@ -0,0 +1,27 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#ifndef _NMBM_MTD_H_ ++#define _NMBM_MTD_H_ ++ ++#include <linux/mtd/mtd.h> ++ ++int nmbm_attach_mtd(struct mtd_info *lower, int flags, uint32_t max_ratio, ++ uint32_t max_reserved_blocks, struct mtd_info **upper); ++ ++int nmbm_free_mtd(struct mtd_info *upper); ++ ++struct mtd_info *nmbm_mtd_get_upper_by_index(uint32_t index); ++struct mtd_info *nmbm_mtd_get_upper(struct mtd_info *lower); ++ ++void nmbm_mtd_list_devices(void); ++int nmbm_mtd_print_info(const char *name); ++int nmbm_mtd_print_states(const char *name); ++int nmbm_mtd_print_bad_blocks(const char *name); ++int nmbm_mtd_print_mappings(const char *name, int printall); ++ ++#endif /* _NMBM_MTD_H_ */ diff --git a/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch new file mode 100644 index 00000000000..da4dce917ba --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-08-common-board_r-add-support-to-initialize-NMBM-after-.patch @@ -0,0 +1,46 @@ +From dcf24c8deeb43a4406ae18136c8700dc2f867415 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 11:18:03 +0800 +Subject: [PATCH 42/71] common: board_r: add support to initialize NMBM after + nand initialization + +This patch add support to initialize NMBM after nand initialized. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + common/board_r.c | 17 +++++++++++++++++ + 1 file changed, 17 insertions(+) + +--- a/common/board_r.c ++++ b/common/board_r.c +@@ -373,6 +373,20 @@ static int initr_nand(void) + } + #endif + ++#ifdef CONFIG_NMBM_MTD ++ ++__weak int board_nmbm_init(void) ++{ ++ return 0; ++} ++ ++/* go init the NMBM */ ++static int initr_nmbm(void) ++{ ++ return board_nmbm_init(); ++} ++#endif ++ + #if defined(CONFIG_CMD_ONENAND) + /* go init the NAND */ + static int initr_onenand(void) +@@ -675,6 +689,9 @@ static init_fnc_t init_sequence_r[] = { + #ifdef CONFIG_CMD_ONENAND + initr_onenand, + #endif ++#ifdef CONFIG_NMBM_MTD ++ initr_nmbm, ++#endif + #ifdef CONFIG_MMC + initr_mmc, + #endif diff --git a/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch new file mode 100644 index 00000000000..4eb2bc9ccfe --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-09-cmd-add-nmbm-command.patch @@ -0,0 +1,370 @@ +From 0af8d0aac77f4df4bc7dadbcdea5d9a16f5f3e45 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:44:57 +0800 +Subject: [PATCH 43/71] cmd: add nmbm command + +Add nmbm command for debugging, data operations and image-booting support + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/Kconfig | 6 + + cmd/Makefile | 1 + + cmd/nmbm.c | 327 +++++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 334 insertions(+) + create mode 100644 cmd/nmbm.c + +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1392,6 +1392,12 @@ config CMD_NAND_TORTURE + + endif # CMD_NAND + ++config CMD_NMBM ++ depends on NMBM_MTD ++ bool "nmbm" ++ help ++ NAND mapping block management (NMBM) utility ++ + config CMD_NVME + bool "nvme" + depends on NVME +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o + endif + obj-$(CONFIG_CMD_MUX) += mux.o + obj-$(CONFIG_CMD_NAND) += nand.o ++obj-$(CONFIG_CMD_NMBM) += nmbm.o + obj-$(CONFIG_CMD_NET) += net.o + obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o + obj-$(CONFIG_CMD_ONENAND) += onenand.o +--- /dev/null ++++ b/cmd/nmbm.c +@@ -0,0 +1,327 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include <command.h> ++#include <image.h> ++#include <stdbool.h> ++#include <linux/types.h> ++#include <linux/mtd/mtd.h> ++#include <jffs2/load_kernel.h> ++ ++#include <nmbm/nmbm-mtd.h> ++ ++static int nmbm_parse_offset_size(struct mtd_info *mtd, char *off_str, ++ char *size_str, uint64_t *off, ++ uint64_t *size) ++{ ++ char *end; ++ ++ *off = simple_strtoull(off_str, &end, 16); ++ if (end == off_str) { ++ printf("Error: offset '%s' is invalid\n", off_str); ++ return -EINVAL; ++ } ++ ++ if (*off >= mtd->size) { ++ printf("Error: offset '0x%llx' is beyond the end of device\n", ++ *off); ++ return -EINVAL; ++ } ++ ++ *size = simple_strtoull(size_str, &end, 16); ++ if (end == off_str) { ++ printf("Error: size '%s' is invalid\n", off_str); ++ return -EINVAL; ++ } ++ ++ if (*off + *size > mtd->size) { ++ printf("Error: size '0x%llx' is too large\n", *size); ++ return -EINVAL; ++ } ++ ++ return 0; ++} ++ ++static int do_nmbm_erase(struct mtd_info *mtd, uint64_t offset, uint64_t size) ++{ ++ struct erase_info ei; ++ int ret; ++ ++ memset(&ei, 0, sizeof(ei)); ++ ++ ei.mtd = mtd; ++ ei.addr = offset; ++ ei.len = size; ++ ++ printf("Erasing from 0x%llx, size 0x%llx ...\n", offset, size); ++ ++ ret = mtd_erase(mtd, &ei); ++ ++ if (!ret) { ++ printf("Succeeded\n"); ++ return CMD_RET_SUCCESS; ++ } ++ ++ printf("Failed at 0x%llx\n", ei.fail_addr); ++ ++ return CMD_RET_FAILURE; ++} ++ ++static int do_nmbm_rw(int read, struct mtd_info *mtd, uintptr_t addr, ++ uint64_t offset, size_t size) ++{ ++ size_t retlen; ++ int ret; ++ ++ printf("%s 0x%llx, size 0x%zx\n", read ? "Reading from" : "Writing to", ++ offset, size); ++ ++ if (read) ++ ret = mtd_read(mtd, offset, size, &retlen, (void *)addr); ++ else ++ ret = mtd_write(mtd, offset, size, &retlen, (void *)addr); ++ ++ if (!ret) { ++ printf("Succeeded\n"); ++ return CMD_RET_SUCCESS; ++ } ++ ++ printf("Failed at 0x%llx\n", offset + retlen); ++ ++ return CMD_RET_FAILURE; ++} ++ ++static int do_nmbm_mtd_boot(struct cmd_tbl *cmdtp, struct mtd_info *mtd, ++ int argc, char *const argv[]) ++{ ++ bool print_image_contents = true; ++ uintptr_t loadaddr = image_load_addr; ++ char *end, *image_name; ++ const char *ep; ++ size_t retlen; ++ uint32_t size; ++ uint64_t off; ++ int ret; ++ ++#if defined(CONFIG_CMD_MTDPARTS) ++ struct mtd_device *partdev; ++ struct mtd_info *partmtd; ++ struct part_info *part; ++ u8 pnum; ++#endif ++ ++ ep = env_get("autostart"); ++ ++ if (ep && !strcmp(ep, "yes")) ++ print_image_contents = false; ++ ++ if (argc == 2) { ++ loadaddr = simple_strtoul(argv[0], &end, 0); ++ if (*end || end == argv[0]) { ++ printf("'%s' is not a valid address\n", argv[0]); ++ return CMD_RET_FAILURE; ++ } ++ ++ argc--; ++ argv++; ++ } ++ ++ off = simple_strtoull(argv[0], &end, 0); ++ if (*end || end == argv[0]) { ++#if defined(CONFIG_CMD_MTDPARTS) ++ ret = mtdparts_init(); ++ if (ret) ++ return CMD_RET_FAILURE; ++ ++ ret = find_dev_and_part(argv[0], &partdev, &pnum, &part); ++ if (ret) ++ return CMD_RET_FAILURE; ++ ++ if (partdev->id->type != MTD_DEV_TYPE_NMBM) { ++ printf("'%s' is not a NMBM device partition\n", ++ argv[0]); ++ return CMD_RET_FAILURE; ++ } ++ ++ partmtd = nmbm_mtd_get_upper_by_index(partdev->id->num); ++ ++ if (partmtd != mtd) { ++ printf("'%s' does not belong to this device\n", ++ argv[0]); ++ return CMD_RET_FAILURE; ++ } ++ ++ off = part->offset; ++#else ++ printf("'%s' is not a valid offset\n", argv[0]); ++ return CMD_RET_FAILURE; ++#endif ++ } ++ ++ ret = mtd_read(mtd, off, sizeof(struct legacy_img_hdr), &retlen, ++ (void *)loadaddr); ++ if (ret || retlen != sizeof(struct legacy_img_hdr)) { ++ printf("Failed to read NMBM at offset 0x%08llx\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ switch (genimg_get_format((void *)loadaddr)) { ++#if defined(CONFIG_LEGACY_IMAGE_FORMAT) ++ case IMAGE_FORMAT_LEGACY: ++ size = image_get_image_size((struct legacy_img_hdr *)loadaddr); ++ image_name = "legacy"; ++ break; ++#endif ++#if defined(CONFIG_FIT) ++ case IMAGE_FORMAT_FIT: ++ size = fit_get_size((const void *)loadaddr); ++ image_name = "FIT"; ++ break; ++#endif ++ default: ++ printf("Error: no Image found at offset 0x%08llx\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ printf("Loading %s image at offset 0x%llx to memory 0x%08lx, size 0x%x ...\n", ++ image_name, off, loadaddr, size); ++ ++ ret = mtd_read(mtd, off, size, &retlen, (void *)loadaddr); ++ if (ret || retlen != size) { ++ printf("Error: Failed to load image at offset 0x%08llx\n", ++ off + retlen); ++ return CMD_RET_FAILURE; ++ } ++ ++ switch (genimg_get_format((void *)loadaddr)) { ++#if defined(CONFIG_LEGACY_IMAGE_FORMAT) ++ case IMAGE_FORMAT_LEGACY: ++ if (print_image_contents) ++ image_print_contents((void *)loadaddr); ++ break; ++#endif ++#if defined(CONFIG_FIT) ++ case IMAGE_FORMAT_FIT: ++ if (print_image_contents) ++ fit_print_contents((void *)loadaddr); ++ break; ++#endif ++ } ++ ++ image_load_addr = loadaddr; ++ ++ return bootm_maybe_autostart(cmdtp, "nmbm"); ++} ++ ++static int do_nmbm(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd; ++ uint64_t offset, size; ++ char *end; ++ uintptr_t addr; ++ int ret, all = 0; ++ ++ if (argc == 1) ++ return CMD_RET_USAGE; ++ ++ if (!strcmp(argv[1], "list")) { ++ nmbm_mtd_list_devices(); ++ return CMD_RET_SUCCESS; ++ } ++ ++ if (argc < 3) ++ return CMD_RET_USAGE; ++ ++ if (!strcmp(argv[2], "info")) ++ return !!nmbm_mtd_print_info(argv[1]); ++ ++ if (!strcmp(argv[2], "state")) ++ return !!nmbm_mtd_print_states(argv[1]); ++ ++ if (!strcmp(argv[2], "bad")) ++ return !!nmbm_mtd_print_bad_blocks(argv[1]); ++ ++ if (!strcmp(argv[2], "mapping")) { ++ if (argc >= 4) { ++ if (!strcmp(argv[3], "all")) ++ all = 1; ++ } ++ ++ return nmbm_mtd_print_mappings(argv[1], all); ++ } ++ ++ if (argc < 4) ++ return CMD_RET_USAGE; ++ ++ mtd = get_mtd_device_nm(argv[1]); ++ if (IS_ERR(mtd)) { ++ printf("Error: NMBM device '%s' not found\n", argv[1]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (mtd->type != MTD_DEV_TYPE_NMBM) { ++ printf("Error: '%s' is not a NMBM device\n", argv[1]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (!strcmp(argv[2], "boot")) ++ return do_nmbm_mtd_boot(cmdtp, mtd, argc - 3, argv + 3); ++ ++ if (argc < 5) ++ return CMD_RET_USAGE; ++ ++ if (!strcmp(argv[2], "erase")) { ++ ret = nmbm_parse_offset_size(mtd, argv[3], argv[4], &offset, ++ &size); ++ if (ret) ++ return CMD_RET_FAILURE; ++ ++ return do_nmbm_erase(mtd, offset, size); ++ } ++ ++ if (argc < 6) ++ return CMD_RET_USAGE; ++ ++ ret = nmbm_parse_offset_size(mtd, argv[4], argv[5], &offset, &size); ++ if (ret) ++ return CMD_RET_FAILURE; ++ ++ if (size > SIZE_MAX) { ++ printf("Error: size 0x%llx is too large\n", size); ++ return -EINVAL; ++ } ++ ++ addr = simple_strtoul(argv[3], &end, 16); ++ if (end == argv[3]) { ++ printf("Error: addr '%s' is invalid\n", argv[3]); ++ return -EINVAL; ++ } ++ ++ if (!strcmp(argv[2], "read")) ++ return do_nmbm_rw(1, mtd, addr, offset, (size_t)size); ++ ++ if (!strcmp(argv[2], "write")) ++ return do_nmbm_rw(0, mtd, addr, offset, (size_t)size); ++ ++ return CMD_RET_USAGE; ++} ++ ++U_BOOT_CMD( ++ nmbm, CONFIG_SYS_MAXARGS, 0, do_nmbm, ++ "NMBM utility commands", ++ "\n" ++ "nmbm list - List NMBM devices\n" ++ "nmbm <name> info - Display NMBM information\n" ++ "nmbm <name> state - Display block states\n" ++ "nmbm <name> bad - Display bad blocks\n" ++ "nmbm <name> boot <part | [loadaddr] offset> - Boot from NMBM\n" ++ "nmbm <name> mapping [all] - Display block mapping\n" ++ "nmbm <name> erase <offset> <size> - Erase blocks\n" ++ "nmbm <name> read <addr> <offset> <size> - Read data\n" ++ "nmbm <name> write <addr> <offset> <size> - Write data\n" ++); diff --git a/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch new file mode 100644 index 00000000000..c6358f32877 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-10-cmd-mtd-add-markbad-subcommand-for-NMBM-testing.patch @@ -0,0 +1,80 @@ +From 6dbbc8affb6ab22f940d13d0e928d5e881127ca4 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 11:22:57 +0800 +Subject: [PATCH 44/71] cmd: mtd: add markbad subcommand for NMBM testing + +This patch adds: +* Mark bad block on lower mtd device and erase on upper mtd +device, which will trigger remapping: +$ mtd markbad spi-nand0 0x20000 (mark block1 as bad) +$ mtd erase nmbm0 0x20000 0x20000 (let nmbm detect the bad block and remap it) + +* Clear bad block mark through: +$ mtd erase.dontskipbad spi-nand0 0x20000 0x20000 +(After cleaning bad block mark, we need to rebuild nmbm manage table.) + +Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com> +--- + cmd/mtd.c | 39 +++++++++++++++++++++++++++++++++++++++ + 1 file changed, 39 insertions(+) + +--- a/cmd/mtd.c ++++ b/cmd/mtd.c +@@ -504,6 +504,42 @@ out_put_mtd: + return CMD_RET_SUCCESS; + } + ++static int do_mtd_markbad(struct cmd_tbl *cmdtp, int flag, int argc, ++ char * const argv[]) ++{ ++ struct mtd_info *mtd; ++ loff_t off; ++ int ret; ++ ++ if (argc < 3) ++ return CMD_RET_USAGE; ++ ++ mtd = get_mtd_by_name(argv[1]); ++ if (IS_ERR(mtd) || !mtd) ++ return CMD_RET_FAILURE; ++ ++ if (!mtd_can_have_bb(mtd)) { ++ printf("Only NAND-based devices can have mark blocks\n"); ++ goto out_put_mtd; ++ } ++ ++ off = simple_strtoull(argv[2], NULL, 0); ++ ++ ret = mtd_block_markbad(mtd, off); ++ if (!ret) { ++ printf("MTD device %s block at 0x%08llx marked bad\n", ++ mtd->name, off); ++ } else { ++ printf("MTD device %s block at 0x%08llx mark bad failed\n", ++ mtd->name, off); ++ } ++ ++out_put_mtd: ++ put_mtd_device(mtd); ++ ++ return CMD_RET_SUCCESS; ++} ++ + #ifdef CONFIG_AUTO_COMPLETE + static int mtd_name_complete(int argc, char *const argv[], char last_char, + int maxv, char *cmdv[]) +@@ -551,6 +587,7 @@ U_BOOT_LONGHELP(mtd, + "\n" + "Specific functions:\n" + "mtd bad <name>\n" ++ "mtd markbad <name> <off>\n" + "\n" + "With:\n" + "\t<name>: NAND partition/chip name (or corresponding DM device name or OF path)\n" +@@ -575,4 +612,6 @@ U_BOOT_CMD_WITH_SUBCMDS(mtd, "MTD utils" + U_BOOT_SUBCMD_MKENT_COMPLETE(erase, 4, 0, do_mtd_erase, + mtd_name_complete), + U_BOOT_SUBCMD_MKENT_COMPLETE(bad, 2, 1, do_mtd_bad, ++ mtd_name_complete), ++ U_BOOT_SUBCMD_MKENT_COMPLETE(markbad, 3, 1, do_mtd_markbad, + mtd_name_complete)); diff --git a/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch new file mode 100644 index 00000000000..dbb1e2e59d2 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-11-env-add-support-for-NMBM-upper-MTD-layer.patch @@ -0,0 +1,260 @@ +From 240d98e6ad0aed3c11236aa40a60bbd6fe01fae5 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:50:46 +0800 +Subject: [PATCH 45/71] env: add support for NMBM upper MTD layer + +Add an env driver for NMBM upper MTD layer + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/nvedit.c | 3 +- + env/Kconfig | 19 ++++- + env/Makefile | 1 + + env/env.c | 3 + + env/nmbm.c | 155 +++++++++++++++++++++++++++++++++++++++++ + include/env_internal.h | 1 + + tools/Makefile | 1 + + 7 files changed, 180 insertions(+), 3 deletions(-) + create mode 100644 env/nmbm.c + +--- a/env/Kconfig ++++ b/env/Kconfig +@@ -59,6 +59,7 @@ config ENV_IS_DEFAULT + def_bool y if !ENV_IS_IN_EEPROM && !ENV_IS_IN_EXT4 && \ + !ENV_IS_IN_FAT && !ENV_IS_IN_FLASH && \ + !ENV_IS_IN_MMC && !ENV_IS_IN_NAND && \ ++ !ENV_IS_IN_NMBM && \ + !ENV_IS_IN_NVRAM && !ENV_IS_IN_ONENAND && \ + !ENV_IS_IN_REMOTE && !ENV_IS_IN_SPI_FLASH && \ + !ENV_IS_IN_UBI && !ENV_IS_IN_MTD +@@ -315,6 +316,21 @@ config ENV_RANGE + Specifying a range with more erase blocks than are needed to hold + CONFIG_ENV_SIZE allows bad blocks within the range to be avoided. + ++config ENV_IS_IN_NMBM ++ bool "Environment in a NMBM upper MTD layer" ++ depends on !CHAIN_OF_TRUST ++ depends on NMBM_MTD ++ help ++ Define this if you have a NMBM upper MTD which you want to use for ++ the environment. ++ ++ - CONFIG_ENV_OFFSET: ++ - CONFIG_ENV_SIZE: ++ ++ These two #defines specify the offset and size of the environment ++ area within the first NAND device. CONFIG_ENV_OFFSET must be ++ aligned to an erase block boundary. ++ + config ENV_IS_IN_NVRAM + bool "Environment in a non-volatile RAM" + depends on !CHAIN_OF_TRUST +@@ -591,7 +607,7 @@ config ENV_MTD_NAME + config ENV_OFFSET + hex "Environment offset" + depends on ENV_IS_IN_EEPROM || ENV_IS_IN_MMC || ENV_IS_IN_NAND || \ +- ENV_IS_IN_SPI_FLASH || ENV_IS_IN_MTD ++ ENV_IS_IN_SPI_FLASH || ENV_IS_IN_NMBM || ENV_IS_IN_MTD + default 0x3f8000 if ARCH_ROCKCHIP && ENV_IS_IN_MMC + default 0x140000 if ARCH_ROCKCHIP && ENV_IS_IN_SPI_FLASH + default 0xF0000 if ARCH_SUNXI +--- a/env/Makefile ++++ b/env/Makefile +@@ -26,6 +26,7 @@ obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FAT) + + obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_EXT4) += ext4.o + obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_MTD) += mtd.o + obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NAND) += nand.o ++obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_NMBM) += nmbm.o + obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_SPI_FLASH) += sf.o + obj-$(CONFIG_$(SPL_TPL_)ENV_IS_IN_FLASH) += flash.o + +--- a/env/env.c ++++ b/env/env.c +@@ -52,6 +52,9 @@ static enum env_location env_locations[] + #ifdef CONFIG_ENV_IS_IN_NAND + ENVL_NAND, + #endif ++#ifdef CONFIG_ENV_IS_IN_NMBM ++ ENVL_NMBM, ++#endif + #ifdef CONFIG_ENV_IS_IN_NVRAM + ENVL_NVRAM, + #endif +--- /dev/null ++++ b/env/nmbm.c +@@ -0,0 +1,155 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/* ++ * Copyright (C) 2020 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include <command.h> ++#include <env.h> ++#include <env_internal.h> ++#include <errno.h> ++#include <linux/kernel.h> ++#include <linux/stddef.h> ++#include <linux/types.h> ++#include <malloc.h> ++#include <memalign.h> ++#include <search.h> ++ ++#include <nmbm/nmbm-mtd.h> ++ ++#if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_NMBM_MTD) ++#define CMD_SAVEENV ++#endif ++ ++#if defined(ENV_IS_EMBEDDED) ++env_t *env_ptr = &environment; ++#else /* ! ENV_IS_EMBEDDED */ ++env_t *env_ptr; ++#endif /* ENV_IS_EMBEDDED */ ++ ++DECLARE_GLOBAL_DATA_PTR; ++ ++static int env_nmbm_init(void) ++{ ++#if defined(ENV_IS_EMBEDDED) ++ int crc1_ok = 0, crc2_ok = 0; ++ env_t *tmp_env1; ++ ++ tmp_env1 = env_ptr; ++ crc1_ok = crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc; ++ ++ if (!crc1_ok && !crc2_ok) { ++ gd->env_addr = 0; ++ gd->env_valid = ENV_INVALID; ++ ++ return 0; ++ } else if (crc1_ok && !crc2_ok) { ++ gd->env_valid = ENV_VALID; ++ } ++ ++ if (gd->env_valid == ENV_VALID) ++ env_ptr = tmp_env1; ++ ++ gd->env_addr = (ulong)env_ptr->data; ++ ++#else /* ENV_IS_EMBEDDED */ ++ gd->env_addr = (ulong)&default_environment[0]; ++ gd->env_valid = ENV_VALID; ++#endif /* ENV_IS_EMBEDDED */ ++ ++ return 0; ++} ++ ++#ifdef CMD_SAVEENV ++static int env_nmbm_save(void) ++{ ++ ALLOC_CACHE_ALIGN_BUFFER(env_t, env_new, 1); ++ struct mtd_info *mtd; ++ struct erase_info ei; ++ int ret = 0; ++ ++ ret = env_export(env_new); ++ if (ret) ++ return ret; ++ ++ mtd = nmbm_mtd_get_upper_by_index(0); ++ if (!mtd) ++ return 1; ++ ++ printf("Erasing on NMBM...\n"); ++ memset(&ei, 0, sizeof(ei)); ++ ++ ei.mtd = mtd; ++ ei.addr = CONFIG_ENV_OFFSET; ++ ei.len = CONFIG_ENV_SIZE; ++ ++ if (mtd_erase(mtd, &ei)) ++ return 1; ++ ++ printf("Writing on NMBM... "); ++ ret = mtd_write(mtd, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, NULL, ++ (u_char *)env_new); ++ puts(ret ? "FAILED!\n" : "OK\n"); ++ ++ return !!ret; ++} ++#endif /* CMD_SAVEENV */ ++ ++static int readenv(size_t offset, u_char *buf) ++{ ++ struct mtd_info *mtd; ++ struct mtd_oob_ops ops; ++ int ret; ++ size_t len = CONFIG_ENV_SIZE; ++ ++ mtd = nmbm_mtd_get_upper_by_index(0); ++ if (!mtd) ++ return 1; ++ ++ ops.mode = MTD_OPS_AUTO_OOB; ++ ops.ooblen = 0; ++ while(len > 0) { ++ ops.datbuf = buf; ++ ops.len = min(len, (size_t)mtd->writesize); ++ ops.oobbuf = NULL; ++ ++ ret = mtd_read_oob(mtd, offset, &ops); ++ if (ret) ++ return 1; ++ ++ buf += mtd->writesize; ++ len -= mtd->writesize; ++ offset += mtd->writesize; ++ } ++ ++ return 0; ++} ++ ++static int env_nmbm_load(void) ++{ ++#if !defined(ENV_IS_EMBEDDED) ++ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE); ++ int ret; ++ ++ ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf); ++ if (ret) { ++ env_set_default("readenv() failed", 0); ++ return -EIO; ++ } ++ ++ return env_import(buf, 1, H_EXTERNAL); ++#endif /* ! ENV_IS_EMBEDDED */ ++ ++ return 0; ++} ++ ++U_BOOT_ENV_LOCATION(nmbm) = { ++ .location = ENVL_NMBM, ++ ENV_NAME("NMBM") ++ .load = env_nmbm_load, ++#if defined(CMD_SAVEENV) ++ .save = env_save_ptr(env_nmbm_save), ++#endif ++ .init = env_nmbm_init, ++}; +--- a/include/env_internal.h ++++ b/include/env_internal.h +@@ -111,6 +111,7 @@ enum env_location { + ENVL_MMC, + ENVL_MTD, + ENVL_NAND, ++ ENVL_NMBM, + ENVL_NVRAM, + ENVL_ONENAND, + ENVL_REMOTE, +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -39,6 +39,7 @@ ENVCRC-$(CONFIG_ENV_IS_IN_FLASH) = y + ENVCRC-$(CONFIG_ENV_IS_IN_ONENAND) = y + ENVCRC-$(CONFIG_ENV_IS_IN_MTD) = y + ENVCRC-$(CONFIG_ENV_IS_IN_NAND) = y ++ENVCRC-$(CONFIG_ENV_IS_IN_NMBM) = y + ENVCRC-$(CONFIG_ENV_IS_IN_NVRAM) = y + ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y + BUILD_ENVCRC ?= $(ENVCRC-y) diff --git a/package/boot/uboot-mediatek/patches/100-12-mtd-mtk-snand-add-NMBM-support-for-SPL.patch b/package/boot/uboot-mediatek/patches/100-12-mtd-mtk-snand-add-NMBM-support-for-SPL.patch new file mode 100644 index 00000000000..32b21be2551 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-12-mtd-mtk-snand-add-NMBM-support-for-SPL.patch @@ -0,0 +1,173 @@ +From 9e8ac4fc7125795ac5e8834aaf454fd45b99c580 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:53:03 +0800 +Subject: [PATCH 46/71] mtd: mtk-snand: add NMBM support for SPL + +Add NMBM support for mtk-snand SPL loader + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/mtk-snand/mtk-snand-spl.c | 127 ++++++++++++++++++++++++++ + 1 file changed, 127 insertions(+) + +--- a/drivers/mtd/mtk-snand/mtk-snand-spl.c ++++ b/drivers/mtd/mtk-snand/mtk-snand-spl.c +@@ -13,12 +13,134 @@ + #include <mtd.h> + #include <watchdog.h> + ++#include <nmbm/nmbm.h> ++ + #include "mtk-snand.h" + + static struct mtk_snand *snf; + static struct mtk_snand_chip_info cinfo; + static u32 oobavail; + ++#ifdef CONFIG_ENABLE_NAND_NMBM ++static struct nmbm_instance *ni; ++ ++static int nmbm_lower_read_page(void *arg, uint64_t addr, void *buf, void *oob, ++ enum nmbm_oob_mode mode) ++{ ++ int ret; ++ bool raw = mode == NMBM_MODE_RAW ? true : false; ++ ++ if (mode == NMBM_MODE_AUTO_OOB) { ++ ret = mtk_snand_read_page_auto_oob(snf, addr, buf, oob, ++ oobavail, NULL, false); ++ } else { ++ ret = mtk_snand_read_page(snf, addr, buf, oob, raw); ++ } ++ ++ if (ret == -EBADMSG) ++ return 1; ++ else if (ret >= 0) ++ return 0; ++ ++ return ret; ++} ++ ++static int nmbm_lower_write_page(void *arg, uint64_t addr, const void *buf, ++ const void *oob, enum nmbm_oob_mode mode) ++{ ++ bool raw = mode == NMBM_MODE_RAW ? true : false; ++ ++ if (mode == NMBM_MODE_AUTO_OOB) { ++ return mtk_snand_write_page_auto_oob(snf, addr, buf, oob, ++ oobavail, NULL, false); ++ } ++ ++ return mtk_snand_write_page(snf, addr, buf, oob, raw); ++} ++ ++static int nmbm_lower_erase_block(void *arg, uint64_t addr) ++{ ++ return mtk_snand_erase_block(snf, addr); ++} ++ ++static int nmbm_lower_is_bad_block(void *arg, uint64_t addr) ++{ ++ return mtk_snand_block_isbad(snf, addr); ++} ++ ++static int nmbm_lower_mark_bad_block(void *arg, uint64_t addr) ++{ ++ return mtk_snand_block_markbad(snf, addr); ++} ++ ++static void nmbm_lower_log(void *arg, enum nmbm_log_category level, ++ const char *fmt, va_list ap) ++{ ++ vprintf(fmt, ap); ++} ++ ++static int nmbm_init(void) ++{ ++ struct nmbm_lower_device nld; ++ size_t ni_size; ++ int ret; ++ ++ memset(&nld, 0, sizeof(nld)); ++ ++ nld.flags = NMBM_F_CREATE; ++ nld.max_ratio = CONFIG_NMBM_MAX_RATIO; ++ nld.max_reserved_blocks = CONFIG_NMBM_MAX_BLOCKS; ++ ++ nld.size = cinfo.chipsize; ++ nld.erasesize = cinfo.blocksize; ++ nld.writesize = cinfo.pagesize; ++ nld.oobsize = cinfo.sparesize; ++ nld.oobavail = oobavail; ++ ++ nld.read_page = nmbm_lower_read_page; ++ nld.write_page = nmbm_lower_write_page; ++ nld.erase_block = nmbm_lower_erase_block; ++ nld.is_bad_block = nmbm_lower_is_bad_block; ++ nld.mark_bad_block = nmbm_lower_mark_bad_block; ++ ++ nld.logprint = nmbm_lower_log; ++ ++ ni_size = nmbm_calc_structure_size(&nld); ++ ni = malloc(ni_size); ++ if (!ni) { ++ printf("Failed to allocate memory (0x%u) for NMBM instance\n", ++ ni_size); ++ return -ENOMEM; ++ } ++ ++ memset(ni, 0, ni_size); ++ ++ printf("Initializing NMBM ...\n"); ++ ++ ret = nmbm_attach(&nld, ni); ++ if (ret) { ++ ni = NULL; ++ return ret; ++ } ++ ++ return 0; ++} ++ ++int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) ++{ ++ size_t retlen; ++ ++ if (!ni) ++ return -ENODEV; ++ ++ nmbm_read_range(ni, offs, size, dst, NMBM_MODE_PLACE_OOB, &retlen); ++ if (retlen != size) ++ return -EIO; ++ ++ return 0; ++} ++ ++#else + static u8 *page_cache; + + int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst) +@@ -60,6 +182,7 @@ int nand_spl_load_image(uint32_t offs, u + + return ret; + } ++#endif + + void nand_init(void) + { +@@ -105,11 +228,15 @@ void nand_init(void) + printf("SPI-NAND: %s (%uMB)\n", cinfo.model, + (u32)(cinfo.chipsize >> 20)); + ++#ifdef CONFIG_ENABLE_NAND_NMBM ++ nmbm_init(); ++#else + page_cache = malloc(cinfo.pagesize + cinfo.sparesize); + if (!page_cache) { + mtk_snand_cleanup(snf); + printf("mtk-snand-spl: failed to allocate page cache\n"); + } ++#endif + } + + void nand_deselect(void) diff --git a/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch new file mode 100644 index 00000000000..e6e12ae24cd --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-13-cmd-add-a-new-command-for-NAND-flash-debugging.patch @@ -0,0 +1,1118 @@ +From 88271cb3ae9c68dc200d627653df96fc557c2a64 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 10:55:35 +0800 +Subject: [PATCH 47/71] cmd: add a new command for NAND flash debugging + +Add a command 'nand-ext' for NAND flash debugging: +- Dump a page with oob, with optional raw read support +- Display all bad blocks +- Mark a block as bad block +- Set a bitflip on a page +- Erase +- Read / write data from/to any offset with any size +- Read / write pages with oob +- Erase, read and write support skip bad block or forced mode, support + raw mode, supporot auto-oob mode +- Supports operating on a specific partition +- No need to specify NAND device name + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/Kconfig | 8 + + cmd/Makefile | 1 + + cmd/nand-ext.c | 1062 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 1071 insertions(+) + create mode 100644 cmd/nand-ext.c + +--- a/cmd/Kconfig ++++ b/cmd/Kconfig +@@ -1392,6 +1392,14 @@ config CMD_NAND_TORTURE + + endif # CMD_NAND + ++config CMD_NAND_EXT ++ bool "nand - extended nand utility for debugging" ++ depends on !CMD_NAND ++ default y if MTD_RAW_NAND || MTD_SPI_NAND || MTK_SPI_NAND ++ select MTD_PARTITIONS ++ help ++ NAND flash R/W and debugging support. ++ + config CMD_NMBM + depends on NMBM_MTD + bool "nmbm" +--- a/cmd/Makefile ++++ b/cmd/Makefile +@@ -127,6 +127,7 @@ obj-y += legacy-mtd-utils.o + endif + obj-$(CONFIG_CMD_MUX) += mux.o + obj-$(CONFIG_CMD_NAND) += nand.o ++obj-$(CONFIG_CMD_NAND_EXT) += nand-ext.o + obj-$(CONFIG_CMD_NMBM) += nmbm.o + obj-$(CONFIG_CMD_NET) += net.o + obj-$(CONFIG_CMD_NVEDIT_EFI) += nvedit_efi.o +--- /dev/null ++++ b/cmd/nand-ext.c +@@ -0,0 +1,1062 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2021 MediaTek Inc. All Rights Reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++#include <command.h> ++#include <stdbool.h> ++#include <malloc.h> ++#include <mtd.h> ++#include <dm/devres.h> ++#include <linux/types.h> ++#include <linux/mtd/mtd.h> ++ ++static struct mtd_info *curr_dev; ++ ++static void mtd_show_parts(struct mtd_info *mtd, int level) ++{ ++ struct mtd_info *part; ++ int i; ++ ++ list_for_each_entry(part, &mtd->partitions, node) { ++ for (i = 0; i < level; i++) ++ printf("\t"); ++ printf(" - 0x%012llx-0x%012llx : \"%s\"\n", ++ part->offset, part->offset + part->size, part->name); ++ ++ mtd_show_parts(part, level + 1); ++ } ++} ++ ++static void mtd_show_device(struct mtd_info *mtd) ++{ ++ /* Device */ ++ printf("* %s\n", mtd->name); ++#if defined(CONFIG_DM) ++ if (mtd->dev) { ++ printf(" - device: %s\n", mtd->dev->name); ++ printf(" - parent: %s\n", mtd->dev->parent->name); ++ printf(" - driver: %s\n", mtd->dev->driver->name); ++ } ++#endif ++ ++ /* MTD device information */ ++ printf(" - type: "); ++ switch (mtd->type) { ++ case MTD_NANDFLASH: ++ printf("NAND flash\n"); ++ break; ++ case MTD_MLCNANDFLASH: ++ printf("MLC NAND flash\n"); ++ break; ++ case MTD_ABSENT: ++ default: ++ printf("Not supported\n"); ++ break; ++ } ++ ++ printf(" - block size: 0x%x bytes\n", mtd->erasesize); ++ printf(" - page size: 0x%x bytes\n", mtd->writesize); ++ printf(" - OOB size: %u bytes\n", mtd->oobsize); ++ printf(" - OOB available: %u bytes\n", mtd->oobavail); ++ ++ if (mtd->ecc_strength) { ++ printf(" - ECC strength: %u bits\n", mtd->ecc_strength); ++ printf(" - ECC step size: %u bytes\n", mtd->ecc_step_size); ++ printf(" - bitflip threshold: %u bits\n", ++ mtd->bitflip_threshold); ++ } ++ ++ printf(" - 0x%012llx-0x%012llx : \"%s\"\n", ++ mtd->offset, mtd->offset + mtd->size, mtd->name); ++ ++ /* MTD partitions, if any */ ++ mtd_show_parts(mtd, 1); ++} ++ ++static int do_nand_list(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd; ++ int dev_nb = 0; ++ ++ /* Ensure all devices (and their partitions) are probed */ ++ mtd_probe_devices(); ++ ++ printf("List of NAND devices:\n"); ++ mtd_for_each_device(mtd) { ++ if (mtd->type != MTD_NANDFLASH && mtd->type != MTD_MLCNANDFLASH) ++ continue; ++ ++ if (!mtd_is_partition(mtd)) ++ mtd_show_device(mtd); ++ ++ dev_nb++; ++ } ++ ++ if (!dev_nb) ++ printf("No NAND MTD device found\n"); ++ ++ return CMD_RET_SUCCESS; ++} ++ ++static struct mtd_info *nand_get_curr_dev(void) ++{ ++ struct mtd_info *mtd, *first_dev = NULL; ++ int err, dev_nb = 0; ++ ++ if (curr_dev) { ++ mtd = get_mtd_device(curr_dev, -1); ++ if (!IS_ERR_OR_NULL(mtd)) { ++ __put_mtd_device(mtd); ++ return mtd; ++ } ++ ++ curr_dev = NULL; ++ } ++ ++ /* Ensure all devices (and their partitions) are probed */ ++ mtd_probe_devices(); ++ ++ mtd_for_each_device(mtd) { ++ if (mtd->type != MTD_NANDFLASH && mtd->type != MTD_MLCNANDFLASH) ++ continue; ++ ++ if (!mtd_is_partition(mtd)) { ++ if (!first_dev) ++ first_dev = mtd; ++ dev_nb++; ++ } ++ } ++ ++ if (!dev_nb) { ++ printf("No NAND MTD device found\n"); ++ return NULL; ++ } ++ ++ if (dev_nb > 1) { ++ printf("No active NAND MTD device specified\n"); ++ return NULL; ++ } ++ ++ err = __get_mtd_device(first_dev); ++ if (err) { ++ printf("Failed to get MTD device '%s': err %d\n", ++ first_dev->name, err); ++ return NULL; ++ } ++ ++ curr_dev = first_dev; ++ ++ printf("'%s' is now active device\n", first_dev->name); ++ ++ return curr_dev; ++} ++ ++static struct mtd_info *nand_get_part(struct mtd_info *master, ++ const char *name) ++{ ++ struct mtd_info *slave; ++ ++ list_for_each_entry(slave, &master->partitions, node) { ++ if (!strcmp(slave->name, name)) ++ return slave; ++ } ++ ++ return NULL; ++} ++ ++static int do_nand_info(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(); ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ mtd_show_device(mtd); ++ ++ return 0; ++} ++ ++static int do_nand_select(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd, *old; ++ ++ if (argc < 2) { ++ printf("MTD device name must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ mtd = get_mtd_device_nm(argv[1]); ++ if (!mtd) { ++ printf("MTD device '%s' not found\n", argv[1]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (mtd_is_partition(mtd)) { ++ printf("Error: '%s' is a MTD partition\n", argv[1]); ++ __put_mtd_device(mtd); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (mtd->type != MTD_NANDFLASH && mtd->type != MTD_MLCNANDFLASH) { ++ printf("Error: '%s' is not a NAND device\n", argv[1]); ++ __put_mtd_device(mtd); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (mtd == curr_dev) { ++ __put_mtd_device(mtd); ++ return CMD_RET_SUCCESS; ++ } ++ ++ if (curr_dev) { ++ old = get_mtd_device(curr_dev, -1); ++ if (!IS_ERR_OR_NULL(old)) { ++ __put_mtd_device(old); ++ __put_mtd_device(curr_dev); ++ } ++ ++ curr_dev = NULL; ++ } ++ ++ curr_dev = mtd; ++ ++ printf("'%s' is now active device\n", curr_dev->name); ++ ++ return CMD_RET_SUCCESS; ++} ++ ++static void dump_buf(const u8 *data, size_t size, u64 addr) ++{ ++ const u8 *p = data; ++ u32 i, chklen; ++ ++ while (size) { ++ chklen = 16; ++ if (chklen > size) ++ chklen = (u32)size; ++ ++ printf("%08llx: ", addr); ++ ++ for (i = 0; i < chklen; i++) { ++ if (i && (i % 4 == 0)) ++ printf(" "); ++ ++ printf("%02x ", p[i]); ++ } ++ ++ for (i = chklen; i < 16; i++) { ++ if (i && (i % 4 == 0)) ++ printf(" "); ++ ++ printf(" "); ++ } ++ printf(" "); ++ ++ for (i = 0; i < chklen; i++) { ++ if (p[i] < 32 || p[i] >= 0x7f) ++ printf("."); ++ else ++ printf("%c", p[i]); ++ } ++ printf("\n"); ++ ++ p += chklen; ++ size -= chklen; ++ addr += chklen; ++ } ++} ++ ++static int do_nand_dump(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(); ++ struct mtd_oob_ops io_op = {}; ++ bool raw = false; ++ int ret; ++ u64 off; ++ u8 *buf; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (strstr(argv[0], ".raw")) ++ raw = true; ++ ++ if (argc < 2) { ++ printf("Dump offset must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ off = simple_strtoull(argv[1], NULL, 0); ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ off &= ~(u64)mtd->writesize_mask; ++ ++ buf = malloc(mtd->writesize + mtd->oobsize); ++ if (!buf) { ++ printf("Failed to allocate buffer\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ io_op.mode = raw ? MTD_OPS_RAW : MTD_OPS_PLACE_OOB; ++ io_op.len = mtd->writesize; ++ io_op.datbuf = buf; ++ io_op.ooblen = mtd->oobsize; ++ io_op.oobbuf = buf + mtd->writesize; ++ ++ ret = mtd_read_oob(mtd, off, &io_op); ++ if (ret < 0 && ret != -EUCLEAN && ret != -EBADMSG) { ++ printf("Failed to read page at 0x%llx, err %d\n", off, ret); ++ free(buf); ++ return CMD_RET_FAILURE; ++ } ++ ++ printf("Dump of %spage at 0x%llx:\n", raw ? "raw " : "", off); ++ dump_buf(buf, mtd->writesize, off); ++ ++ printf("\n"); ++ printf("OOB:\n"); ++ dump_buf(buf + mtd->writesize, mtd->oobsize, 0); ++ ++ free(buf); ++ ++ return CMD_RET_SUCCESS; ++} ++ ++static int do_nand_bad(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(); ++ u64 off = 0; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ while (off < mtd->size) { ++ if (mtd_block_isbad(mtd, off)) ++ printf("\t%08llx\n", off); ++ ++ off += mtd->erasesize; ++ } ++ ++ return 0; ++} ++ ++static int do_nand_markbad(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(); ++ u64 off; ++ int ret; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (argc < 2) { ++ printf("Missing address within a block to be marked bad\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ off = simple_strtoull(argv[1], NULL, 0); ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ off &= ~(u64)mtd->erasesize_mask; ++ ++ ret = mtd_block_markbad(mtd, off); ++ ++ if (!ret) ++ printf("Block at 0x%08llx has been marked bad\n", off); ++ else ++ printf("Failed to mark bad block at 0x%08llx\n", off); ++ ++ return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS; ++} ++ ++static int do_nand_bitflip(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(); ++ struct mtd_oob_ops io_op = {}; ++ u32 col, bit; ++ bool res; ++ u64 off; ++ u8 *buf; ++ int ret; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (argc < 2) { ++ printf("Missing address to generate bitflip\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ off = simple_strtoull(argv[1], NULL, 0); ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 3) { ++ printf("Missing column address\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ col = simple_strtoul(argv[2], NULL, 0); ++ if (col >= mtd->writesize + mtd->oobsize) { ++ printf("Column address must be less than %u\n", ++ mtd->writesize + mtd->oobsize); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 4) { ++ printf("Missing bit position\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ bit = simple_strtoul(argv[3], NULL, 0); ++ if (bit > 7) { ++ printf("Bit position must be less than 8\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ off &= ~(u64)mtd->writesize_mask; ++ ++ buf = malloc(mtd->writesize + mtd->oobsize); ++ if (!buf) { ++ printf("Failed to allocate buffer\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ io_op.mode = MTD_OPS_RAW; ++ io_op.len = mtd->writesize; ++ io_op.datbuf = buf; ++ io_op.ooblen = mtd->oobsize; ++ io_op.oobbuf = buf + mtd->writesize; ++ ++ ret = mtd_read_oob(mtd, off, &io_op); ++ if (ret < 0) { ++ printf("Failed to read page at 0x%llx, err %d\n", off, ret); ++ free(buf); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (!(buf[col] & (1 << bit))) { ++ printf("Bit %u at byte %u is already zero\n", bit, col); ++ free(buf); ++ return CMD_RET_FAILURE; ++ } ++ ++ buf[col] &= ~(1 << bit); ++ ++ memset(&io_op, 0, sizeof(io_op)); ++ io_op.mode = MTD_OPS_RAW; ++ io_op.len = mtd->writesize; ++ io_op.datbuf = buf; ++ io_op.ooblen = mtd->oobsize; ++ io_op.oobbuf = buf + mtd->writesize; ++ ++ ret = mtd_write_oob(mtd, off, &io_op); ++ ++ if (ret < 0) { ++ printf("Failed to write page at 0x%llx, err %d\n", off, ret); ++ return CMD_RET_FAILURE; ++ } ++ ++ memset(&io_op, 0, sizeof(io_op)); ++ io_op.mode = MTD_OPS_RAW; ++ io_op.len = mtd->writesize; ++ io_op.datbuf = buf; ++ io_op.ooblen = mtd->oobsize; ++ io_op.oobbuf = buf + mtd->writesize; ++ ++ ret = mtd_read_oob(mtd, off, &io_op); ++ if (ret < 0) { ++ printf("Failed to read page at 0x%llx, err %d\n", off, ret); ++ free(buf); ++ return CMD_RET_FAILURE; ++ } ++ ++ res = (buf[col] & (1 << bit)) == 0; ++ free(buf); ++ ++ if (res) { ++ printf("Bit %u at byte %u has been changed to 0\n", bit, col); ++ return CMD_RET_SUCCESS; ++ } ++ ++ printf("Failed to change bit %u at byte %u to 0\n", bit, col); ++ return CMD_RET_FAILURE; ++} ++ ++static int do_nand_erase(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(), *part; ++ bool spread = false, force = false; ++ u64 off, size, end, limit; ++ struct erase_info ei; ++ char *ends; ++ int ret; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (strstr(argv[0], ".spread")) ++ spread = true; ++ ++ if (strstr(argv[0], ".force")) ++ force = true; ++ ++ if (spread && force) { ++ printf("spread and force must not be set at the same time\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 2) { ++ printf("Erase start offset/partition must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ part = nand_get_part(mtd, argv[1]); ++ if (part) { ++ off = part->offset; ++ ++ if (argc < 3) ++ size = part->size; ++ else ++ size = simple_strtoull(argv[2], NULL, 0); ++ ++ if (size > part->size) { ++ printf("Erase end offset is larger than partition size\n"); ++ printf("Erase size reduced to 0x%llx\n", part->size); ++ ++ size = part->size; ++ } ++ ++ limit = off + part->size; ++ } else { ++ off = simple_strtoull(argv[1], &ends, 0); ++ ++ if (ends == argv[1] || *ends) { ++ printf("Partition '%s' not found\n", argv[1]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 3) { ++ printf("Erase size offset must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ size = simple_strtoull(argv[2], NULL, 0); ++ ++ if (off + size > mtd->size) { ++ printf("Erase end offset is larger than flash size\n"); ++ ++ size = mtd->size - off; ++ printf("Erase size reduced to 0x%llx\n", size); ++ } ++ ++ limit = mtd->size; ++ } ++ ++ end = off + size; ++ off &= ~(u64)mtd->erasesize_mask; ++ end = (end + mtd->erasesize_mask) & (~(u64)mtd->erasesize_mask); ++ size = end - off; ++ ++ printf("Erasing from 0x%llx to 0x%llx, size 0x%llx ...\n", ++ off, end - 1, end - off); ++ ++ while (size && off < limit) { ++ if (mtd_block_isbad(mtd, off)) { ++ printf("Bad block at 0x%llx", off); ++ ++ if (spread) { ++ printf(" ... skipped\n"); ++ off += mtd->erasesize; ++ continue; ++ } ++ ++ if (!force) { ++ printf(" ... aborted\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ printf(" ... will be force erased\n"); ++ } ++ ++ memset(&ei, 0, sizeof(ei)); ++ ++ ei.mtd = mtd; ++ ei.addr = off; ++ ei.len = mtd->erasesize; ++ ei.scrub = force; ++ ++ ret = mtd_erase(mtd, &ei); ++ if (ret) { ++ printf("Erase failed at 0x%llx\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ off += mtd->erasesize; ++ size -= mtd->erasesize; ++ } ++ ++ printf("Succeeded\n"); ++ ++ return CMD_RET_SUCCESS; ++} ++ ++static bool is_empty_page(const u8 *buf, size_t size) ++{ ++ size_t i; ++ ++ for (i = 0; i < size; i++) { ++ if (buf[i] != 0xff) ++ return false; ++ } ++ ++ return true; ++} ++ ++static int do_nand_io_normal(int argc, char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(), *part; ++ bool spread = false, force = false, raw = false, writeff = false; ++ bool read = false, checkbad = true; ++ struct mtd_oob_ops io_op = {}; ++ size_t size, padding, chksz; ++ uintptr_t addr; ++ u64 off, offp; ++ char *ends; ++ u8 *buf; ++ int ret; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (!strncmp(argv[0], "read", 4)) ++ read = true; ++ ++ if (strstr(argv[0], ".spread")) ++ spread = true; ++ ++ if (strstr(argv[0], ".force")) ++ force = true; ++ ++ if (strstr(argv[0], ".raw")) ++ raw = true; ++ ++ if (strstr(argv[0], ".ff")) ++ writeff = true; ++ ++ if (spread && force) { ++ printf("spread and force must not be set at the same time\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 2) { ++ printf("Data address must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ addr = simple_strtoul(argv[1], NULL, 0); ++ ++ if (argc < 3) { ++ printf("Flash address/partition must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ part = nand_get_part(mtd, argv[2]); ++ if (part) { ++ if (argc < 4) { ++ off = 0; ++ } else { ++ off = simple_strtoull(argv[3], NULL, 0); ++ if (off + part->offset >= part->size) { ++ printf("Offset is larger than partition size\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ if (argc < 5) { ++ size = part->size - off; ++ } else { ++ size = simple_strtoul(argv[4], NULL, 0); ++ if (off + size > part->size) { ++ printf("Data size is too large\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ off += part->offset; ++ } else { ++ off = simple_strtoull(argv[2], &ends, 0); ++ ++ if (ends == argv[1] || *ends) { ++ printf("Partition '%s' not found\n", argv[2]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 4) { ++ printf("Data size must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ size = simple_strtoul(argv[3], NULL, 0); ++ if (off + size > mtd->size) { ++ printf("Data size is too large\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ buf = malloc(mtd->writesize); ++ if (!buf) { ++ printf("Failed to allocate buffer\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ printf("%s from 0x%llx to 0x%llx, size 0x%zx ...\n", ++ read ? "Reading" : "Writing", off, off + size - 1, size); ++ ++ while (size && off < mtd->size) { ++ if (checkbad || !(off & mtd->erasesize_mask)) { ++ offp = off & ~(u64)mtd->erasesize_mask; ++ ++ if (mtd_block_isbad(mtd, offp)) { ++ printf("Bad block at 0x%llx", offp); ++ ++ if (spread) { ++ printf(" ... skipped\n"); ++ off += mtd->erasesize; ++ checkbad = true; ++ continue; ++ } ++ ++ if (!force) { ++ printf(" ... aborted\n"); ++ goto err_out; ++ } ++ ++ printf(" ... continue\n"); ++ } ++ ++ checkbad = false; ++ } ++ ++ padding = off & mtd->writesize_mask; ++ chksz = mtd->writesize - padding; ++ chksz = min_t(size_t, chksz, size); ++ ++ offp = off & ~(u64)mtd->writesize_mask; ++ ++ memset(&io_op, 0, sizeof(io_op)); ++ io_op.mode = raw ? MTD_OPS_RAW : MTD_OPS_PLACE_OOB; ++ io_op.len = mtd->writesize; ++ ++ if (chksz < mtd->writesize) ++ io_op.datbuf = buf; ++ else ++ io_op.datbuf = (void *)addr; ++ ++ if (read) { ++ ret = mtd_read_oob(mtd, offp, &io_op); ++ if (ret && ret != -EUCLEAN && ret != -EBADMSG) ++ goto io_err; ++ ++ if (chksz < mtd->writesize) ++ memcpy((void *)addr, buf + padding, chksz); ++ } else { ++ if (chksz < mtd->writesize) { ++ memset(buf, 0xff, mtd->writesize); ++ memcpy(buf + padding, (void *)addr, chksz); ++ } ++ ++ if (is_empty_page(io_op.datbuf, io_op.len) && !writeff) ++ ret = 0; ++ else ++ ret = mtd_write_oob(mtd, offp, &io_op); ++ ++ if (ret) ++ goto io_err; ++ } ++ ++ size -= chksz; ++ addr += chksz; ++ off += chksz; ++ } ++ ++ if (!size) { ++ printf("Succeeded\n"); ++ ret = CMD_RET_SUCCESS; ++ goto out; ++ } ++ ++ printf("0x%zx byte%s remained for %s\n", size, size > 1 ? "s" : "", ++ read ? "read" : "write"); ++ goto err_out; ++ ++io_err: ++ printf("%s error %d at 0x%llx\n", read ? "Read" : "Write", ret, offp); ++ ++err_out: ++ ret = CMD_RET_FAILURE; ++ ++out: ++ free(buf); ++ return ret; ++} ++ ++static int do_nand_io_page(int argc, char *const argv[]) ++{ ++ struct mtd_info *mtd = nand_get_curr_dev(), *part; ++ bool spread = false, force = false, raw = false, autooob = false; ++ bool read = false, checkbad = true, writeff = false; ++ struct mtd_oob_ops io_op = {}; ++ uintptr_t addr; ++ u64 off, offp; ++ char *ends; ++ u32 count; ++ int ret; ++ ++ if (!mtd) ++ return CMD_RET_FAILURE; ++ ++ if (!strncmp(argv[0], "read", 4)) ++ read = true; ++ ++ if (strstr(argv[0], ".spread")) ++ spread = true; ++ ++ if (strstr(argv[0], ".force")) ++ force = true; ++ ++ if (strstr(argv[0], ".raw")) ++ raw = true; ++ ++ if (strstr(argv[0], ".auto")) ++ autooob = true; ++ ++ if (spread && force) { ++ printf("spread and force must not be set at the same time\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (raw && autooob) { ++ printf("raw and auto must not be set at the same time\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (argc < 2) { ++ printf("Data address must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ addr = simple_strtoul(argv[1], NULL, 0); ++ ++ if (argc < 3) { ++ printf("Flash address/partition must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ part = nand_get_part(mtd, argv[2]); ++ if (part) { ++ if (argc < 4) { ++ printf("Partition offset / page count must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ if (argc < 5) { ++ off = 0; ++ ++ count = simple_strtoul(argv[3], NULL, 0); ++ if (part->offset + count * mtd->writesize > part->size) { ++ printf("Page count exceeds partition size\n"); ++ return CMD_RET_FAILURE; ++ } ++ } else { ++ off = simple_strtoull(argv[3], NULL, 0); ++ if (off >= part->size) { ++ printf("Offset 0x%llx is larger than partition size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ off &= ~(u64)mtd->writesize_mask; ++ ++ count = simple_strtoul(argv[4], NULL, 0); ++ if (part->offset + off + count * mtd->writesize > part->size) { ++ printf("Page count exceeds partition size\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ off += part->offset; ++ } else { ++ off = simple_strtoull(argv[2], &ends, 0); ++ ++ if (ends == argv[1] || *ends) { ++ printf("Partition '%s' not found\n", argv[2]); ++ return CMD_RET_FAILURE; ++ } ++ ++ if (off >= mtd->size) { ++ printf("Offset 0x%llx is larger than flash size\n", off); ++ return CMD_RET_FAILURE; ++ } ++ ++ off &= ~(u64)mtd->writesize_mask; ++ ++ if (argc < 4) { ++ printf("Page count must be specified\n"); ++ return CMD_RET_USAGE; ++ } ++ ++ count = simple_strtoul(argv[3], NULL, 0); ++ if (off + count * mtd->writesize > mtd->size) { ++ printf("Page count exceeds flash size\n"); ++ return CMD_RET_FAILURE; ++ } ++ } ++ ++ printf("%s from 0x%llx to 0x%llx (+%u), count %u ...\n", ++ read ? "Reading" : "Writing", off, ++ off + count * mtd->writesize - 1, mtd->oobsize, count); ++ ++ while (count && off < mtd->size) { ++ if (checkbad || !(off & mtd->erasesize_mask)) { ++ offp = off & ~(u64)mtd->erasesize_mask; ++ ++ if (mtd_block_isbad(mtd, offp)) { ++ printf("Bad block at 0x%llx", offp); ++ ++ if (spread) { ++ printf(" ... skipped\n"); ++ off += mtd->erasesize; ++ checkbad = true; ++ continue; ++ } ++ ++ if (!force) { ++ printf(" ... aborted\n"); ++ return CMD_RET_FAILURE; ++ } ++ ++ printf(" ... continue\n"); ++ } ++ ++ checkbad = false; ++ } ++ ++ memset(&io_op, 0, sizeof(io_op)); ++ ++ if (raw) ++ io_op.mode = MTD_OPS_RAW; ++ else if (autooob) ++ io_op.mode = MTD_OPS_AUTO_OOB; ++ else ++ io_op.mode = MTD_OPS_PLACE_OOB; ++ ++ io_op.len = mtd->writesize; ++ io_op.ooblen = mtd->oobsize; ++ io_op.datbuf = (void *)addr; ++ io_op.oobbuf = io_op.datbuf + mtd->writesize; ++ ++ if (read) { ++ ret = mtd_read_oob(mtd, off, &io_op); ++ if (ret && ret != -EUCLEAN && ret != -EBADMSG) ++ goto io_err; ++ } else { ++ if (is_empty_page((void *)addr, mtd->writesize + mtd->oobsize) && !writeff) ++ ret = 0; ++ else ++ ret = mtd_write_oob(mtd, off, &io_op); ++ ++ if (ret) ++ goto io_err; ++ } ++ ++ count--; ++ addr += mtd->writesize + mtd->oobsize; ++ off += mtd->writesize; ++ } ++ ++ if (!count) { ++ printf("Succeeded\n"); ++ return CMD_RET_SUCCESS; ++ } ++ ++ printf("%u page%s remained for %s\n", count, count > 1 ? "s" : "", ++ read ? "read" : "write"); ++ return CMD_RET_FAILURE; ++ ++io_err: ++ printf("%s error %d at 0x%llx\n", read ? "Read" : "Write", ret, off); ++ return CMD_RET_FAILURE; ++} ++ ++static int do_nand_io(struct cmd_tbl *cmdtp, int flag, int argc, ++ char *const argv[]) ++{ ++ if (strstr(argv[0], ".oob")) ++ return do_nand_io_page(argc, argv); ++ ++ return do_nand_io_normal(argc, argv); ++} ++ ++#ifdef CONFIG_SYS_LONGHELP ++static char nand_help_text[] = ++ "- NAND flash R/W and debugging utility\n" ++ "nand list\n" ++ "nand info - Show active NAND devices\n" ++ "nand select <name> - Select active NAND devices\n" ++ "nand dump[.raw] <off>\n" ++ "nand bad\n" ++ "nand markbad <off>\n" ++ "nand bitflip <off> <col> <bit>\n" ++ "nand erase[.spread|.force] [<off> <size>|<part> [<size>]]\n" ++ "nand read[.spread|.force][.raw] <addr> <off> <size>\n" ++ " <addr> <part> [<off> [<size>]]\n" ++ "nand write[.spread|.force][.raw][.ff] <addr> <off> <size>\n" ++ " <addr> <part> [<off> [<size>]]\n" ++ "nand read.oob[.spread|.force][.raw|.auto] <addr> <off> <count>\n" ++ " <addr> <part> [<off>] <count>\n" ++ "nand write.oob[.spread|.force][.raw|.auto][.ff] <addr> <off> <count>\n" ++ " <addr> <part> [<off>] <count>\n"; ++#endif ++ ++U_BOOT_CMD_WITH_SUBCMDS(nand, "NAND utility", ++ nand_help_text, ++ U_BOOT_SUBCMD_MKENT(list, 1, 0, do_nand_list), ++ U_BOOT_SUBCMD_MKENT(info, 1, 0, do_nand_info), ++ U_BOOT_SUBCMD_MKENT(select, 2, 0, do_nand_select), ++ U_BOOT_SUBCMD_MKENT(dump, 2, 0, do_nand_dump), ++ U_BOOT_SUBCMD_MKENT(bad, 1, 0, do_nand_bad), ++ U_BOOT_SUBCMD_MKENT(markbad, 2, 0, do_nand_markbad), ++ U_BOOT_SUBCMD_MKENT(bitflip, 4, 0, do_nand_bitflip), ++ U_BOOT_SUBCMD_MKENT(erase, 3, 0, do_nand_erase), ++ U_BOOT_SUBCMD_MKENT(read, 5, 0, do_nand_io), ++ U_BOOT_SUBCMD_MKENT(write, 5, 0, do_nand_io) ++); diff --git a/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch new file mode 100644 index 00000000000..da09cd9c088 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-14-mtd-spi-nor-add-support-to-read-flash-unique-ID.patch @@ -0,0 +1,142 @@ +From c4172a95df8a57a66c70a8b9948b9600a01c4cb7 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 11:32:08 +0800 +Subject: [PATCH 49/71] mtd: spi-nor: add support to read flash unique ID + +This patch adds support to read unique ID from spi-nor flashes. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/spi/spi-nor-core.c | 95 ++++++++++++++++++++++++++++++++++ + include/linux/mtd/spi-nor.h | 2 + + 2 files changed, 97 insertions(+) + +--- a/drivers/mtd/spi/spi-nor-core.c ++++ b/drivers/mtd/spi/spi-nor-core.c +@@ -2854,6 +2854,100 @@ static int spi_nor_init_params(struct sp + return 0; + } + ++static int spi_nor_read_uuid(struct spi_nor *nor) ++{ ++ u8 read_opcode, addr_width, read_dummy; ++ loff_t addr; ++ u8 *uuid; ++ u8 uuid_len; ++ int shift = 0; ++ int ret; ++ int i; ++ struct spi_mem_op op; ++ ++ read_opcode = nor->read_opcode; ++ addr_width = nor->addr_width; ++ read_dummy = nor->read_dummy; ++ ++ switch (JEDEC_MFR(nor->info)) { ++ case SNOR_MFR_WINBOND: ++ uuid_len = 8; ++ nor->read_opcode = 0x4b; ++ nor->addr_width = 0; ++ addr = 0x0; ++ nor->read_dummy = 4; ++ break; ++ case SNOR_MFR_GIGADEVICE: ++ uuid_len = 16; ++ nor->read_opcode = 0x4b; ++ nor->addr_width = 3; ++ addr = 0x0; ++ nor->read_dummy = 1; ++ break; ++ case CFI_MFR_ST: ++ case SNOR_MFR_MICRON: ++ uuid_len = 17; ++ shift = 3; ++ nor->read_opcode = 0x9f; ++ nor->addr_width = 0; ++ addr = 0x0; ++ nor->read_dummy = 0; ++ break; ++ case SNOR_MFR_EON: ++ uuid_len = 12; ++ nor->read_opcode = 0x5a; ++ nor->addr_width = 3; ++ addr = 0x80; ++ nor->read_dummy = 1; ++ break; ++ /* Automotive only in SPANSION's NOR devices */ ++ case SNOR_MFR_SPANSION: ++ uuid_len = 11; ++ shift = 386; ++ nor->read_opcode = 0x9f; ++ nor->addr_width = 0; ++ addr = 0x0; ++ nor->read_dummy = 0; ++ break; ++ default: ++ printf("UUID not supported on this device.\n"); ++ return -ENOTSUPP; ++ } ++ ++ uuid = kmalloc((uuid_len + shift) * sizeof(*uuid), GFP_KERNEL); ++ if (!uuid) { ++ ret = -ENOMEM; ++ goto read_err; ++ } ++ memset(uuid, 0x0, (uuid_len + shift) * sizeof(*uuid)); ++ ++ op = (struct spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 0), ++ SPI_MEM_OP_ADDR(nor->addr_width, addr, 0), ++ SPI_MEM_OP_DUMMY(nor->read_dummy, 0), ++ SPI_MEM_OP_DATA_IN(uuid_len+shift, NULL, 0)); ++ ++ spi_nor_setup_op(nor, &op, nor->reg_proto); ++ ++ ret = spi_nor_read_write_reg(nor, &op, uuid); ++ if (ret < 0) { ++ dev_dbg(nor->dev, "error %d reading %x\n", ret, nor->read_opcode); ++ goto read_err; ++ } ++ ++ printf("UUID: 0x"); ++ for(i = 0; i<uuid_len; i++) ++ printf("%02x", uuid[i+shift]); ++ puts("\n"); ++ ++read_err: ++ nor->read_opcode = read_opcode; ++ nor->addr_width = addr_width; ++ nor->read_dummy = read_dummy; ++ kfree(uuid); ++ ++ return ret; ++} ++ + static int spi_nor_hwcaps2cmd(u32 hwcaps, const int table[][2], size_t size) + { + size_t i; +@@ -4051,6 +4145,7 @@ int spi_nor_scan(struct spi_nor *nor) + nor->write = spi_nor_write_data; + nor->read_reg = spi_nor_read_reg; + nor->write_reg = spi_nor_write_reg; ++ nor->read_uuid = spi_nor_read_uuid; + + nor->setup = spi_nor_default_setup; + +--- a/include/linux/mtd/spi-nor.h ++++ b/include/linux/mtd/spi-nor.h +@@ -29,6 +29,7 @@ + #define SNOR_MFR_SPANSION CFI_MFR_AMD + #define SNOR_MFR_SST CFI_MFR_SST + #define SNOR_MFR_WINBOND 0xef /* Also used by some Spansion */ ++#define SNOR_MFR_EON CFI_MFR_EON + #define SNOR_MFR_CYPRESS 0x34 + + /* +@@ -571,6 +572,7 @@ struct spi_nor { + void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops); + int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len); ++ int (*read_uuid)(struct spi_nor *nor); + + ssize_t (*read)(struct spi_nor *nor, loff_t from, + size_t len, u_char *read_buf); diff --git a/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch new file mode 100644 index 00000000000..f7cbd8d052c --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-15-cmd-sf-add-support-to-read-flash-unique-ID.patch @@ -0,0 +1,46 @@ +From e60939acbebd07161f3978d1c6f13123fdd2ebf2 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 11:27:02 +0800 +Subject: [PATCH 50/71] cmd: sf: add support to read flash unique ID + +This patch adds support to display unique ID from spi-nor flashes + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/sf.c | 13 ++++++++++++- + 1 file changed, 12 insertions(+), 1 deletion(-) + +--- a/cmd/sf.c ++++ b/cmd/sf.c +@@ -412,6 +412,14 @@ static int do_spi_protect(int argc, char + return ret == 0 ? 0 : 1; + } + ++static int do_spi_flash_read_uuid(void) ++{ ++ int ret = 0; ++ ret = flash->read_uuid(flash); ++ ++ return ret == 0 ? 0 : 1; ++} ++ + enum { + STAGE_ERASE, + STAGE_CHECK, +@@ -606,6 +614,8 @@ static int do_spi_flash(struct cmd_tbl * + ret = do_spi_flash_erase(argc, argv); + else if (IS_ENABLED(CONFIG_SPI_FLASH_LOCK) && strcmp(cmd, "protect") == 0) + ret = do_spi_protect(argc, argv); ++ else if (strcmp(cmd, "uuid") == 0) ++ ret = do_spi_flash_read_uuid(); + else if (IS_ENABLED(CONFIG_CMD_SF_TEST) && !strcmp(cmd, "test")) + ret = do_spi_flash_test(argc, argv); + else +@@ -636,6 +646,7 @@ U_BOOT_LONGHELP(sf, + #ifdef CONFIG_CMD_SF_TEST + "\nsf test offset len - run a very basic destructive test" + #endif ++ "sf uuid - read uuid from flash" + ); + + U_BOOT_CMD( diff --git a/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch new file mode 100644 index 00000000000..0438895fdba --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-16-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch @@ -0,0 +1,323 @@ +From 5a15437610e8e8c68dc347845a83d0cbad80ca08 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 19 Jan 2021 10:58:48 +0800 +Subject: [PATCH 51/71] cmd: bootmenu: add ability to select item by shortkey + +Add ability to use shortkey to select item for bootmenu command + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/bootmenu.c | 34 ++++++++++++++++++++++++----- + common/menu.c | 58 ++++++++++++++++++++++++++++++++++++++++++++++++-- + include/menu.h | 12 +++++++---- + 3 files changed, 93 insertions(+), 11 deletions(-) + +--- a/cmd/bootmenu.c ++++ b/cmd/bootmenu.c +@@ -89,6 +89,7 @@ static char *bootmenu_choice_entry(void + struct bootmenu_data *menu = data; + struct bootmenu_entry *iter; + enum bootmenu_key key = BKEY_NONE; ++ int choice = -1; + int i; + + cli_ch_init(cch); +@@ -96,10 +97,10 @@ static char *bootmenu_choice_entry(void + while (1) { + if (menu->delay >= 0) { + /* Autoboot was not stopped */ +- key = bootmenu_autoboot_loop(menu, cch); ++ key = bootmenu_autoboot_loop(menu, cch, &choice); + } else { + /* Some key was pressed, so autoboot was stopped */ +- key = bootmenu_loop(menu, cch); ++ key = bootmenu_loop(menu, cch, &choice); + } + + switch (key) { +@@ -113,6 +114,12 @@ static char *bootmenu_choice_entry(void + ++menu->active; + /* no menu key selected, regenerate menu */ + return NULL; ++ case BKEY_CHOICE: ++ menu->active = choice; ++ if (!menu->last_choiced) { ++ menu->last_choiced = true; ++ return NULL; ++ } + case BKEY_SELECT: + iter = menu->first; + for (i = 0; i < menu->active; ++i) +@@ -170,6 +177,9 @@ static int prepare_bootmenu_entry(struct + unsigned short int i = *index; + struct bootmenu_entry *entry = NULL; + struct bootmenu_entry *iter = *current; ++ char *choice_option; ++ char choice_char; ++ int len; + + while ((option = bootmenu_getoption(i))) { + +@@ -184,11 +194,24 @@ static int prepare_bootmenu_entry(struct + if (!entry) + return -ENOMEM; + +- entry->title = strndup(option, sep - option); ++ /* Add KEY_CHOICE support: '%d. %s\0' : len --> len + 4 */ ++ len = sep - option + 4; ++ choice_option = malloc(len); ++ if (!choice_option) { ++ free(entry->title); ++ free(entry); ++ return -ENOMEM; ++ } ++ if (!get_choice_char(i, &choice_char)) ++ len = snprintf(choice_option, len, "%c. %s", choice_char, option); ++ else ++ len = snprintf(choice_option, len, " %s", option); ++ entry->title = strndup(choice_option, len); + if (!entry->title) { + free(entry); + return -ENOMEM; + } ++ free(choice_option); + + entry->command = strdup(sep + 1); + if (!entry->command) { +@@ -334,6 +357,7 @@ static struct bootmenu_data *bootmenu_cr + menu->delay = delay; + menu->active = 0; + menu->first = NULL; ++ menu->last_choiced = false; + + default_str = env_get("bootmenu_default"); + if (default_str) +@@ -369,9 +393,9 @@ static struct bootmenu_data *bootmenu_cr + + /* Add Quit entry if entering U-Boot console is disabled */ + if (!IS_ENABLED(CONFIG_BOOTMENU_DISABLE_UBOOT_CONSOLE)) +- entry->title = strdup("U-Boot console"); ++ entry->title = strdup("0. U-Boot console"); + else +- entry->title = strdup("Quit"); ++ entry->title = strdup("0. Quit"); + + if (!entry->title) { + free(entry); +--- a/common/menu.c ++++ b/common/menu.c +@@ -49,6 +49,33 @@ struct menu { + int item_cnt; + }; + ++const char choice_chars[] = { ++ '1', '2', '3', '4', '5', '6', '7', '8', '9', ++ 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', ++ 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', ++ 'u', 'v', 'w', 'x', 'y', 'z' ++}; ++ ++static int find_choice(char choice) ++{ ++ int i; ++ ++ for (i = 0; i < ARRAY_SIZE(choice_chars); i++) ++ if (tolower(choice) == choice_chars[i]) ++ return i; ++ ++ return -1; ++} ++ ++int get_choice_char(int index, char *result) ++{ ++ if (index < ARRAY_SIZE(choice_chars)) ++ *result = choice_chars[index]; ++ else ++ return -1; ++ return 0; ++} ++ + /* + * An iterator function for menu items. callback will be called for each item + * in m, with m, a pointer to the item, and extra being passed to callback. If +@@ -428,7 +455,7 @@ int menu_destroy(struct menu *m) + } + + enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, +- struct cli_ch_state *cch) ++ struct cli_ch_state *cch, int *choice) + { + enum bootmenu_key key = BKEY_NONE; + int i, c; +@@ -463,6 +490,19 @@ enum bootmenu_key bootmenu_autoboot_loop + break; + default: + key = BKEY_NONE; ++ if (cch->esc_len || !choice) ++ break; ++ ++ *choice = find_choice(c); ++ if ((*choice >= 0 && ++ *choice < menu->count - 1)) { ++ key = BKEY_CHOICE; ++ } else if (c == '0') { ++ *choice = menu->count - 1; ++ key = BKEY_CHOICE; ++ } else { ++ key = BKEY_NONE; ++ } + break; + } + break; +@@ -483,7 +523,8 @@ enum bootmenu_key bootmenu_autoboot_loop + return key; + } + +-enum bootmenu_key bootmenu_conv_key(int ichar) ++enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar, ++ int *choice) + { + enum bootmenu_key key; + +@@ -515,6 +556,20 @@ enum bootmenu_key bootmenu_conv_key(int + case ' ': + key = BKEY_SPACE; + break; ++ case '0' ... '9': ++ case 'a' ... 'z': ++ if (choice && menu) { ++ *choice = find_choice(ichar); ++ if ((*choice >= 0 && *choice < menu->count - 1)) { ++ key = BKEY_CHOICE; ++ break; ++ } else if (ichar == '0') { ++ *choice = menu->count - 1; ++ key = BKEY_CHOICE; ++ break; ++ } ++ } ++ fallthrough; + default: + key = BKEY_NONE; + break; +@@ -524,11 +579,16 @@ enum bootmenu_key bootmenu_conv_key(int + } + + enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, +- struct cli_ch_state *cch) ++ struct cli_ch_state *cch, int *choice) + { + enum bootmenu_key key; + int c; + ++ if (menu->last_choiced) { ++ menu->last_choiced = false; ++ return BKEY_SELECT; ++ } ++ + c = cli_ch_process(cch, 0); + if (!c) { + while (!c && !tstc()) { +@@ -542,7 +602,7 @@ enum bootmenu_key bootmenu_loop(struct b + } + } + +- key = bootmenu_conv_key(c); ++ key = bootmenu_conv_key(menu, c, choice); + + return key; + } +--- a/include/menu.h ++++ b/include/menu.h +@@ -6,6 +6,8 @@ + #ifndef __MENU_H__ + #define __MENU_H__ + ++#include <linux/ctype.h> ++ + struct cli_ch_state; + struct menu; + +@@ -19,6 +21,8 @@ int menu_get_choice(struct menu *m, void + int menu_item_add(struct menu *m, char *item_key, void *item_data); + int menu_destroy(struct menu *m); + int menu_default_choice(struct menu *m, void **choice); ++/* Add KEY_CHOICE support */ ++int get_choice_char(int index, char *result); + + /** + * menu_show() Show a boot menu +@@ -41,6 +45,7 @@ struct bootmenu_data { + int active; /* active menu entry */ + int count; /* total count of menu entries */ + struct bootmenu_entry *first; /* first menu entry */ ++ bool last_choiced; + }; + + /** enum bootmenu_key - keys that can be returned by the bootmenu */ +@@ -51,6 +56,7 @@ enum bootmenu_key { + BKEY_SELECT, + BKEY_QUIT, + BKEY_SAVE, ++ BKEY_CHOICE, + + /* 'extra' keys, which are used by menus but not cedit */ + BKEY_PLUS, +@@ -81,7 +87,7 @@ enum bootmenu_key { + * anything else: KEY_NONE + */ + enum bootmenu_key bootmenu_autoboot_loop(struct bootmenu_data *menu, +- struct cli_ch_state *cch); ++ struct cli_ch_state *cch, int *choice); + + /** + * bootmenu_loop() - handle waiting for a keypress when autoboot is disabled +@@ -107,7 +113,7 @@ enum bootmenu_key bootmenu_autoboot_loop + * Space: BKEY_SPACE + */ + enum bootmenu_key bootmenu_loop(struct bootmenu_data *menu, +- struct cli_ch_state *cch); ++ struct cli_ch_state *cch, int *choice); + + /** + * bootmenu_conv_key() - Convert a U-Boot keypress into a menu key +@@ -115,6 +121,7 @@ enum bootmenu_key bootmenu_loop(struct b + * @ichar: Keypress to convert (ASCII, including control characters) + * Returns: Menu key that corresponds to @ichar, or BKEY_NONE if none + */ +-enum bootmenu_key bootmenu_conv_key(int ichar); ++enum bootmenu_key bootmenu_conv_key(struct bootmenu_data *menu, int ichar, ++ int *choice); + + #endif /* __MENU_H__ */ +--- a/cmd/eficonfig.c ++++ b/cmd/eficonfig.c +@@ -239,7 +239,7 @@ char *eficonfig_choice_entry(void *data) + cli_ch_init(cch); + + while (1) { +- key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch); ++ key = bootmenu_loop((struct bootmenu_data *)efi_menu, cch, NULL); + + switch (key) { + case BKEY_UP: +@@ -1838,7 +1838,7 @@ char *eficonfig_choice_change_boot_order + + cli_ch_init(cch); + while (1) { +- key = bootmenu_loop(NULL, cch); ++ key = bootmenu_loop(NULL, cch, NULL); + + switch (key) { + case BKEY_PLUS: +--- a/boot/bootflow_menu.c ++++ b/boot/bootflow_menu.c +@@ -235,7 +235,7 @@ int bootflow_menu_run(struct bootstd_pri + + key = 0; + if (ichar) { +- key = bootmenu_conv_key(ichar); ++ key = bootmenu_conv_key(NULL, ichar, NULL); + if (key == BKEY_NONE) + key = ichar; + } diff --git a/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch new file mode 100644 index 00000000000..f017ce92ade --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-17-common-spl-spl_nand-enable-CONFIG_SYS_NAND_U_BOOT_OF.patch @@ -0,0 +1,28 @@ +From 7ab891faaaf2b6126694352d4503dc40605a6aec Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 15:10:02 +0800 +Subject: [PATCH 52/71] common: spl: spl_nand: enable + CONFIG_SYS_NAND_U_BOOT_OFFS undefined + +Enable using spl_nand with CONFIG_SYS_NAND_U_BOOT_OFFS undefined since +mtk-snand does not require raw nand framework. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + common/spl/spl_nand.c | 4 ++++ + 1 file changed, 4 insertions(+) + +--- a/common/spl/spl_nand.c ++++ b/common/spl/spl_nand.c +@@ -17,7 +17,11 @@ + + uint32_t __weak spl_nand_get_uboot_raw_page(void) + { ++#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS + return CONFIG_SYS_NAND_U_BOOT_OFFS; ++#else ++ return 0; ++#endif + } + + #if defined(CONFIG_SPL_NAND_RAW_ONLY) diff --git a/package/boot/uboot-mediatek/patches/000-mtk-17-board-mt7629-add-support-for-booting-from-SPI-NAND.patch b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch index aa38b2745e3..ef20c2dfb6c 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-17-board-mt7629-add-support-for-booting-from-SPI-NAND.patch +++ b/package/boot/uboot-mediatek/patches/100-18-board-mt7629-add-support-for-booting-from-SPI-NAND.patch @@ -1,7 +1,7 @@ -From 47b386259625061b376f538055a4f3fbd0ab7fef Mon Sep 17 00:00:00 2001 +From 452dc98572f8353f77551bcce5a2ca8cd050f498 Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Wed, 3 Mar 2021 10:48:53 +0800 -Subject: [PATCH 17/21] board: mt7629: add support for booting from SPI-NAND +Subject: [PATCH 53/71] board: mt7629: add support for booting from SPI-NAND Add support for mt7629 to boot from SPI-NAND. Add a new defconfig for mt7629+spi-nand configuration. @@ -11,17 +11,19 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> arch/arm/dts/mt7629-rfb-u-boot.dtsi | 8 ++ arch/arm/dts/mt7629-rfb.dts | 10 +++ arch/arm/dts/mt7629.dtsi | 16 ++++ - board/mediatek/mt7629/Kconfig | 35 ++++++++- - configs/mt7629_nand_rfb_defconfig | 111 ++++++++++++++++++++++++++++ - include/configs/mt7629.h | 7 ++ - 6 files changed, 186 insertions(+), 1 deletion(-) + arch/arm/mach-mediatek/Kconfig | 4 +- + board/mediatek/mt7629/Kconfig | 40 ++++++++++ + board/mediatek/mt7629/mt7629_rfb.c | 5 ++ + configs/mt7629_nand_rfb_defconfig | 113 ++++++++++++++++++++++++++++ + 7 files changed, 195 insertions(+), 1 deletion(-) + create mode 100644 board/mediatek/mt7629/Kconfig create mode 100644 configs/mt7629_nand_rfb_defconfig --- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi +++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi @@ -40,3 +40,11 @@ &snfi { - u-boot,dm-pre-reloc; + bootph-all; }; + +&pinctrl { @@ -85,13 +87,28 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> snor: snor@11014000 { compatible = "mediatek,mtk-snor"; reg = <0x11014000 0x1000>; ---- a/board/mediatek/mt7629/Kconfig -+++ b/board/mediatek/mt7629/Kconfig -@@ -12,6 +12,39 @@ config MTK_SPL_PAD_SIZE +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -144,9 +144,11 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string -- default "media=nor" +- default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 ++ default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7622 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 || TARGET_MT7988 + default "lk=1" if TARGET_MT7623 + ++source "board/mediatek/mt7629/Kconfig" ++ + endif +--- /dev/null ++++ b/board/mediatek/mt7629/Kconfig +@@ -0,0 +1,40 @@ ++if TARGET_MT7629 ++ ++config MTK_BROM_HEADER_INFO ++ string + default "media=nor" if BOOT_FROM_SNOR + default "media=snand;nandinfo=2k+64" if BOOT_FROM_SNAND_2K_64 + default "media=snand;nandinfo=2k+128" if BOOT_FROM_SNAND_2K_128 @@ -126,49 +143,66 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +config MT7629_BOOT_FROM_SNAND + bool + default n ++ ++endif +--- a/board/mediatek/mt7629/mt7629_rfb.c ++++ b/board/mediatek/mt7629/mt7629_rfb.c +@@ -15,3 +15,8 @@ int board_init(void) - endif + return 0; + } ++ ++uint32_t spl_nand_get_uboot_raw_page(void) ++{ ++ return CONFIG_SPL_PAD_TO; ++} --- /dev/null +++ b/configs/mt7629_nand_rfb_defconfig -@@ -0,0 +1,111 @@ +@@ -0,0 +1,113 @@ +CONFIG_ARM=y +CONFIG_SYS_ARCH_TIMER=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x20000 -+CONFIG_ENV_OFFSET=0x100000 ++CONFIG_ENV_OFFSET=0x0 ++CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" +CONFIG_SPL_TEXT_BASE=0x201000 +CONFIG_TARGET_MT7629=y +CONFIG_BOOT_FROM_SNAND_2K_64=y -+CONFIG_SPL_SERIAL_SUPPORT=y -+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y ++CONFIG_SPL_SERIAL=y +CONFIG_SPL_STACK_R_ADDR=0x40800000 ++CONFIG_SYS_LOAD_ADDR=0x42007f1c +CONFIG_SPL_PAYLOAD="u-boot.img" +CONFIG_BUILD_TARGET="u-boot-mtk.bin" -+CONFIG_DEFAULT_DEVICE_TREE="mt7629-rfb" ++CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y ++CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41fffef0 +CONFIG_SPL_IMAGE="spl/u-boot-spl-mtk.bin" +CONFIG_FIT=y -+CONFIG_FIT_VERBOSE=y -+CONFIG_BOOTDELAY=3 ++# CONFIG_AUTOBOOT is not set +CONFIG_DEFAULT_FDT_FILE="mt7629-rfb" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y -+CONFIG_SYS_STDIO_DEREGISTER=y +# CONFIG_DISPLAY_BOARDINFO is not set ++CONFIG_SPL_MAX_SIZE=0x20000 ++CONFIG_SPL_FOOTPRINT_LIMIT=y ++CONFIG_SPL_MAX_FOOTPRINT=0x20000 +CONFIG_SPL_SYS_MALLOC_SIMPLE=y ++# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set ++CONFIG_SPL_STACK=0x106000 +CONFIG_SPL_STACK_R=y +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y -+CONFIG_SPL_WATCHDOG_SUPPORT=y ++CONFIG_SPL_WATCHDOG=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " -+CONFIG_CMD_BOOTMENU=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set ++CONFIG_SYS_BOOTM_LEN=0x4000000 ++CONFIG_CMD_BOOTMENU=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_BIND=y @@ -183,13 +217,10 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_LOG=y -+CONFIG_EFI_PARTITION=y -+# CONFIG_SPL_PARTITION_UUIDS is not set -+CONFIG_PARTITION_TYPE_GUID=y +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-parents" +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MTD=y -+CONFIG_ENV_MTD_NAME="spi-nand0" ++CONFIG_ENV_MTD_NAME="u-boot-env" +CONFIG_ENV_SIZE_REDUND=0x40000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y @@ -198,7 +229,6 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y -+CONFIG_BLK=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +# CONFIG_MMC is not set @@ -232,35 +262,13 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +CONFIG_SPL_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y -+CONFIG_DM_USB=y +# CONFIG_SPL_DM_USB is not set +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y +CONFIG_WDT_MTK=y -+CONFIG_FAT_WRITE=y ++# CONFIG_SHA256 is not set ++# CONFIG_SPL_SHA1 is not set +CONFIG_LZMA=y +CONFIG_SPL_LZMA=y +# CONFIG_EFI_LOADER is not set ---- a/include/configs/mt7629.h -+++ b/include/configs/mt7629.h -@@ -30,12 +30,19 @@ - - /* Defines for SPL */ - #define CONFIG_SPL_STACK 0x106000 -+#ifdef CONFIG_MT7629_BOOT_FROM_SNAND -+#define CONFIG_SPL_MAX_SIZE SZ_128K -+#define CONFIG_SPL_MAX_FOOTPRINT SZ_128K -+#define CONFIG_SPL_PAD_TO 0x20000 -+#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO -+#else - #define CONFIG_SPL_MAX_SIZE SZ_64K - #define CONFIG_SPL_MAX_FOOTPRINT SZ_64K - #define CONFIG_SPL_PAD_TO 0x10000 - - #define CONFIG_SPI_ADDR 0x30000000 - #define CONFIG_SYS_UBOOT_BASE (CONFIG_SPI_ADDR + CONFIG_SPL_PAD_TO) -+#endif - - /* SPL -> Uboot */ - #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \ diff --git a/package/boot/uboot-mediatek/patches/000-mtk-18-board-mt7622-use-new-spi-nand-driver.patch b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch index 2202911950c..6202ddf3b01 100644 --- a/package/boot/uboot-mediatek/patches/000-mtk-18-board-mt7622-use-new-spi-nand-driver.patch +++ b/package/boot/uboot-mediatek/patches/100-19-board-mt7622-use-new-spi-nand-driver.patch @@ -1,7 +1,7 @@ -From ec0d1899b035700a657721761ff6370b940450ab Mon Sep 17 00:00:00 2001 +From 4c1803cc08b1618d935c1386f43f43a4e9c97697 Mon Sep 17 00:00:00 2001 From: Weijie Gao <weijie.gao@mediatek.com> Date: Wed, 3 Mar 2021 10:51:43 +0800 -Subject: [PATCH 18/21] board: mt7622: use new spi-nand driver +Subject: [PATCH 54/71] board: mt7622: use new spi-nand driver Enable new spi-nand driver support for mt7622_rfb_defconfig @@ -14,7 +14,7 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> --- a/arch/arm/dts/mt7622-rfb.dts +++ b/arch/arm/dts/mt7622-rfb.dts -@@ -188,6 +188,13 @@ +@@ -196,6 +196,13 @@ }; }; @@ -26,11 +26,11 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +}; + &uart0 { - pinctrl-names = "default"; - pinctrl-0 = <&uart0_pins>; + status = "okay"; + }; --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi -@@ -53,6 +53,22 @@ +@@ -77,6 +77,22 @@ #size-cells = <0>; }; @@ -55,16 +55,16 @@ Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> reg = <0x11014000 0x1000>; --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig -@@ -15,6 +15,7 @@ CONFIG_LOG=y - CONFIG_SYS_PROMPT="MT7622> " +@@ -22,6 +22,7 @@ CONFIG_SYS_MAXARGS=8 + CONFIG_SYS_PBSIZE=1049 CONFIG_CMD_BOOTMENU=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_PCI=y CONFIG_CMD_SF_TEST=y CONFIG_CMD_PING=y -@@ -28,6 +29,10 @@ CONFIG_CLK=y - CONFIG_DM_MMC=y +@@ -41,6 +42,10 @@ CONFIG_SYSCON=y + CONFIG_CLK=y CONFIG_MMC_HS200_SUPPORT=y CONFIG_MMC_MTK=y +CONFIG_MTD=y diff --git a/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch new file mode 100644 index 00000000000..9dc1a577228 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-20-board-mt7981-add-reference-board-using-new-spi-nand-.patch @@ -0,0 +1,223 @@ +From d5841f8707dcb7a1f73607de67ab45dba93a56a4 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Fri, 29 Jul 2022 17:04:12 +0800 +Subject: [PATCH 55/71] board: mt7981: add reference board using new spi-nand + driver + +Add a new reference board using new spi-nand driver for SPI-NAND flash on +SNFI interface + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + arch/arm/dts/Makefile | 1 + + arch/arm/dts/mt7981-snfi-nand-rfb.dts | 132 +++++++++++++++++++++++++ + configs/mt7981_snfi_nand_rfb_defconfig | 57 +++++++++++ + 3 files changed, 190 insertions(+) + create mode 100644 arch/arm/dts/mt7981-snfi-nand-rfb.dts + create mode 100644 configs/mt7981_snfi_nand_rfb_defconfig + +--- a/arch/arm/dts/Makefile ++++ b/arch/arm/dts/Makefile +@@ -1425,6 +1425,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ + mt7623n-bananapi-bpi-r2.dtb \ + mt7629-rfb.dtb \ + mt7981-rfb.dtb \ ++ mt7981-snfi-nand-rfb.dtb \ + mt7981-emmc-rfb.dtb \ + mt7981-sd-rfb.dtb \ + mt7986a-bpi-r3-sd.dtb \ +--- /dev/null ++++ b/arch/arm/dts/mt7981-snfi-nand-rfb.dts +@@ -0,0 +1,132 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "mt7981-rfb"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ snfi_pins: snfi-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ ++ clk { ++ pins = "SPI0_CLK"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ /* pin15 as pwm0 */ ++ one_pwm_pins: one-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1"; ++ }; ++ }; ++ ++ /* pin15 as pwm0 and pin14 as pwm1 */ ++ two_pwm_pins: two-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++ ++ /* pin15 as pwm0, pin14 as pwm1, pin7 as pwm2 */ ++ three_pwm_pins: three-pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0", "pwm2"; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; ++}; ++ ++&snand { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&snfi_pins>; ++ status = "okay"; ++ quad-spi; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&two_pwm_pins>; ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/configs/mt7981_snfi_nand_rfb_defconfig +@@ -0,0 +1,57 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb" ++CONFIG_TARGET_MT7981=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++# CONFIG_AUTOBOOT is not set ++CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb" ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_UNLZ4 is not set ++# CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_SMC=y ++CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" ++CONFIG_MTDPARTS_DEFAULT="spi-nand0:1024k(bl2),512k(u-boot-env),2048k(factory),2048k(fip),65536k(ubi)" ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y diff --git a/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch new file mode 100644 index 00000000000..15e943b1c02 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-21-mtd-spi-nor-add-more-flash-ids.patch @@ -0,0 +1,76 @@ +From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Wed, 27 Jul 2022 16:32:17 +0800 +Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids + +Add more spi-nor flash ids + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/spi/spi-nor-core.c | 1 + + drivers/mtd/spi/spi-nor-ids.c | 23 ++++++++++++++++++++++- + 2 files changed, 23 insertions(+), 1 deletion(-) + +--- a/drivers/mtd/spi/spi-nor-core.c ++++ b/drivers/mtd/spi/spi-nor-core.c +@@ -674,6 +674,7 @@ static int set_4byte(struct spi_nor *nor + case SNOR_MFR_ISSI: + case SNOR_MFR_MACRONIX: + case SNOR_MFR_WINBOND: ++ case SNOR_MFR_EON: + if (need_wren) + write_enable(nor); + +--- a/drivers/mtd/spi/spi-nor-ids.c ++++ b/drivers/mtd/spi/spi-nor-ids.c +@@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] = + { INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) }, + { INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, + { INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) }, +- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) }, ++ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, ++ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) }, + #endif + #ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */ +@@ -149,6 +150,11 @@ const struct flash_info spi_nor_ids[] = + {INFO("gd55x02g", 0xc8481C, 0, 64 * 1024, 4096, SECT_4K | + SPI_NOR_OCTAL_READ | SPI_NOR_4B_OPCODES)}, + { ++ INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512, ++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | ++ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) ++ }, ++ { + INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) +@@ -474,6 +480,16 @@ const struct flash_info spi_nor_ids[] = + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { ++ INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512, ++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | ++ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) ++ }, ++ { ++ INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024, ++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | ++ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) ++ }, ++ { + INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) +@@ -523,6 +539,11 @@ const struct flash_info spi_nor_ids[] = + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, + { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, ++ { ++ INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024, ++ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | ++ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) ++ }, + { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, diff --git a/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch new file mode 100644 index 00000000000..20489d87266 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-22-mtd-spi-nand-backport-from-upstream-kernel.patch @@ -0,0 +1,549 @@ +From 8d0665327819c41fce2c8d50f19c967b22eae564 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Wed, 27 Jul 2022 16:36:13 +0800 +Subject: [PATCH 57/71] mtd: spi-nand: backport from upstream kernel + +Backport new features from upstream kernel + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/nand/spi/Kconfig | 1 + + drivers/mtd/nand/spi/Makefile | 2 +- + drivers/mtd/nand/spi/core.c | 102 ++++++---- + drivers/mtd/nand/spi/etron.c | 181 +++++++++++++++++ + drivers/mtd/nand/spi/gigadevice.c | 322 ++++++++++++++++++++++++++---- + drivers/mtd/nand/spi/macronix.c | 173 +++++++++++++--- + drivers/mtd/nand/spi/micron.c | 50 ++--- + drivers/mtd/nand/spi/toshiba.c | 66 +++--- + drivers/mtd/nand/spi/winbond.c | 164 ++++++++++++--- + include/linux/mtd/spinand.h | 87 +++++--- + 10 files changed, 923 insertions(+), 225 deletions(-) + create mode 100644 drivers/mtd/nand/spi/etron.c + +--- a/drivers/mtd/nand/spi/Makefile ++++ b/drivers/mtd/nand/spi/Makefile +@@ -1,4 +1,4 @@ + # SPDX-License-Identifier: GPL-2.0 + +-spinand-objs := core.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o ++spinand-objs := core.o etron.o gigadevice.o macronix.o micron.o paragon.o toshiba.o winbond.o + obj-$(CONFIG_MTD_SPI_NAND) += spinand.o +--- a/drivers/mtd/nand/spi/core.c ++++ b/drivers/mtd/nand/spi/core.c +@@ -822,6 +822,7 @@ static const struct nand_ops spinand_ops + }; + + static const struct spinand_manufacturer *spinand_manufacturers[] = { ++ &etron_spinand_manufacturer, + &gigadevice_spinand_manufacturer, + ¯onix_spinand_manufacturer, + µn_spinand_manufacturer, +--- /dev/null ++++ b/drivers/mtd/nand/spi/etron.c +@@ -0,0 +1,181 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2020 Etron Technology, Inc. ++ * ++ */ ++#ifndef __UBOOT__ ++#include <malloc.h> ++#include <linux/device.h> ++#include <linux/kernel.h> ++#endif ++#include <linux/bug.h> ++#include <linux/mtd/spinand.h> ++ ++#define SPINAND_MFR_ETRON 0xD5 ++ ++#define STATUS_ECC_LIMIT_BITFLIPS (3 << 4) ++ ++static SPINAND_OP_VARIANTS(read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(write_cache_variants, ++ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), ++ SPINAND_PROG_LOAD(true, 0, NULL, 0)); ++ ++static SPINAND_OP_VARIANTS(update_cache_variants, ++ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), ++ SPINAND_PROG_LOAD(false, 0, NULL, 0)); ++ ++static int etron_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (14 * section) + 72; ++ region->length = 14; ++ ++ return 0; ++} ++ ++static int etron_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ if (section) { ++ region->offset = 18 * section; ++ region->length = 18; ++ } else { ++ /* section 0 has one byte reserved for bad block mark */ ++ region->offset = 2; ++ region->length = 16; ++ } ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops etron_ooblayout = { ++ .ecc = etron_ooblayout_ecc, ++ .rfree = etron_ooblayout_free, ++}; ++ ++static int etron_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ struct nand_device *nand = spinand_to_nand(spinand); ++ ++ switch (status & STATUS_ECC_MASK) { ++ case STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ case STATUS_ECC_HAS_BITFLIPS: ++ return nand->eccreq.strength >> 1; ++ ++ case STATUS_ECC_LIMIT_BITFLIPS: ++ return nand->eccreq.strength; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ ++static const struct spinand_info etron_spinand_table[] = { ++ /* EM73C 1Gb 3.3V */ ++ SPINAND_INFO("EM73C044VCF", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x25), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xD 2Gb */ ++ SPINAND_INFO("EM73D044VCR", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x41), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM73D044VCO", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3A), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78D044VCM", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8E), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xE 4Gb */ ++ SPINAND_INFO("EM73E044VCE", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x3B), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78E044VCD", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x8F), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ /* EM7xF044VCA 8Gb */ ++ SPINAND_INFO("EM73F044VCA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++ SPINAND_INFO("EM78F044VCA", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x8D), ++ NAND_MEMORG(1, 4096, 256, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&etron_ooblayout, etron_ecc_get_status)), ++}; ++ ++static const struct spinand_manufacturer_ops etron_spinand_manuf_ops = { ++}; ++ ++const struct spinand_manufacturer etron_spinand_manufacturer = { ++ .id = SPINAND_MFR_ETRON, ++ .name = "Etron", ++ .chips = etron_spinand_table, ++ .nchips = ARRAY_SIZE(etron_spinand_table), ++ .ops = &etron_spinand_manuf_ops, ++}; +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -43,6 +43,24 @@ static SPINAND_OP_VARIANTS(read_cache_va + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(true, 0, 1, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_OP_3A(false, 0, 0, NULL, 0)); + ++/* Q5 1Gb */ ++static SPINAND_OP_VARIANTS(dummy2_read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ ++/* Q5 2Gb & 4Gb */ ++static SPINAND_OP_VARIANTS(dummy4_read_cache_variants, ++ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0), ++ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0)); ++ + static SPINAND_OP_VARIANTS(write_cache_variants, + SPINAND_PROG_LOAD_X4(true, 0, NULL, 0), + SPINAND_PROG_LOAD(true, 0, NULL, 0)); +@@ -268,7 +286,45 @@ static int gd5fxgq4ufxxg_ecc_get_status( + return -EINVAL; + } + ++static int esmt_1_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 8; ++ region->length = 8; ++ ++ return 0; ++} ++ ++static int esmt_1_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 6; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops esmt_1_ooblayout = { ++ .ecc = esmt_1_ooblayout_ecc, ++ .rfree = esmt_1_ooblayout_free, ++ }; ++ + static const struct spinand_info gigadevice_spinand_table[] = { ++ SPINAND_INFO("F50L1G41LB", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x01), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&esmt_1_ooblayout, NULL)), + SPINAND_INFO("GD5F1GQ4xA", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xf1), + NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), +@@ -349,6 +405,87 @@ static const struct spinand_info gigadev + SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, + gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GQ5UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x52), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ6UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x55), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GM7UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x91), ++ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GM7UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x92), ++ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GM8UExxG", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0x95), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 1, 1, 1), ++ NAND_ECCREQ(8, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq4uexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F1GQ5UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy2_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F2GQ5UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32), ++ NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ SPINAND_INFO("GD5F4GQ6UExxH", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35), ++ NAND_MEMORG(1, 2048, 64, 64, 4096, 40, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&dummy4_read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ SPINAND_HAS_QE_BIT, ++ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout, ++ gd5fxgq5xexxg_ecc_get_status)), ++ + }; + + static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = { +--- a/drivers/mtd/nand/spi/winbond.c ++++ b/drivers/mtd/nand/spi/winbond.c +@@ -18,6 +18,23 @@ + + #define WINBOND_CFG_BUF_READ BIT(3) + ++#define W25N02_N04KV_STATUS_ECC_MASK (3 << 4) ++#define W25N02_N04KV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS (1 << 4) ++#define W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS (3 << 4) ++#define W25N02_N04KV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++ ++#define W25N01_M02GV_STATUS_ECC_MASK (3 << 4) ++#define W25N01_M02GV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N01_M02GV_STATUS_ECC_1_BITFLIPS (1 << 4) ++#define W25N01_M02GV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++ ++#define W25N01KV_STATUS_ECC_MASK (3 << 4) ++#define W25N01KV_STATUS_ECC_NO_BITFLIPS (0 << 4) ++#define W25N01KV_STATUS_ECC_1_3_BITFLIPS (1 << 4) ++#define W25N01KV_STATUS_ECC_4_BITFLIPS (3 << 4) ++#define W25N01KV_STATUS_ECC_UNCOR_ERROR (2 << 4) ++ + static SPINAND_OP_VARIANTS(read_cache_variants, + SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), + SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0), +@@ -34,6 +51,35 @@ static SPINAND_OP_VARIANTS(update_cache_ + SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), + SPINAND_PROG_LOAD(false, 0, NULL, 0)); + ++static int w25n02kv_n04kv_ooblayout_ecc(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 64; ++ region->length = 16; ++ ++ return 0; ++} ++ ++static int w25n02kv_n04kv_ooblayout_free(struct mtd_info *mtd, int section, ++ struct mtd_oob_region *region) ++{ ++ if (section > 3) ++ return -ERANGE; ++ ++ region->offset = (16 * section) + 2; ++ region->length = 14; ++ ++ return 0; ++} ++ ++static const struct mtd_ooblayout_ops w25n02kv_n04kv_ooblayout = { ++ .ecc = w25n02kv_n04kv_ooblayout_ecc, ++ .rfree = w25n02kv_n04kv_ooblayout_free, ++}; ++ + static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) + { +@@ -106,6 +152,58 @@ static const struct mtd_ooblayout_ops w2 + .rfree = w25n02kv_ooblayout_free, + }; + ++static int w25n01kv_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & W25N01KV_STATUS_ECC_MASK) { ++ case W25N01KV_STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case W25N01KV_STATUS_ECC_1_3_BITFLIPS: ++ return 3; ++ ++ case W25N01KV_STATUS_ECC_4_BITFLIPS: ++ return 4; ++ ++ case W25N01KV_STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ ++static int w25n02kv_n04kv_ecc_get_status(struct spinand_device *spinand, ++ u8 status) ++{ ++ switch (status & W25N02_N04KV_STATUS_ECC_MASK) { ++ case W25N02_N04KV_STATUS_ECC_NO_BITFLIPS: ++ return 0; ++ ++ case W25N02_N04KV_STATUS_ECC_1_4_BITFLIPS: ++ return 3; ++ ++ case W25N02_N04KV_STATUS_ECC_5_8_BITFLIPS: ++ return 4; ++ ++ /* W25N02_N04KV_use internal 8bit ECC algorithm. ++ * But the ECC strength is 4 bit requried. ++ * Return 3 if the bit bit flip count less than 5. ++ * Return 4 if the bit bit flip count more than 5 to 8. ++ */ ++ ++ case W25N02_N04KV_STATUS_ECC_UNCOR_ERROR: ++ return -EBADMSG; ++ ++ default: ++ break; ++ } ++ ++ return -EINVAL; ++} ++ + static int w25n02kv_ecc_get_status(struct spinand_device *spinand, + u8 status) + { +@@ -163,6 +261,15 @@ static const struct spinand_info winbond + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25m02gv_ooblayout, NULL)), ++ SPINAND_INFO("W25N01KV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xae, 0x21), ++ NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, w25n01kv_ecc_get_status)), + SPINAND_INFO("W25N02KV", + SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x22), + NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1), +@@ -172,6 +279,16 @@ static const struct spinand_info winbond + &update_cache_variants), + 0, + SPINAND_ECCINFO(&w25n02kv_ooblayout, w25n02kv_ecc_get_status)), ++ SPINAND_INFO("W25N04KV", ++ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xaa, 0x23), ++ NAND_MEMORG(1, 2048, 128, 64, 4096, 80, 2, 1, 1), ++ NAND_ECCREQ(4, 512), ++ SPINAND_INFO_OP_VARIANTS(&read_cache_variants, ++ &write_cache_variants, ++ &update_cache_variants), ++ 0, ++ SPINAND_ECCINFO(&w25n02kv_n04kv_ooblayout, ++ w25n02kv_n04kv_ecc_get_status)), + }; + + static int winbond_spinand_init(struct spinand_device *spinand) +--- a/include/linux/mtd/spinand.h ++++ b/include/linux/mtd/spinand.h +@@ -245,6 +245,7 @@ struct spinand_manufacturer { + }; + + /* SPI NAND manufacturers */ ++extern const struct spinand_manufacturer etron_spinand_manufacturer; + extern const struct spinand_manufacturer gigadevice_spinand_manufacturer; + extern const struct spinand_manufacturer macronix_spinand_manufacturer; + extern const struct spinand_manufacturer micron_spinand_manufacturer; diff --git a/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch new file mode 100644 index 00000000000..5c90e24ebf5 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-23-mmc-mtk-sd-add-support-to-display-verbose-error-log.patch @@ -0,0 +1,78 @@ +From 793bed29e78cc54d989333d756fef51efaca4e56 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Tue, 26 Jul 2022 09:29:18 +0800 +Subject: [PATCH 58/71] mmc: mtk-sd: add support to display verbose error log + +Add an option to enable debug log, and also display verbose error log for +both command and data. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mmc/Kconfig | 8 ++++++++ + drivers/mmc/Makefile | 4 ++++ + drivers/mmc/mtk-sd.c | 24 +++++++++++++++--------- + 3 files changed, 27 insertions(+), 9 deletions(-) + +--- a/drivers/mmc/Kconfig ++++ b/drivers/mmc/Kconfig +@@ -815,6 +815,14 @@ config MMC_MTK + This is needed if support for any SD/SDIO/MMC devices is required. + If unsure, say N. + ++config MMC_MTK_DEBUG ++ bool "Display verbose error log" ++ default n ++ depends on MMC_MTK ++ help ++ Enable this option to allow verbose error log being displayed for ++ debugging. ++ + endif + + config FSL_SDHC_V2_3 +--- a/drivers/mmc/Makefile ++++ b/drivers/mmc/Makefile +@@ -82,3 +82,7 @@ obj-$(CONFIG_RENESAS_SDHI) += tmio-comm + obj-$(CONFIG_MMC_BCM2835) += bcm2835_sdhost.o + obj-$(CONFIG_MMC_MTK) += mtk-sd.o + obj-$(CONFIG_MMC_SDHCI_F_SDH30) += f_sdh30.o ++ ++ifdef CONFIG_MMC_MTK_DEBUG ++CFLAGS_mtk-sd.o += -DDEBUG ++endif +--- a/drivers/mmc/mtk-sd.c ++++ b/drivers/mmc/mtk-sd.c +@@ -779,18 +779,24 @@ static int msdc_ops_send_cmd(struct udev + if (cmd_ret && + !(cmd_ret == -EIO && + (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK || +- cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))) ++ cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))) { ++ dev_dbg(dev, "MSDC start command failure with %d, cmd=%d, arg=0x%x\n", ++ cmd_ret, cmd->cmdidx, cmd->cmdarg); + return cmd_ret; +- +- if (data) { +- data_ret = msdc_start_data(host, data); +- if (cmd_ret) +- return cmd_ret; +- else +- return data_ret; + } + +- return 0; ++ if (!data) ++ return cmd_ret; ++ ++ data_ret = msdc_start_data(host, data); ++ if (cmd_ret) ++ return cmd_ret; ++ ++ if (data_ret) ++ dev_dbg(dev, "MSDC start data failure with %d, cmd=%d, arg=0x%x\n", ++ data_ret, cmd->cmdidx, cmd->cmdarg); ++ ++ return data_ret; + } + + static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) diff --git a/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch new file mode 100644 index 00000000000..ed74eab1e4b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-24-cmd-ubi-make-volume-find-create-remove-APIs-public.patch @@ -0,0 +1,58 @@ +From dd66fc817f7ab7a4fcab9836a9251a8f64f329df Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 16:58:36 +0800 +Subject: [PATCH 59/71] cmd: ubi: make volume find/create/remove APIs public + +Export ubi_create_vol/ubi_find_volume/ubi_remove_vol to public so that they +can be used by other programs. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/ubi.c | 8 ++++---- + include/ubi_uboot.h | 4 ++++ + 2 files changed, 8 insertions(+), 4 deletions(-) + +--- a/cmd/ubi.c ++++ b/cmd/ubi.c +@@ -213,8 +213,8 @@ bad: + return err; + } + +-static int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, +- bool skipcheck) ++int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, ++ bool skipcheck) + { + struct ubi_mkvol_req req; + int err; +@@ -247,7 +247,7 @@ static int ubi_create_vol(char *volume, + return ubi_create_volume(ubi, &req); + } + +-static struct ubi_volume *ubi_find_volume(char *volume) ++struct ubi_volume *ubi_find_volume(char *volume) + { + struct ubi_volume *vol = NULL; + int i; +@@ -262,7 +262,7 @@ static struct ubi_volume *ubi_find_volum + return NULL; + } + +-static int ubi_remove_vol(char *volume) ++int ubi_remove_vol(char *volume) + { + int err, reserved_pebs, i; + struct ubi_volume *vol; +--- a/include/ubi_uboot.h ++++ b/include/ubi_uboot.h +@@ -51,6 +51,10 @@ extern void ubi_exit(void); + extern int ubi_part(char *part_name, const char *vid_header_offset); + extern int ubi_volume_write(char *volume, void *buf, size_t size); + extern int ubi_volume_read(char *volume, char *buf, size_t size); ++extern int ubi_create_vol(char *volume, int64_t size, int dynamic, int vol_id, ++ bool skipcheck); ++extern struct ubi_volume *ubi_find_volume(char *volume); ++extern int ubi_remove_vol(char *volume); + + extern struct ubi_device *ubi_devices[]; + int cmd_ubifs_mount(char *vol_name); diff --git a/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch b/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch new file mode 100644 index 00000000000..d023b004f76 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-25-cmd-ubi-allow-creating-volume-with-all-free-spaces.patch @@ -0,0 +1,27 @@ +From f6a4130959af1e6d13d616203e42ed3c894666ad Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 17:00:00 +0800 +Subject: [PATCH 60/71] cmd: ubi: allow creating volume with all free spaces + +Allow creating volume with all free spaces by giving a negative size value. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + cmd/ubi.c | 6 +++++- + 1 file changed, 5 insertions(+), 1 deletion(-) + +--- a/cmd/ubi.c ++++ b/cmd/ubi.c +@@ -226,7 +226,11 @@ int ubi_create_vol(char *volume, int64_t + + req.vol_id = vol_id; + req.alignment = 1; +- req.bytes = size; ++ ++ if (size < 0) ++ req.bytes = ubi->avail_pebs * ubi->leb_size; ++ else ++ req.bytes = size; + + strcpy(req.name, volume); + req.name_len = strlen(volume); diff --git a/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch new file mode 100644 index 00000000000..fb8d15ddf9b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-26-env-ubi-add-support-to-create-environment-volume-if-.patch @@ -0,0 +1,72 @@ +From fc0c70a7c6a088072d0c77e5a59d5e9b7754c6db Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 17:01:20 +0800 +Subject: [PATCH 61/71] env: ubi: add support to create environment volume if + it does not exist + +Add an option to allow environment volume being auto created if not exist. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + env/Kconfig | 6 ++++++ + env/ubi.c | 20 ++++++++++++++++++++ + 2 files changed, 26 insertions(+) + +--- a/env/Kconfig ++++ b/env/Kconfig +@@ -689,6 +689,12 @@ config ENV_UBI_VOLUME_REDUND + help + Name of the redundant volume that you want to store the environment in. + ++config ENV_UBI_VOLUME_CREATE ++ bool "Create UBI volume if not exist" ++ depends on ENV_IS_IN_UBI ++ help ++ Create the UBI volume if it does not exist. ++ + config ENV_UBI_VID_OFFSET + int "ubi environment VID offset" + depends on ENV_IS_IN_UBI +--- a/env/ubi.c ++++ b/env/ubi.c +@@ -106,6 +106,18 @@ static int env_ubi_save(void) + #endif /* CONFIG_SYS_REDUNDAND_ENVIRONMENT */ + #endif /* CONFIG_CMD_SAVEENV */ + ++int __weak env_ubi_volume_create(const char *volume) ++{ ++ struct ubi_volume *vol; ++ ++ vol = ubi_find_volume((char *)volume); ++ if (vol) ++ return 0; ++ ++ return ubi_create_vol((char *)volume, CONFIG_ENV_SIZE, true, ++ UBI_VOL_NUM_AUTO, false); ++} ++ + #ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT + static int env_ubi_load(void) + { +@@ -135,6 +147,11 @@ static int env_ubi_load(void) + return -EIO; + } + ++ if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) { ++ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME); ++ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME_REDUND); ++ } ++ + read1_fail = ubi_volume_read(CONFIG_ENV_UBI_VOLUME, (void *)tmp_env1, + CONFIG_ENV_SIZE); + if (read1_fail) +@@ -172,6 +189,9 @@ static int env_ubi_load(void) + return -EIO; + } + ++ if (IS_ENABLED(CONFIG_ENV_UBI_VOLUME_CREATE)) ++ env_ubi_volume_create(CONFIG_ENV_UBI_VOLUME); ++ + if (ubi_volume_read(CONFIG_ENV_UBI_VOLUME, buf, CONFIG_ENV_SIZE)) { + printf("\n** Unable to read env from %s:%s **\n", + CONFIG_ENV_UBI_PART, CONFIG_ENV_UBI_VOLUME); diff --git a/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch new file mode 100644 index 00000000000..9c83e6cc25d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-27-mtd-ubi-add-support-for-UBI-end-of-filesystem-marker.patch @@ -0,0 +1,66 @@ +From 189a2fe96931ef3ea0e187c8e9bfa589c2a0ae10 Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Mon, 25 Jul 2022 17:24:56 +0800 +Subject: [PATCH 62/71] mtd: ubi: add support for UBI end-of-filesystem marker + used by OpenWrt + +Add support for UBI end-of-filesystem marker used by OpenWrt to allow +attaching a new UBI mtd partition just upgraded. + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + drivers/mtd/ubi/attach.c | 25 ++++++++++++++++++++++--- + drivers/mtd/ubi/ubi.h | 1 + + 2 files changed, 23 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/ubi/attach.c ++++ b/drivers/mtd/ubi/attach.c +@@ -803,6 +803,13 @@ out_unlock: + return err; + } + ++static bool ec_hdr_has_eof(struct ubi_ec_hdr *ech) ++{ ++ return ech->padding1[0] == 'E' && ++ ech->padding1[1] == 'O' && ++ ech->padding1[2] == 'F'; ++} ++ + /** + * scan_peb - scan and process UBI headers of a PEB. + * @ubi: UBI device description object +@@ -833,9 +840,21 @@ static int scan_peb(struct ubi_device *u + return 0; + } + +- err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); +- if (err < 0) +- return err; ++ if (!ai->eof_found) { ++ err = ubi_io_read_ec_hdr(ubi, pnum, ech, 0); ++ if (err < 0) ++ return err; ++ ++ if (ec_hdr_has_eof(ech)) { ++ pr_notice("UBI: EOF marker found, PEBs from %d will be erased\n", ++ pnum); ++ ai->eof_found = true; ++ } ++ } ++ ++ if (ai->eof_found) ++ err = UBI_IO_FF_BITFLIPS; ++ + switch (err) { + case 0: + break; +--- a/drivers/mtd/ubi/ubi.h ++++ b/drivers/mtd/ubi/ubi.h +@@ -746,6 +746,7 @@ struct ubi_attach_info { + int mean_ec; + uint64_t ec_sum; + int ec_count; ++ bool eof_found; + struct kmem_cache *aeb_slab_cache; + }; + diff --git a/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch new file mode 100644 index 00000000000..f22449ae76f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/100-29-board-mediatek-wire-up-NMBM-support.patch @@ -0,0 +1,238 @@ +From 6792b57b3ba61ca6d69ea4a13a58bed65fc5da87 Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel@makrotopia.org> +Date: Sun, 7 Aug 2022 04:04:46 +0200 +Subject: [PATCH] board: mediatek: wire-up NMBM support + +--- + board/mediatek/mt7622/mt7622_rfb.c | 38 +++++++++++++++++++++ + board/mediatek/mt7629/mt7629_rfb.c | 38 +++++++++++++++++++++ + board/mediatek/mt7981/mt7981_rfb.c | 52 ++++++++++++++++++++++++++++ + board/mediatek/mt7986/mt7986_rfb.c | 54 ++++++++++++++++++++++++++++++ + 4 files changed, 182 insertions(+) + +--- a/board/mediatek/mt7622/mt7622_rfb.c ++++ b/board/mediatek/mt7622/mt7622_rfb.c +@@ -10,6 +10,11 @@ + #include <init.h> + #include <asm/global_data.h> + ++#include <mtd.h> ++#include <linux/mtd/mtd.h> ++#include <nmbm/nmbm.h> ++#include <nmbm/nmbm-mtd.h> ++ + DECLARE_GLOBAL_DATA_PTR; + + int board_init(void) +@@ -23,3 +28,36 @@ int board_late_init(void) + env_relocate(); + return 0; + } ++ ++int board_nmbm_init(void) ++{ ++#ifdef CONFIG_ENABLE_NAND_NMBM ++ struct mtd_info *lower, *upper; ++ int ret; ++ ++ printf("\n"); ++ printf("Initializing NMBM ...\n"); ++ ++ mtd_probe_devices(); ++ ++ lower = get_mtd_device_nm("spi-nand0"); ++ if (IS_ERR(lower) || !lower) { ++ printf("Lower MTD device 'spi-nand0' not found\n"); ++ return 0; ++ } ++ ++ ret = nmbm_attach_mtd(lower, ++ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK, ++ CONFIG_NMBM_MAX_RATIO, ++ CONFIG_NMBM_MAX_BLOCKS, &upper); ++ ++ printf("\n"); ++ ++ if (ret) ++ return 0; ++ ++ add_mtd_device(upper); ++#endif ++ ++ return 0; ++} +--- a/board/mediatek/mt7629/mt7629_rfb.c ++++ b/board/mediatek/mt7629/mt7629_rfb.c +@@ -6,6 +6,11 @@ + #include <common.h> + #include <asm/global_data.h> + ++#include <mtd.h> ++#include <linux/mtd/mtd.h> ++#include <nmbm/nmbm.h> ++#include <nmbm/nmbm-mtd.h> ++ + DECLARE_GLOBAL_DATA_PTR; + + int board_init(void) +@@ -20,3 +25,36 @@ uint32_t spl_nand_get_uboot_raw_page(voi + { + return CONFIG_SPL_PAD_TO; + } ++ ++int board_nmbm_init(void) ++{ ++#ifdef CONFIG_ENABLE_NAND_NMBM ++ struct mtd_info *lower, *upper; ++ int ret; ++ ++ printf("\n"); ++ printf("Initializing NMBM ...\n"); ++ ++ mtd_probe_devices(); ++ ++ lower = get_mtd_device_nm("spi-nand0"); ++ if (IS_ERR(lower) || !lower) { ++ printf("Lower MTD device 'spi-nand0' not found\n"); ++ return 0; ++ } ++ ++ ret = nmbm_attach_mtd(lower, ++ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK, ++ CONFIG_NMBM_MAX_RATIO, ++ CONFIG_NMBM_MAX_BLOCKS, &upper); ++ ++ printf("\n"); ++ ++ if (ret) ++ return 0; ++ ++ add_mtd_device(upper); ++#endif ++ ++ return 0; ++} +--- a/board/mediatek/mt7981/mt7981_rfb.c ++++ b/board/mediatek/mt7981/mt7981_rfb.c +@@ -4,7 +4,58 @@ + * Author: Sam Shih <sam.shih@mediatek.com> + */ + ++#include <common.h> ++#include <config.h> ++#include <env.h> ++#include <init.h> ++#include <asm/global_data.h> ++ ++#include <mtd.h> ++#include <linux/mtd/mtd.h> ++#include <nmbm/nmbm.h> ++#include <nmbm/nmbm-mtd.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ + int board_init(void) + { + return 0; + } ++ ++int board_late_init(void) ++{ ++ gd->env_valid = 1; //to load environment variable from persistent store ++ env_relocate(); ++ return 0; ++} ++ ++int board_nmbm_init(void) ++{ ++#ifdef CONFIG_ENABLE_NAND_NMBM ++ struct mtd_info *lower, *upper; ++ int ret; ++ ++ printf("\n"); ++ printf("Initializing NMBM ...\n"); ++ ++ mtd_probe_devices(); ++ ++ lower = get_mtd_device_nm("spi-nand0"); ++ if (IS_ERR(lower) || !lower) { ++ printf("Lower MTD device 'spi-nand0' not found\n"); ++ return 0; ++ } ++ ++ ret = nmbm_attach_mtd(lower, NMBM_F_CREATE, CONFIG_NMBM_MAX_RATIO, ++ CONFIG_NMBM_MAX_BLOCKS, &upper); ++ ++ printf("\n"); ++ ++ if (ret) ++ return 0; ++ ++ add_mtd_device(upper); ++#endif ++ ++ return 0; ++} +--- a/board/mediatek/mt7986/mt7986_rfb.c ++++ b/board/mediatek/mt7986/mt7986_rfb.c +@@ -4,7 +4,60 @@ + * Author: Sam Shih <sam.shih@mediatek.com> + */ + ++#include <common.h> ++#include <config.h> ++#include <env.h> ++#include <init.h> ++#include <asm/global_data.h> ++ ++#include <mtd.h> ++#include <linux/mtd/mtd.h> ++#include <nmbm/nmbm.h> ++#include <nmbm/nmbm-mtd.h> ++ ++DECLARE_GLOBAL_DATA_PTR; ++ + int board_init(void) + { + return 0; + } ++ ++int board_late_init(void) ++{ ++ gd->env_valid = 1; //to load environment variable from persistent store ++ env_relocate(); ++ return 0; ++} ++ ++int board_nmbm_init(void) ++{ ++#ifdef CONFIG_ENABLE_NAND_NMBM ++ struct mtd_info *lower, *upper; ++ int ret; ++ ++ printf("\n"); ++ printf("Initializing NMBM ...\n"); ++ ++ mtd_probe_devices(); ++ ++ lower = get_mtd_device_nm("spi-nand0"); ++ if (IS_ERR(lower) || !lower) { ++ printf("Lower MTD device 'spi-nand0' not found\n"); ++ return 0; ++ } ++ ++ ret = nmbm_attach_mtd(lower, ++ NMBM_F_CREATE | NMBM_F_EMPTY_PAGE_ECC_OK, ++ CONFIG_NMBM_MAX_RATIO, ++ CONFIG_NMBM_MAX_BLOCKS, &upper); ++ ++ printf("\n"); ++ ++ if (ret) ++ return 0; ++ ++ add_mtd_device(upper); ++#endif ++ ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/100-scripts-remove-dependency-on-swig.patch b/package/boot/uboot-mediatek/patches/100-scripts-remove-dependency-on-swig.patch deleted file mode 100644 index 05055893854..00000000000 --- a/package/boot/uboot-mediatek/patches/100-scripts-remove-dependency-on-swig.patch +++ /dev/null @@ -1,24 +0,0 @@ -From b137ca16b54c67d76714ea5a0138741959b0dc29 Mon Sep 17 00:00:00 2001 -From: David Bauer <mail@david-bauer.net> -Date: Mon, 13 Jul 2020 23:37:37 +0200 -Subject: [PATCH] scripts: remove dependency on swig - -Don't build the libfdt tool, as it has a dependency on swig (which -OpenWrt does not ship). - -This requires more hacks, as of-platdata generation does not work -without it. - -Signed-off-by: David Bauer <mail@david-bauer.net> ---- - scripts/dtc/Makefile | 2 -- - 1 file changed, 2 deletions(-) - ---- a/scripts/dtc/Makefile -+++ b/scripts/dtc/Makefile -@@ -18,5 +18,3 @@ HOSTCFLAGS_dtc-parser.tab.o := -I$(src) - # dependencies on generated files need to be listed explicitly - $(obj)/dtc-lexer.lex.o: $(obj)/dtc-parser.tab.h - --# Added for U-Boot --subdir-$(CONFIG_PYLIBFDT) += pylibfdt diff --git a/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch new file mode 100644 index 00000000000..747aa2e5dac --- /dev/null +++ b/package/boot/uboot-mediatek/patches/103-mt7988-enable-pstore.patch @@ -0,0 +1,33 @@ +--- a/arch/arm/dts/mt7988.dtsi ++++ b/arch/arm/dts/mt7988.dtsi +@@ -62,6 +62,30 @@ + #clock-cells = <0>; + }; + ++ psci { ++ compatible = "arm,psci-0.2"; ++ method = "smc"; ++ }; ++ ++ reserved-memory { ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ ++ /* 64 KiB reserved for ramoops/pstore */ ++ ramoops@42ff0000 { ++ compatible = "ramoops"; ++ reg = <0 0x42ff0000 0 0x10000>; ++ record-size = <0x1000>; ++ }; ++ ++ /* 320 KiB reserved for ARM Trusted Firmware (BL31+BL32) */ ++ secmon_reserved: secmon@43000000 { ++ reg = <0 0x43000000 0 0x50000>; ++ no-map; ++ }; ++ }; ++ + hwver: hwver { + compatible = "mediatek,hwver", "syscon"; + reg = <0 0x8000000 0 0x1000>; diff --git a/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch new file mode 100644 index 00000000000..da1d985688b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/105-configs-add-usefull-stuff-to-mt7988-rfb.patch @@ -0,0 +1,314 @@ +--- a/configs/mt7988_sd_rfb_defconfig ++++ b/configs/mt7988_sd_rfb_defconfig +@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + # CONFIG_AUTOBOOT is not set + CONFIG_DEFAULT_FDT_FILE="mt7988-sd-rfb" + CONFIG_LOGLEVEL=7 +@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_CLK=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_PWM=y + CONFIG_CMD_MMC=y + CONFIG_CMD_MTD=y + CONFIG_CMD_PING=y ++CONFIG_CMD_SF=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 + CONFIG_DOS_PARTITION=y + CONFIG_EFI_PARTITION=y + CONFIG_PARTITION_TYPE_GUID=y +@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y + CONFIG_MMC_HS200_SUPPORT=y + CONFIG_MMC_MTK=y + CONFIG_MTD=y +--- a/configs/mt7988_rfb_defconfig ++++ b/configs/mt7988_rfb_defconfig +@@ -11,6 +11,24 @@ CONFIG_DEBUG_UART_BASE=0x11000000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_SD_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + # CONFIG_AUTOBOOT is not set + CONFIG_DEFAULT_FDT_FILE="mt7988-rfb" + CONFIG_LOGLEVEL=7 +@@ -22,15 +40,118 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_CLK=y + CONFIG_CMD_DM=y + CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_PWM=y + CONFIG_CMD_MMC=y + CONFIG_CMD_MTD=y + CONFIG_CMD_PING=y ++CONFIG_CMD_SF=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 + CONFIG_DOS_PARTITION=y + CONFIG_EFI_PARTITION=y + CONFIG_PARTITION_TYPE_GUID=y +@@ -46,6 +167,9 @@ CONFIG_PROT_TCP=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y + CONFIG_MMC_HS200_SUPPORT=y + CONFIG_MMC_MTK=y + CONFIG_MTD=y diff --git a/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch new file mode 100644 index 00000000000..3a3f8d0e1ed --- /dev/null +++ b/package/boot/uboot-mediatek/patches/106-configs-sync-mt7981-rfb-storage.patch @@ -0,0 +1,129 @@ +--- a/configs/mt7981_rfb_defconfig ++++ b/configs/mt7981_rfb_defconfig +@@ -30,6 +30,9 @@ CONFIG_CMD_MTD=y + CONFIG_CMD_SF_TEST=y + CONFIG_CMD_PING=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y + CONFIG_REGMAP=y +--- a/configs/mt7981_snfi_nand_rfb_defconfig ++++ b/configs/mt7981_snfi_nand_rfb_defconfig +@@ -1,11 +1,12 @@ + CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y + CONFIG_POSITION_INDEPENDENT=y + CONFIG_ARCH_MEDIATEK=y + CONFIG_TEXT_BASE=0x41e00000 + CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 +-CONFIG_ENV_SIZE=0x20000 + CONFIG_DEFAULT_DEVICE_TREE="mt7981-snfi-nand-rfb" ++CONFIG_SYS_PROMPT="MT7981> " + CONFIG_TARGET_MT7981=y + CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 +@@ -15,7 +16,6 @@ CONFIG_DEBUG_UART=y + CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +-CONFIG_SYS_PROMPT="MT7981> " + CONFIG_SYS_CBSIZE=512 + CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_NETBSD is not set +@@ -29,8 +29,6 @@ CONFIG_CMD_GPIO=y + CONFIG_CMD_MTD=y + CONFIG_CMD_PING=y + CONFIG_CMD_SMC=y +-CONFIG_MTDIDS_DEFAULT="spi-nand0=spi-nand0" +-CONFIG_MTDPARTS_DEFAULT="spi-nand0:1024k(bl2),512k(u-boot-env),2048k(factory),2048k(fip),65536k(ubi)" + CONFIG_CMD_UBI=y + CONFIG_CMD_UBI_RENAME=y + CONFIG_ENV_OVERWRITE=y +@@ -45,7 +43,6 @@ CONFIG_DM_MTD=y + CONFIG_MTK_SPI_NAND=y + CONFIG_MTK_SPI_NAND_MTD=y + CONFIG_PHY_FIXED=y +-CONFIG_DM_ETH=y + CONFIG_MEDIATEK_ETH=y + CONFIG_PINCTRL=y + CONFIG_PINCONF=y +@@ -55,3 +52,4 @@ CONFIG_MTK_POWER_DOMAIN=y + CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y + CONFIG_HEXDUMP=y ++CONFIG_LMB_MAX_REGIONS=64 +--- /dev/null ++++ b/configs/mt7981_nor_rfb_defconfig +@@ -0,0 +1,68 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-rfb" ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_TARGET_MT7981=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++# CONFIG_AUTOBOOT is not set ++CONFIG_DEFAULT_FDT_FILE="mt7981-rfb" ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_UNLZ4 is not set ++# CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_SMC=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++# CONFIG_MMC is not set ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_SFDP_SUPPORT=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_ISSI=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_XTX=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPIM=y ++CONFIG_HEXDUMP=y ++CONFIG_LMB_MAX_REGIONS=64 diff --git a/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch new file mode 100644 index 00000000000..bd4c6b55f03 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/107-configs-add-useful-options-to-mt7981-rfb.patch @@ -0,0 +1,474 @@ +--- a/configs/mt7981_emmc_rfb_defconfig ++++ b/configs/mt7981_emmc_rfb_defconfig +@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y +-# CONFIG_AUTOBOOT is not set ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_MMC_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + CONFIG_DEFAULT_FDT_FILE="mt7981-emmc-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +@@ -24,9 +39,23 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set + # CONFIG_CMD_UNLZ4 is not set + # CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_GPT_RENAME=y +@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y + CONFIG_CMD_READ=y + CONFIG_CMD_PING=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y + CONFIG_CMD_FAT=y + CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_PARTITION_TYPE_GUID=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGEX=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y +--- a/configs/mt7981_rfb_defconfig ++++ b/configs/mt7981_rfb_defconfig +@@ -11,7 +11,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y +-# CONFIG_AUTOBOOT is not set ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + CONFIG_DEFAULT_FDT_FILE="mt7981-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +@@ -22,23 +38,74 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set + # CONFIG_CMD_UNLZ4 is not set + # CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MTD=y +-CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 + CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_SF=y ++CONFIG_CMD_SF_TEST=y + CONFIG_CMD_SMC=y + CONFIG_CMD_UBI=y + CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGEX=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y + # CONFIG_MMC is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_SPI_NAND=y +--- a/configs/mt7981_sd_rfb_defconfig ++++ b/configs/mt7981_sd_rfb_defconfig +@@ -13,7 +13,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y +-# CONFIG_AUTOBOOT is not set ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_MMC_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + CONFIG_DEFAULT_FDT_FILE="mt7981-sd-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +@@ -24,9 +39,23 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set + # CONFIG_CMD_UNLZ4 is not set + # CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_GPT=y + CONFIG_CMD_GPT_RENAME=y +@@ -36,13 +65,35 @@ CONFIG_CMD_PART=y + CONFIG_CMD_READ=y + CONFIG_CMD_PING=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y + CONFIG_CMD_FAT=y + CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF=y ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_PARTITION_TYPE_GUID=y + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGEX=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y +--- a/configs/mt7981_snfi_nand_rfb_defconfig ++++ b/configs/mt7981_snfi_nand_rfb_defconfig +@@ -12,7 +12,23 @@ CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y +-# CONFIG_AUTOBOOT is not set ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_NAND_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + CONFIG_DEFAULT_FDT_FILE="mt7981-snfi-nand-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +@@ -22,22 +38,73 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set + # CONFIG_CMD_UNLZ4 is not set + # CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MTD=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++# CONFIG_MTD_RAW_NAND is not set ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF=y ++CONFIG_CMD_SF_TEST=y + CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_SMC=y + CONFIG_CMD_UBI=y + CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y + CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGEX=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y + # CONFIG_MMC is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTK_SPI_NAND=y +--- a/configs/mt7981_nor_rfb_defconfig ++++ b/configs/mt7981_nor_rfb_defconfig +@@ -12,7 +12,22 @@ CONFIG_DEBUG_UART_BASE=0x11002000 + CONFIG_DEBUG_UART_CLOCK=40000000 + CONFIG_SYS_LOAD_ADDR=0x46000000 + CONFIG_DEBUG_UART=y +-# CONFIG_AUTOBOOT is not set ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SPI_BOOT=y ++CONFIG_BOOTSTD_DEFAULTS=y ++CONFIG_BOOTSTD_FULL=y + CONFIG_DEFAULT_FDT_FILE="mt7981-rfb" + CONFIG_LOGLEVEL=7 + CONFIG_LOG=y +@@ -22,21 +37,66 @@ CONFIG_SYS_PBSIZE=1049 + # CONFIG_BOOTM_PLAN9 is not set + # CONFIG_BOOTM_RTEMS is not set + # CONFIG_BOOTM_VXWORKS is not set +-# CONFIG_CMD_ELF is not set + # CONFIG_CMD_UNLZ4 is not set + # CONFIG_CMD_UNZIP is not set ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_ELF=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + CONFIG_CMD_GPIO=y + CONFIG_CMD_MTD=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF=y + CONFIG_CMD_SF_TEST=y + CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y + CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="u-boot-env" ++CONFIG_ENV_SIZE_REDUND=0x4000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0x0 + CONFIG_ENV_OVERWRITE=y + CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGEX=y + CONFIG_REGMAP=y + CONFIG_SYSCON=y + CONFIG_CLK=y + # CONFIG_MMC is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y + CONFIG_MTD=y + CONFIG_DM_MTD=y + CONFIG_MTD_SPI_NAND=y diff --git a/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch new file mode 100644 index 00000000000..a58c81b6568 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/108-dts-arm64-mt7981-rfb-add-mtd-partitions.patch @@ -0,0 +1,140 @@ +--- a/arch/arm/dts/mt7981-rfb.dts ++++ b/arch/arm/dts/mt7981-rfb.dts +@@ -143,6 +143,37 @@ + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ factory: partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x0200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x4000000>; ++ }; ++ }; + }; + }; + +@@ -164,6 +195,37 @@ + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@00000 { ++ label = "BL2"; ++ reg = <0x00000 0x0040000>; ++ }; ++ ++ partition@40000 { ++ label = "u-boot-env"; ++ reg = <0x40000 0x0010000>; ++ }; ++ ++ partition@50000 { ++ label = "Factory"; ++ reg = <0x50000 0x00B0000>; ++ }; ++ ++ partition@100000 { ++ label = "FIP"; ++ reg = <0x100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "firmware"; ++ reg = <0x180000 0xE00000>; ++ }; ++ }; + }; + }; + +--- a/arch/arm/dts/mt7981-snfi-nand-rfb.dts ++++ b/arch/arm/dts/mt7981-snfi-nand-rfb.dts +@@ -107,11 +107,11 @@ + }; + + mmc0_pins_default: mmc0default { +- mux { +- function = "flash"; +- groups = "emmc_45"; +- }; +- }; ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ }; + }; + + &snand { +@@ -119,6 +119,42 @@ + pinctrl-0 = <&snfi_pins>; + status = "okay"; + quad-spi; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "BL2"; ++ reg = <0x00000 0x0100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ factory: partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0200000>; ++ }; ++ ++ partition@380000 { ++ label = "FIP"; ++ reg = <0x380000 0x0200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x4000000>; ++ }; ++ }; ++ }; + }; + + &pwm { diff --git a/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch new file mode 100644 index 00000000000..3bf033f8143 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/110-no-kwbimage.patch @@ -0,0 +1,10 @@ +--- a/tools/Makefile ++++ b/tools/Makefile +@@ -116,7 +116,6 @@ dumpimage-mkimage-objs := aisimage.o \ + imximage.o \ + imx8image.o \ + imx8mimage.o \ +- kwbimage.o \ + generated/lib/md5.o \ + lpc32xximage.o \ + mxsimage.o \ diff --git a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch index 4dfe5062678..9a9224963d4 100644 --- a/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch +++ b/package/boot/uboot-mediatek/patches/120-use-xz-instead-of-lzma.patch @@ -1,6 +1,6 @@ --- a/Makefile +++ b/Makefile -@@ -1004,7 +1004,7 @@ quiet_cmd_pad_cat = CAT $@ +@@ -1083,7 +1083,7 @@ quiet_cmd_pad_cat = CAT $@ cmd_pad_cat = $(cmd_objcopy) && $(append) || { rm -f $@; false; } quiet_cmd_lzma = LZMA $@ diff --git a/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch new file mode 100644 index 00000000000..86a424e8b76 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/130-fix-mkimage-host-build.patch @@ -0,0 +1,24 @@ +--- a/tools/image-host.c ++++ b/tools/image-host.c +@@ -1137,6 +1137,7 @@ static int fit_config_add_verification_d + * 2) get public key (X509_get_pubkey) + * 3) provide der format (d2i_RSAPublicKey) + */ ++#ifdef CONFIG_TOOLS_LIBCRYPTO + static int read_pub_key(const char *keydir, const void *name, + unsigned char **pubkey, int *pubkey_len) + { +@@ -1190,6 +1191,13 @@ err_cert: + fclose(f); + return ret; + } ++#else ++static int read_pub_key(const char *keydir, const void *name, ++ unsigned char **pubkey, int *pubkey_len) ++{ ++ return -ENOSYS; ++} ++#endif + + int fit_pre_load_data(const char *keydir, void *keydest, void *fit) + { diff --git a/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch new file mode 100644 index 00000000000..f8e86599527 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/160-net-phy-add-support-for-Airoha-ethernet-PHY-driver.patch @@ -0,0 +1,1929 @@ +From 70157a6148ad47734f1dc646b4157ca83cc5df9f Mon Sep 17 00:00:00 2001 +From: Weijie Gao <weijie.gao@mediatek.com> +Date: Thu, 13 Jul 2023 16:34:48 +0800 +Subject: [PATCH] net: phy: add support for Airoha ethernet PHY driver + +This patch adds support for Airoha ethernet PHY driver. + +If GMAC2 of your board connects to Airoha EN8801S, please change the eth +node as follow: + +ð { + status = "okay"; + mediatek,gmac-id = <1>; + mediatek,sgmiisys = <&sgmiisys1>; + phy-mode = "sgmii"; + phy-handle = <&phy5>; + + phy5: eth-phy@5 { + reg = <24>; + }; +}; + +If GMAC2 of your board connects to Airoha EN8811H, please change the eth +node as follow: + +ð { + status = "okay"; + mediatek,gmac-id = <1>; + mediatek,sgmiisys = <&sgmiisys1>; + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + + fixed-link { + speed = <2500>; + full-duplex; + }; + + phy5: eth-phy@5 { + reg = <15>; + }; +}; + +Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> +--- + .../drivers/net/phy/Kconfig | 15 + + .../drivers/net/phy/Makefile | 2 + + .../drivers/net/phy/air_en8801s.c | 633 ++ + .../drivers/net/phy/air_en8801s.h | 267 + + .../drivers/net/phy/air_en8811h.c | 649 ++ + .../drivers/net/phy/air_en8811h.h | 160 + + .../drivers/net/phy/air_en8811h_fw.h | 9227 +++++++++++++++++ + 7 files changed, 10953 insertions(+) + create mode 100644 drivers/net/phy/air_en8801s.c + create mode 100644 drivers/net/phy/air_en8801s.h + create mode 100644 drivers/net/phy/air_en8811h.c + create mode 100644 drivers/net/phy/air_en8811h.h + create mode 100644 drivers/net/phy/air_en8811h_fw.h + +--- a/drivers/net/phy/Kconfig ++++ b/drivers/net/phy/Kconfig +@@ -77,6 +77,37 @@ config PHY_ADIN + help + Add support for configuring RGMII on Analog Devices ADIN PHYs. + ++menuconfig PHY_AIROHA ++ bool "Airoha Ethernet PHYs support" ++ ++config PHY_AIROHA_EN8801S ++ bool "Airoha Ethernet EN8801S support" ++ depends on PHY_AIROHA ++ help ++ AIROHA EN8801S supported. ++ ++config PHY_AIROHA_EN8811H ++ bool "Airoha Ethernet EN8811H support" ++ depends on PHY_AIROHA ++ help ++ AIROHA EN8811H supported. ++ ++choice ++ prompt "Location of the Airoha PHY firmware" ++ default PHY_AIROHA_FW_IN_UBI ++ depends on PHY_AIROHA_EN8811H ++ ++config PHY_AIROHA_FW_IN_MMC ++ bool "Airoha firmware in MMC boot1 partition" ++ ++config PHY_AIROHA_FW_IN_UBI ++ bool "Airoha firmware in UBI volume en8811h-fw on NAND flash" ++ ++config PHY_AIROHA_FW_IN_MTD ++ bool "Airoha firmware in MTD partition on raw flash" ++ ++endchoice ++ + menuconfig PHY_AQUANTIA + bool "Aquantia Ethernet PHYs support" + select PHY_GIGE +--- a/drivers/net/phy/Makefile ++++ b/drivers/net/phy/Makefile +@@ -11,6 +11,8 @@ obj-$(CONFIG_MV88E6352_SWITCH) += mv88e6 + obj-$(CONFIG_PHYLIB) += phy.o + obj-$(CONFIG_PHYLIB_10G) += generic_10g.o + obj-$(CONFIG_PHY_ADIN) += adin.o ++obj-$(CONFIG_PHY_AIROHA_EN8801S) += air_en8801s.o ++obj-$(CONFIG_PHY_AIROHA_EN8811H) += air_en8811h.o + obj-$(CONFIG_PHY_AQUANTIA) += aquantia.o + obj-$(CONFIG_PHY_ATHEROS) += atheros.o + obj-$(CONFIG_PHY_BROADCOM) += broadcom.o +--- /dev/null ++++ b/drivers/net/phy/air_en8801s.c +@@ -0,0 +1,633 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/************************************************* ++ * FILE NAME: air_en8801s.c ++ * PURPOSE: ++ * EN8801S PHY Driver for Uboot ++ * NOTES: ++ * ++ * Copyright (C) 2023 Airoha Technology Corp. ++ *************************************************/ ++ ++/* INCLUDE FILE DECLARATIONS ++ */ ++#include <common.h> ++#include <phy.h> ++#include <errno.h> ++#include <version.h> ++#include "air_en8801s.h" ++ ++#if AIR_UBOOT_REVISION > 0x202004 ++#include <linux/delay.h> ++#endif ++ ++static struct phy_device *s_phydev = 0; ++/****************************************************** ++ * The following led_cfg example is for reference only. ++ * LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0, ++ * LED6 10/100M/LINK/ACT (GPIO9) <-> BASE_T_LED1, ++ * LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2, ++ ******************************************************/ ++/* User-defined.B */ ++#define AIR_LED_SUPPORT ++#ifdef AIR_LED_SUPPORT ++static const AIR_BASE_T_LED_CFG_T led_cfg[4] = ++{ ++ /* ++ * LED Enable, GPIO, LED Polarity, LED ON, LED Blink ++ */ ++ {LED_ENABLE, 5, AIR_ACTIVE_LOW, BASE_T_LED0_ON_CFG, BASE_T_LED0_BLK_CFG}, /* BASE-T LED0 */ ++ {LED_ENABLE, 9, AIR_ACTIVE_LOW, BASE_T_LED1_ON_CFG, BASE_T_LED1_BLK_CFG}, /* BASE-T LED1 */ ++ {LED_ENABLE, 8, AIR_ACTIVE_LOW, BASE_T_LED2_ON_CFG, BASE_T_LED2_BLK_CFG}, /* BASE-T LED2 */ ++ {LED_DISABLE, 1, AIR_ACTIVE_LOW, BASE_T_LED3_ON_CFG, BASE_T_LED3_BLK_CFG} /* BASE-T LED3 */ ++}; ++static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M; ++#endif ++/* User-defined.E */ ++/************************************************************************ ++ * F U N C T I O N S ++ ************************************************************************/ ++/* Airoha MII read function */ ++static int airoha_cl22_read(struct mii_dev *bus, int phy_addr, int phy_register) ++{ ++ int read_data = bus->read(bus, phy_addr, MDIO_DEVAD_NONE, phy_register); ++ ++ if (read_data < 0) ++ return -EIO; ++ return read_data; ++} ++ ++/* Airoha MII write function */ ++static int airoha_cl22_write(struct mii_dev *bus, int phy_addr, int phy_register, int write_data) ++{ ++ int ret = bus->write(bus, phy_addr, MDIO_DEVAD_NONE, phy_register, write_data); ++ ++ return ret; ++} ++ ++static int airoha_cl45_write(struct phy_device *phydev, int devad, int reg, int val) ++{ ++ int ret = 0; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, val); ++ AIR_RTN_ERR(ret); ++ return ret; ++} ++ ++static int airoha_cl45_read(struct phy_device *phydev, int devad, int reg) ++{ ++ int read_data, ret; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad); ++ AIR_RTN_ERR(ret); ++ read_data = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG); ++ if (read_data < 0) ++ return -EIO; ++ return read_data; ++} ++ ++/* EN8801 PBUS write function */ ++int airoha_pbus_write(struct mii_dev *bus, int pbus_addr, int pbus_reg, unsigned long pbus_data) ++{ ++ int ret = 0; ++ ++ ret = airoha_cl22_write(bus, pbus_addr, 0x1F, (pbus_reg >> 6)); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl22_write(bus, pbus_addr, ((pbus_reg >> 2) & 0xf), (pbus_data & 0xFFFF)); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl22_write(bus, pbus_addr, 0x10, (pbus_data >> 16)); ++ AIR_RTN_ERR(ret); ++ return ret; ++} ++ ++/* EN8801 PBUS read function */ ++unsigned long airoha_pbus_read(struct mii_dev *bus, int pbus_addr, int pbus_reg) ++{ ++ unsigned long pbus_data; ++ unsigned int pbus_data_low, pbus_data_high; ++ ++ airoha_cl22_write(bus, pbus_addr, 0x1F, (pbus_reg >> 6)); ++ pbus_data_low = airoha_cl22_read(bus, pbus_addr, ((pbus_reg >> 2) & 0xf)); ++ pbus_data_high = airoha_cl22_read(bus, pbus_addr, 0x10); ++ pbus_data = (pbus_data_high << 16) + pbus_data_low; ++ return pbus_data; ++} ++ ++/* Airoha Token Ring Write function */ ++static int airoha_tr_reg_write(struct phy_device *phydev, unsigned long tr_address, unsigned long tr_data) ++{ ++ int ret; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x52b5); /* page select */ ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (int)(tr_data & 0xffff)); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (int)(tr_data >> 16)); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (int)(tr_address | TrReg_WR)); ++ AIR_RTN_ERR(ret); ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, 0x0); /* page resetore */ ++ AIR_RTN_ERR(ret); ++ return ret; ++} ++ ++int airoha_phy_process(void) ++{ ++ int ret = 0, pbus_addr = EN8801S_PBUS_PHY_ID; ++ unsigned long pbus_data; ++ struct mii_dev *mbus; ++ ++ mbus = s_phydev->bus; ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19e0); ++ pbus_data |= BIT(0); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, pbus_data); ++ if(ret) ++ printf("error: airoha_pbus_write fail ret: %d\n", ret); ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x19e0); ++ pbus_data &= ~BIT(0); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x19e0, pbus_data); ++ if(ret) ++ printf("error: airoha_pbus_write fail ret: %d\n", ret); ++ ++ if(ret) ++ printf("error: FCM regs reset fail, ret: %d\n", ret); ++ else ++ debug("FCM regs reset successful\n"); ++ return ret; ++} ++ ++#ifdef AIR_LED_SUPPORT ++static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, int polar, ++ u16 on_evt, u16 blk_evt) ++{ ++ int ret = 0; ++ ++ if (AIR_ACTIVE_HIGH == polar) { ++ on_evt |= LED_ON_POL; ++ } else { ++ on_evt &= ~LED_ON_POL; ++ } ++ ret = airoha_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt | LED_ON_EN); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt); ++ AIR_RTN_ERR(ret); ++ return 0; ++} ++ ++static int airoha_led_set_mode(struct phy_device *phydev, u8 mode) ++{ ++ u16 cl45_data; ++ int err = 0; ++ ++ cl45_data = airoha_cl45_read(phydev, 0x1f, LED_BCR); ++ switch (mode) { ++ case AIR_LED_MODE_DISABLE: ++ cl45_data &= ~LED_BCR_EXT_CTRL; ++ cl45_data &= ~LED_BCR_MODE_MASK; ++ cl45_data |= LED_BCR_MODE_DISABLE; ++ break; ++ case AIR_LED_MODE_USER_DEFINE: ++ cl45_data |= LED_BCR_EXT_CTRL; ++ cl45_data |= LED_BCR_CLK_EN; ++ break; ++ default: ++ printf("LED mode%d is not supported!\n", mode); ++ return -EINVAL; ++ } ++ err = airoha_cl45_write(phydev, 0x1f, LED_BCR, cl45_data); ++ AIR_RTN_ERR(err); ++ return 0; ++} ++ ++static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state) ++{ ++ u16 cl45_data; ++ int err; ++ ++ cl45_data = airoha_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity)); ++ if (LED_ENABLE == state) { ++ cl45_data |= LED_ON_EN; ++ } else { ++ cl45_data &= ~LED_ON_EN; ++ } ++ ++ err = airoha_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data); ++ AIR_RTN_ERR(err); ++ return 0; ++} ++ ++static int en8801s_led_init(struct phy_device *phydev) ++{ ++ ++ unsigned long led_gpio = 0, reg_value = 0; ++ int ret = 0, led_id; ++ struct mii_dev *mbus = phydev->bus; ++ int gpio_led_rg[3] = {0x1870, 0x1874, 0x1878}; ++ u16 cl45_data = led_dur; ++ ++ ret = airoha_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data); ++ AIR_RTN_ERR(ret); ++ cl45_data >>= 1; ++ ret = airoha_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data); ++ AIR_RTN_ERR(ret); ++ ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE); ++ if (ret != 0) { ++ printf("LED fail to set mode, ret %d !\n", ret); ++ return ret; ++ } ++ for(led_id = 0; led_id < EN8801S_LED_COUNT; led_id++) { ++ reg_value = 0; ++ ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en); ++ if (ret != 0) { ++ printf("LED fail to set state, ret %d !\n", ret); ++ return ret; ++ } ++ if (LED_ENABLE == led_cfg[led_id].en) { ++ if ( (led_cfg[led_id].gpio < 0) || led_cfg[led_id].gpio > 9) { ++ printf("GPIO%d is out of range!! GPIO number is 0~9.\n", led_cfg[led_id].gpio); ++ return -EIO; ++ } ++ led_gpio |= BIT(led_cfg[led_id].gpio); ++ reg_value = airoha_pbus_read(mbus, EN8801S_PBUS_PHY_ID, gpio_led_rg[led_cfg[led_id].gpio / 4]); ++ LED_SET_GPIO_SEL(led_cfg[led_id].gpio, led_id, reg_value); ++ debug("[Airoha] gpio%d, reg_value 0x%lx\n", led_cfg[led_id].gpio, reg_value); ++ ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, gpio_led_rg[led_cfg[led_id].gpio / 4], reg_value); ++ AIR_RTN_ERR(ret); ++ ret = airoha_led_set_usr_def(phydev, led_id, led_cfg[led_id].pol, led_cfg[led_id].on_cfg, led_cfg[led_id].blk_cfg); ++ if (ret != 0) { ++ printf("LED fail to set usr def, ret %d !\n", ret); ++ return ret; ++ } ++ } ++ } ++ reg_value = (airoha_pbus_read(mbus, EN8801S_PBUS_PHY_ID, 0x1880) & ~led_gpio); ++ ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, 0x1880, reg_value); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, EN8801S_PBUS_PHY_ID, 0x186c, led_gpio); ++ AIR_RTN_ERR(ret); ++ ++ printf("LED initialize OK !\n"); ++ return 0; ++} ++#endif /* AIR_LED_SUPPORT */ ++ ++static int en8801s_config(struct phy_device *phydev) ++{ ++ int reg_value = 0, ret = 0; ++ struct mii_dev *mbus = phydev->bus; ++ int retry, pbus_addr = EN8801S_PBUS_DEFAULT_ID; ++ int phy_addr = EN8801S_MDIO_PHY_ID; ++ unsigned long pbus_data = 0; ++ gephy_all_REG_LpiReg1Ch GPHY_RG_LPI_1C; ++ gephy_all_REG_dev1Eh_reg324h GPHY_RG_1E_324; ++ gephy_all_REG_dev1Eh_reg012h GPHY_RG_1E_012; ++ gephy_all_REG_dev1Eh_reg017h GPHY_RG_1E_017; ++ ++ s_phydev = phydev; ++ retry = MAX_OUI_CHECK; ++ while (1) { ++ /* PHY OUI */ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_ETHER_PHY_OUI); ++ if (EN8801S_PBUS_OUI == pbus_data) { ++ printf("PBUS addr 0x%x: Start initialized.\n", pbus_addr); ++ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_BUCK_CTL, 0x03); ++ AIR_RTN_ERR(ret); ++ break; ++ } else ++ pbus_addr = EN8801S_PBUS_PHY_ID; ++ ++ if (0 == --retry) { ++ printf("EN8801S Probe fail !\n"); ++ return 0; ++ } ++ } ++ ++ /* SMI ADDR */ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_SMI_ADDR); ++ pbus_data = (pbus_data & 0xffff0000) | (unsigned long)(pbus_addr << 8) | (unsigned long)(EN8801S_MDIO_DEFAULT_ID); ++ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_SMI_ADDR, pbus_data); ++ AIR_RTN_ERR(ret); ++ mdelay(10); ++ ++ pbus_data = (airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_LTR_CTL) & (~0x3)) | BIT(2) ; ++ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_LTR_CTL, pbus_data); ++ AIR_RTN_ERR(ret); ++ mdelay(500); ++ pbus_data = (pbus_data & ~BIT(2)) | EN8801S_RX_POLARITY_NORMAL | EN8801S_TX_POLARITY_NORMAL; ++ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_LTR_CTL, pbus_data); ++ AIR_RTN_ERR(ret); ++ mdelay(500); ++ /* SMI ADDR */ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, EN8801S_RG_SMI_ADDR); ++ pbus_data = (pbus_data & 0xffff0000) | (unsigned long)(EN8801S_PBUS_PHY_ID << 8) | (unsigned long)(EN8801S_MDIO_PHY_ID); ++ ret = airoha_pbus_write(mbus, pbus_addr, EN8801S_RG_SMI_ADDR, pbus_data); ++ pbus_addr = EN8801S_PBUS_PHY_ID; ++ AIR_RTN_ERR(ret); ++ mdelay(10); ++ ++ /* Optimze 10M IoT */ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1690); ++ pbus_data |= (1 << 31); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1690, pbus_data); ++ AIR_RTN_ERR(ret); ++ /* set SGMII Base Page */ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); ++ AIR_RTN_ERR(ret); ++ /* Set FCM control */ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007); ++ AIR_RTN_ERR(ret); ++ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x142c, 0x05050505); ++ AIR_RTN_ERR(ret); ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1440); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1440, pbus_data & ~BIT(11)); ++ AIR_RTN_ERR(ret); ++ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1408); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1408, pbus_data | BIT(5)); ++ AIR_RTN_ERR(ret); ++ ++ /* Set GPHY Perfomance*/ ++ /* Token Ring */ ++ ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_15h, 0x0055A0); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_R1000DEC_17h, 0x07FF3F); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_00h, 0x00001E); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_01h, 0x6FB90A); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_17h, 0x060671); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_PMA_18h, 0x0E2F00); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_TR_26h, 0x444444); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_03h, 0x000000); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_06h, 0x2EBAEF); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_08h, 0x00000B); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Ch, 0x00504D); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Dh, 0x02314F); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_0Fh, 0x003028); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_10h, 0x005010); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_11h, 0x040001); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_13h, 0x018670); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_14h, 0x00024A); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Bh, 0x000072); ++ AIR_RTN_ERR(ret); ++ ret = airoha_tr_reg_write(phydev, RgAddr_DSPF_1Ch, 0x003210); ++ AIR_RTN_ERR(ret); ++ /* CL22 & CL45 */ ++ ret = airoha_cl22_write(mbus, phy_addr, 0x1f, 0x03); ++ AIR_RTN_ERR(ret); ++ GPHY_RG_LPI_1C.DATA = airoha_cl22_read(mbus, phy_addr, RgAddr_LPI_1Ch); ++ if (GPHY_RG_LPI_1C.DATA < 0) ++ return -EIO; ++ GPHY_RG_LPI_1C.DataBitField.smi_deton_th = 0x0C; ++ ret = airoha_cl22_write(mbus, phy_addr, RgAddr_LPI_1Ch, GPHY_RG_LPI_1C.DATA); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl22_write(mbus, phy_addr, RgAddr_LPI_1Ch, 0xC92); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl22_write(mbus, phy_addr, RgAddr_AUXILIARY_1Dh, 0x1); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl22_write(mbus, phy_addr, 0x1f, 0x0); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x120, 0x8014); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x122, 0xffff); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x123, 0xffff); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x144, 0x0200); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x14A, 0xEE20); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x189, 0x0110); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x19B, 0x0111); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x234, 0x0181); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x238, 0x0120); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x239, 0x0117); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x268, 0x07F4); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x2D1, 0x0733); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x323, 0x0011); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x324, 0x013F); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x326, 0x0037); ++ AIR_RTN_ERR(ret); ++ ++ reg_value = airoha_cl45_read(phydev, 0x1E, 0x324); ++ if (reg_value < 0) ++ return -EIO; ++ GPHY_RG_1E_324.DATA = (int)reg_value; ++ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = 0; ++ ret = airoha_cl45_write(phydev, 0x1E, 0x324, GPHY_RG_1E_324.DATA); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x19E, 0xC2); ++ AIR_RTN_ERR(ret); ++ ret = airoha_cl45_write(phydev, 0x1E, 0x013, 0x0); ++ AIR_RTN_ERR(ret); ++ ++ /* EFUSE */ ++ airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40000040); ++ retry = MAX_RETRY; ++ while (0 != retry) { ++ mdelay(1); ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C08); ++ if ((pbus_data & (1 << 30)) == 0) { ++ break; ++ } ++ retry--; ++ } ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C38); /* RAW#2 */ ++ reg_value = airoha_cl45_read(phydev, 0x1E, 0x12); ++ if (reg_value < 0) ++ return -EIO; ++ GPHY_RG_1E_012.DATA = reg_value; ++ GPHY_RG_1E_012.DataBitField.da_tx_i2mpb_a_tbt = pbus_data & 0x03f; ++ ret = airoha_cl45_write(phydev, 0x1E, 0x12, GPHY_RG_1E_012.DATA); ++ AIR_RTN_ERR(ret); ++ reg_value = airoha_cl45_read(phydev, 0x1E, 0x17); ++ if (reg_value < 0) ++ return -EIO; ++ GPHY_RG_1E_017.DataBitField.da_tx_i2mpb_b_tbt = (reg_value >> 8) & 0x03f; ++ ret = airoha_cl45_write(phydev, 0x1E, 0x17, GPHY_RG_1E_017.DATA); ++ AIR_RTN_ERR(ret); ++ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1C08, 0x40400040); ++ AIR_RTN_ERR(ret); ++ retry = MAX_RETRY; ++ while (0 != retry) { ++ mdelay(1); ++ reg_value = airoha_pbus_read(mbus, pbus_addr, 0x1C08); ++ if ((reg_value & (1 << 30)) == 0) { ++ break; ++ } ++ retry--; ++ } ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1C30); /* RAW#16 */ ++ GPHY_RG_1E_324.DataBitField.smi_det_deglitch_off = (pbus_data >> 12) & 0x01; ++ ret = airoha_cl45_write(phydev, 0x1E, 0x324, GPHY_RG_1E_324.DATA); ++ AIR_RTN_ERR(ret); ++#ifdef AIR_LED_SUPPORT ++ ret = en8801s_led_init(phydev); ++ if (ret != 0){ ++ printf("en8801s_led_init fail (ret:%d) !\n", ret); ++ } ++#endif ++ printf("EN8801S initialize OK ! (%s)\n", EN8801S_DRIVER_VERSION); ++ return 0; ++} ++ ++int en8801s_read_status(struct phy_device *phydev) ++{ ++ int ret, pbus_addr = EN8801S_PBUS_PHY_ID; ++ struct mii_dev *mbus; ++ unsigned long pbus_data; ++ ++ mbus = phydev->bus; ++ if (SPEED_10 == phydev->speed) { ++ /* set the bit for Optimze 10M IoT */ ++ debug("[Airoha] SPEED_10 0x1694\n"); ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1694); ++ pbus_data |= (1 << 31); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, pbus_data); ++ AIR_RTN_ERR(ret); ++ } else { ++ debug("[Airoha] SPEED_1000/100 0x1694\n"); ++ /* clear the bit for other speeds */ ++ pbus_data = airoha_pbus_read(mbus, pbus_addr, 0x1694); ++ pbus_data &= ~(1 << 31); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1694, pbus_data); ++ AIR_RTN_ERR(ret); ++ } ++ ++ airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); ++ if(SPEED_1000 == phydev->speed) { ++ debug("[Airoha] SPEED_1000\n"); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD801); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140); ++ AIR_RTN_ERR(ret); ++ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0003); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c000c00); ++ AIR_RTN_ERR(ret); ++ mdelay(2); /* delay 2 ms */ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x004b); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007); ++ AIR_RTN_ERR(ret); ++ } ++ else if (SPEED_100 == phydev->speed) { ++ debug("[Airoha] SPEED_100\n"); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD401); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x0007); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c11); ++ AIR_RTN_ERR(ret); ++ mdelay(2); /* delay 2 ms */ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x0027); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007); ++ AIR_RTN_ERR(ret); ++ } ++ else { ++ debug("[Airoha] SPEED_10\n"); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x10, 0xD001); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0, 0x9140); ++ AIR_RTN_ERR(ret); ++ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0A14, 0x000b); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x0600, 0x0c11); ++ AIR_RTN_ERR(ret); ++ mdelay(2); /* delay 2 ms */ ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x1404, 0x0047); ++ AIR_RTN_ERR(ret); ++ ret = airoha_pbus_write(mbus, pbus_addr, 0x140c, 0x0007); ++ AIR_RTN_ERR(ret); ++ } ++ return 0; ++} ++ ++static int en8801s_startup(struct phy_device *phydev) ++{ ++ int ret; ++ ++ ret = genphy_update_link(phydev); ++ if (ret) ++ return ret; ++ ret = genphy_parse_link(phydev); ++ if (ret) ++ return ret; ++ return en8801s_read_status(phydev); ++} ++#if AIR_UBOOT_REVISION > 0x202303 ++U_BOOT_PHY_DRIVER(en8801s) = { ++ .name = "Airoha EN8801S", ++ .uid = EN8801S_PHY_ID, ++ .mask = 0x0ffffff0, ++ .features = PHY_GBIT_FEATURES, ++ .config = &en8801s_config, ++ .startup = &en8801s_startup, ++ .shutdown = &genphy_shutdown, ++}; ++#else ++static struct phy_driver AIR_EN8801S_driver = { ++ .name = "Airoha EN8801S", ++ .uid = EN8801S_PHY_ID, ++ .mask = 0x0ffffff0, ++ .features = PHY_GBIT_FEATURES, ++ .config = &en8801s_config, ++ .startup = &en8801s_startup, ++ .shutdown = &genphy_shutdown, ++}; ++ ++int phy_air_en8801s_init(void) ++{ ++ phy_register(&AIR_EN8801S_driver); ++ return 0; ++} ++#endif +--- /dev/null ++++ b/drivers/net/phy/air_en8801s.h +@@ -0,0 +1,267 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/************************************************* ++ * FILE NAME: air_en8801s.h ++ * PURPOSE: ++ * EN8801S PHY Driver for Uboot ++ * NOTES: ++ * ++ * Copyright (C) 2023 Airoha Technology Corp. ++ *************************************************/ ++ ++#ifndef __EN8801S_H ++#define __EN8801S_H ++ ++/************************************************************************ ++* D E F I N E S ++************************************************************************/ ++#define AIR_UBOOT_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 20) | \ ++ (((U_BOOT_VERSION_NUM / 100) % 10) << 16) | \ ++ (((U_BOOT_VERSION_NUM / 10) % 10) << 12) | \ ++ ((U_BOOT_VERSION_NUM % 10) << 8) | \ ++ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 4) | \ ++ ((U_BOOT_VERSION_NUM_PATCH % 10) << 0)) ++ ++#define EN8801S_MDIO_DEFAULT_ID 0x1d ++#define EN8801S_PBUS_DEFAULT_ID (EN8801S_MDIO_DEFAULT_ID + 1) ++#define EN8801S_MDIO_PHY_ID 0x18 /* Range PHY_ADDRESS_RANGE .. 0x1e */ ++#define EN8801S_PBUS_PHY_ID (EN8801S_MDIO_PHY_ID + 1) ++#define EN8801S_DRIVER_VERSION "v1.1.3" ++ ++#define EN8801S_RG_ETHER_PHY_OUI 0x19a4 ++#define EN8801S_RG_SMI_ADDR 0x19a8 ++#define EN8801S_PBUS_OUI 0x17a5 ++#define EN8801S_RG_BUCK_CTL 0x1a20 ++#define EN8801S_RG_LTR_CTL 0x0cf8 ++ ++#define EN8801S_PHY_ID1 0x03a2 ++#define EN8801S_PHY_ID2 0x9461 ++#define EN8801S_PHY_ID (unsigned long)((EN8801S_PHY_ID1 << 16) | EN8801S_PHY_ID2) ++ ++/* ++SFP Sample for verification ++Tx Reverse, Rx Reverse ++*/ ++#define EN8801S_TX_POLARITY_NORMAL 0x0 ++#define EN8801S_TX_POLARITY_REVERSE 0x1 ++ ++#define EN8801S_RX_POLARITY_NORMAL (0x1 << 1) ++#define EN8801S_RX_POLARITY_REVERSE (0x0 << 1) ++ ++#ifndef BIT ++#define BIT(nr) (1UL << (nr)) ++#endif ++ ++#define MAX_RETRY 5 ++#define MAX_OUI_CHECK 2 ++ ++/* CL45 MDIO control */ ++#define MII_MMD_ACC_CTL_REG 0x0d ++#define MII_MMD_ADDR_DATA_REG 0x0e ++#define MMD_OP_MODE_DATA BIT(14) ++ ++#define MAX_TRG_COUNTER 5 ++ ++/* TokenRing Reg Access */ ++#define TrReg_PKT_XMT_STA 0x8000 ++#define TrReg_WR 0x8000 ++#define TrReg_RD 0xA000 ++ ++#define RgAddr_LPI_1Ch 0x1c ++#define RgAddr_AUXILIARY_1Dh 0x1d ++#define RgAddr_PMA_00h 0x0f80 ++#define RgAddr_PMA_01h 0x0f82 ++#define RgAddr_PMA_17h 0x0fae ++#define RgAddr_PMA_18h 0x0fb0 ++#define RgAddr_DSPF_03h 0x1686 ++#define RgAddr_DSPF_06h 0x168c ++#define RgAddr_DSPF_08h 0x1690 ++#define RgAddr_DSPF_0Ch 0x1698 ++#define RgAddr_DSPF_0Dh 0x169a ++#define RgAddr_DSPF_0Fh 0x169e ++#define RgAddr_DSPF_10h 0x16a0 ++#define RgAddr_DSPF_11h 0x16a2 ++#define RgAddr_DSPF_13h 0x16a6 ++#define RgAddr_DSPF_14h 0x16a8 ++#define RgAddr_DSPF_1Bh 0x16b6 ++#define RgAddr_DSPF_1Ch 0x16b8 ++#define RgAddr_TR_26h 0x0ecc ++#define RgAddr_R1000DEC_15h 0x03aa ++#define RgAddr_R1000DEC_17h 0x03ae ++ ++/* ++The following led_cfg example is for reference only. ++LED5 1000M/LINK/ACT (GPIO5) <-> BASE_T_LED0, ++LED6 10/100M/LINK/ACT(GPIO9) <-> BASE_T_LED1, ++LED4 100M/LINK/ACT (GPIO8) <-> BASE_T_LED2, ++*/ ++/* User-defined.B */ ++#define BASE_T_LED0_ON_CFG (LED_ON_EVT_LINK_1000M) ++#define BASE_T_LED0_BLK_CFG (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT) ++#define BASE_T_LED1_ON_CFG (LED_ON_EVT_LINK_100M | LED_ON_EVT_LINK_10M) ++#define BASE_T_LED1_BLK_CFG (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT | \ ++ LED_BLK_EVT_10M_TX_ACT | LED_BLK_EVT_10M_RX_ACT ) ++#define BASE_T_LED2_ON_CFG (LED_ON_EVT_LINK_100M) ++#define BASE_T_LED2_BLK_CFG (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT) ++#define BASE_T_LED3_ON_CFG (0x0) ++#define BASE_T_LED3_BLK_CFG (0x0) ++/* User-defined.E */ ++ ++#define EN8801S_LED_COUNT 4 ++ ++#define LED_BCR (0x021) ++#define LED_BCR_EXT_CTRL (1 << 15) ++#define LED_BCR_CLK_EN (1 << 3) ++#define LED_BCR_TIME_TEST (1 << 2) ++#define LED_BCR_MODE_MASK (3) ++#define LED_BCR_MODE_DISABLE (0) ++#define LED_ON_CTRL(i) (0x024 + ((i)*2)) ++#define LED_ON_EN (1 << 15) ++#define LED_ON_POL (1 << 14) ++#define LED_ON_EVT_MASK (0x7f) ++/* LED ON Event Option.B */ ++#define LED_ON_EVT_FORCE (1 << 6) ++#define LED_ON_EVT_LINK_DOWN (1 << 3) ++#define LED_ON_EVT_LINK_10M (1 << 2) ++#define LED_ON_EVT_LINK_100M (1 << 1) ++#define LED_ON_EVT_LINK_1000M (1 << 0) ++/* LED ON Event Option.E */ ++#define LED_BLK_CTRL(i) (0x025 + ((i)*2)) ++#define LED_BLK_EVT_MASK (0x3ff) ++/* LED Blinking Event Option.B*/ ++#define LED_BLK_EVT_FORCE (1 << 9) ++#define LED_BLK_EVT_10M_RX_ACT (1 << 5) ++#define LED_BLK_EVT_10M_TX_ACT (1 << 4) ++#define LED_BLK_EVT_100M_RX_ACT (1 << 3) ++#define LED_BLK_EVT_100M_TX_ACT (1 << 2) ++#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) ++#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) ++/* LED Blinking Event Option.E*/ ++#define LED_ON_DUR (0x022) ++#define LED_ON_DUR_MASK (0xffff) ++#define LED_BLK_DUR (0x023) ++#define LED_BLK_DUR_MASK (0xffff) ++ ++#define LED_ENABLE 1 ++#define LED_DISABLE 0 ++ ++#define UNIT_LED_BLINK_DURATION 1024 ++ ++#define AIR_RTN_ON_ERR(cond, err) \ ++ do { if ((cond)) return (err); } while(0) ++ ++#define AIR_RTN_ERR(err) AIR_RTN_ON_ERR(err < 0, err) ++ ++#define LED_SET_EVT(reg, cod, result, bit) do \ ++ { \ ++ if(reg & cod) { \ ++ result |= bit; \ ++ } \ ++ } while(0) ++ ++#define LED_SET_GPIO_SEL(gpio, led, val) do \ ++ { \ ++ val |= (led << (8 * (gpio % 4))); \ ++ } while(0) ++ ++/* DATA TYPE DECLARATIONS ++ */ ++typedef struct ++{ ++ int DATA_Lo; ++ int DATA_Hi; ++}TR_DATA_T; ++ ++typedef union ++{ ++ struct ++ { ++ /* b[15:00] */ ++ int smi_deton_wt : 3; ++ int smi_det_mdi_inv : 1; ++ int smi_detoff_wt : 3; ++ int smi_sigdet_debouncing_en : 1; ++ int smi_deton_th : 6; ++ int rsv_14 : 2; ++ } DataBitField; ++ int DATA; ++} gephy_all_REG_LpiReg1Ch, *Pgephy_all_REG_LpiReg1Ch; ++ ++typedef union ++{ ++ struct ++ { ++ /* b[15:00] */ ++ int rg_smi_detcnt_max : 6; ++ int rsv_6 : 2; ++ int rg_smi_det_max_en : 1; ++ int smi_det_deglitch_off : 1; ++ int rsv_10 : 6; ++ } DataBitField; ++ int DATA; ++} gephy_all_REG_dev1Eh_reg324h, *Pgephy_all_REG_dev1Eh_reg324h; ++ ++typedef union ++{ ++ struct ++ { ++ /* b[15:00] */ ++ int da_tx_i2mpb_a_tbt : 6; ++ int rsv_6 : 4; ++ int da_tx_i2mpb_a_gbe : 6; ++ } DataBitField; ++ int DATA; ++} gephy_all_REG_dev1Eh_reg012h, *Pgephy_all_REG_dev1Eh_reg012h; ++ ++typedef union ++{ ++ struct ++ { ++ /* b[15:00] */ ++ int da_tx_i2mpb_b_tbt : 6; ++ int rsv_6 : 2; ++ int da_tx_i2mpb_b_gbe : 6; ++ int rsv_14 : 2; ++ } DataBitField; ++ int DATA; ++} gephy_all_REG_dev1Eh_reg017h, *Pgephy_all_REG_dev1Eh_reg017h; ++ ++typedef struct AIR_BASE_T_LED_CFG_S ++{ ++ u16 en; ++ u16 gpio; ++ u16 pol; ++ u16 on_cfg; ++ u16 blk_cfg; ++}AIR_BASE_T_LED_CFG_T; ++ ++typedef enum ++{ ++ AIR_LED_BLK_DUR_32M, ++ AIR_LED_BLK_DUR_64M, ++ AIR_LED_BLK_DUR_128M, ++ AIR_LED_BLK_DUR_256M, ++ AIR_LED_BLK_DUR_512M, ++ AIR_LED_BLK_DUR_1024M, ++ AIR_LED_BLK_DUR_LAST ++} AIR_LED_BLK_DUT_T; ++ ++typedef enum ++{ ++ AIR_ACTIVE_LOW, ++ AIR_ACTIVE_HIGH, ++} AIR_LED_POLARITY; ++typedef enum ++{ ++ AIR_LED_MODE_DISABLE, ++ AIR_LED_MODE_USER_DEFINE, ++ AIR_LED_MODE_LAST ++} AIR_LED_MODE_T; ++ ++/************************************************************************ ++* F U N C T I O N P R O T O T Y P E S ++************************************************************************/ ++ ++unsigned long airoha_pbus_read(struct mii_dev *bus, int pbus_addr, int pbus_reg); ++int airoha_pbus_write(struct mii_dev *bus, int pbus_addr, int pbus_reg, unsigned long pbus_data); ++int airoha_phy_process(void); ++#endif /* __EN8801S_H */ +--- /dev/null ++++ b/drivers/net/phy/air_en8811h.c +@@ -0,0 +1,725 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/************************************************* ++ * FILE NAME: air_en8811h.c ++ * PURPOSE: ++ * EN8811H PHY Driver for Uboot ++ * NOTES: ++ * ++ * Copyright (C) 2023 Airoha Technology Corp. ++ *************************************************/ ++ ++/* INCLUDE FILE DECLARATIONS ++*/ ++#include <common.h> ++#include <eth_phy.h> ++#include <phy.h> ++#include <errno.h> ++#include <malloc.h> ++#include <version.h> ++#include "air_en8811h.h" ++ ++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI ++#include <ubi_uboot.h> ++#endif ++ ++#ifdef CONFIG_PHY_AIROHA_FW_IN_MMC ++#include <mmc.h> ++#endif ++ ++#ifdef CONFIG_PHY_AIROHA_FW_IN_MTD ++#include <mtd.h> ++#endif ++ ++#if AIR_UBOOT_REVISION > 0x202004 ++#include <linux/delay.h> ++#endif ++ ++/************************** ++ * GPIO5 <-> BASE_T_LED0, ++ * GPIO4 <-> BASE_T_LED1, ++ * GPIO3 <-> BASE_T_LED2, ++ **************************/ ++/* User-defined.B */ ++#define AIR_LED_SUPPORT ++#ifdef AIR_LED_SUPPORT ++static const struct air_base_t_led_cfg_s led_cfg[3] = { ++/********************************************************************* ++ *Enable, GPIO, LED Polarity, LED ON, LED Blink ++**********************************************************************/ ++ {1, AIR_LED0_GPIO5, AIR_ACTIVE_HIGH, AIR_LED0_ON, AIR_LED0_BLK}, ++ {1, AIR_LED1_GPIO4, AIR_ACTIVE_HIGH, AIR_LED1_ON, AIR_LED1_BLK}, ++ {1, AIR_LED2_GPIO3, AIR_ACTIVE_HIGH, AIR_LED2_ON, AIR_LED2_BLK}, ++}; ++static const u16 led_dur = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M; ++#endif ++/* User-defined.E */ ++/************************************************************* ++ * F U N C T I O N S ++ **************************************************************/ ++/* Airoha MII read function */ ++static int air_mii_cl22_read(struct mii_dev *bus, int phy_addr, int phy_register) ++{ ++ int read_data = bus->read(bus, phy_addr, MDIO_DEVAD_NONE, phy_register); ++ ++ if (read_data < 0) ++ return -EIO; ++ return read_data; ++} ++ ++/* Airoha MII write function */ ++static int air_mii_cl22_write(struct mii_dev *bus, int phy_addr, int phy_register, int write_data) ++{ ++ int ret = 0; ++ ++ ret = bus->write(bus, phy_addr, MDIO_DEVAD_NONE, phy_register, write_data); ++ if (ret < 0) { ++ printf("bus->write, ret: %d\n", ret); ++ return ret; ++ } ++ return ret; ++} ++ ++static int air_mii_cl45_read(struct phy_device *phydev, int devad, u16 reg) ++{ ++ int ret = 0; ++ int data; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return INVALID_DATA; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return INVALID_DATA; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return INVALID_DATA; ++ } ++ data = phy_read(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG); ++ return data; ++} ++ ++static int air_mii_cl45_write(struct phy_device *phydev, int devad, u16 reg, u16 write_data) ++{ ++ int ret = 0; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, devad); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, reg); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ACC_CTL_REG, MMD_OP_MODE_DATA | devad); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_MMD_ADDR_DATA_REG, write_data); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++/* Use default PBUS_PHY_ID */ ++/* EN8811H PBUS write function */ ++static int air_pbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned long pbus_data) ++{ ++ int ret = 0; ++ struct mii_dev *mbus = phydev->bus; ++ ++ ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), 0x1F, (unsigned int)(pbus_address >> 6)); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), (unsigned int)((pbus_address >> 2) & 0xf), (unsigned int)(pbus_data & 0xFFFF)); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl22_write(mbus, ((phydev->addr) + 8), 0x10, (unsigned int)(pbus_data >> 16)); ++ if (ret < 0) ++ return ret; ++ return 0; ++} ++ ++/* EN8811H BUCK write function */ ++static int air_buckpbus_reg_write(struct phy_device *phydev, unsigned long pbus_address, unsigned int pbus_data) ++{ ++ int ret = 0; ++ ++ /* page 4 */ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (unsigned int)((pbus_address >> 16) & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (unsigned int)(pbus_address & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x13, (unsigned int)((pbus_data >> 16) & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, (unsigned int)(pbus_data & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++/* EN8811H BUCK read function */ ++static unsigned int air_buckpbus_reg_read(struct phy_device *phydev, unsigned long pbus_address) ++{ ++ unsigned int pbus_data = 0, pbus_data_low, pbus_data_high; ++ int ret = 0; ++ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4); /* page 4 */ ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return PBUS_INVALID_DATA; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return PBUS_INVALID_DATA; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x15, (unsigned int)((pbus_address >> 16) & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return PBUS_INVALID_DATA; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x16, (unsigned int)(pbus_address & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return PBUS_INVALID_DATA; ++ } ++ ++ pbus_data_high = phy_read(phydev, MDIO_DEVAD_NONE, 0x17); ++ pbus_data_low = phy_read(phydev, MDIO_DEVAD_NONE, 0x18); ++ pbus_data = (pbus_data_high << 16) + pbus_data_low; ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)0); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ return pbus_data; ++} ++ ++static int MDIOWriteBuf(struct phy_device *phydev, unsigned long address, unsigned long array_size, const unsigned char *buffer) ++{ ++ unsigned int write_data, offset ; ++ int ret = 0; ++ ++ /* page 4 */ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)4); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ /* address increment*/ ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x10, (unsigned int)0x8000); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x11, (unsigned int)((address >> 16) & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x12, (unsigned int)(address & 0xffff)); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ ++ for (offset = 0; offset < array_size; offset += 4) { ++ write_data = (buffer[offset + 3] << 8) | buffer[offset + 2]; ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x13, write_data); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ write_data = (buffer[offset + 1] << 8) | buffer[offset]; ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x14, write_data); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ } ++ ret = phy_write(phydev, MDIO_DEVAD_NONE, 0x1F, (unsigned int)0); ++ if (ret < 0) { ++ printf("phy_write, ret: %d\n", ret); ++ return ret; ++ } ++ return 0; ++} ++ ++#ifdef AIR_LED_SUPPORT ++static int airoha_led_set_usr_def(struct phy_device *phydev, u8 entity, int polar, ++ u16 on_evt, u16 blk_evt) ++{ ++ int ret = 0; ++ ++ if (AIR_ACTIVE_HIGH == polar) ++ on_evt |= LED_ON_POL; ++ else ++ on_evt &= ~LED_ON_POL; ++ ++ ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), on_evt | LED_ON_EN); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_CTRL(entity), blk_evt); ++ if (ret < 0) ++ return ret; ++ return 0; ++} ++ ++static int airoha_led_set_mode(struct phy_device *phydev, u8 mode) ++{ ++ u16 cl45_data; ++ int err = 0; ++ ++ cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_BCR); ++ switch (mode) { ++ case AIR_LED_MODE_DISABLE: ++ cl45_data &= ~LED_BCR_EXT_CTRL; ++ cl45_data &= ~LED_BCR_MODE_MASK; ++ cl45_data |= LED_BCR_MODE_DISABLE; ++ break; ++ case AIR_LED_MODE_USER_DEFINE: ++ cl45_data |= LED_BCR_EXT_CTRL; ++ cl45_data |= LED_BCR_CLK_EN; ++ break; ++ default: ++ printf("LED mode%d is not supported!\n", mode); ++ return -EINVAL; ++ } ++ err = air_mii_cl45_write(phydev, 0x1f, LED_BCR, cl45_data); ++ if (err < 0) ++ return err; ++ return 0; ++} ++ ++static int airoha_led_set_state(struct phy_device *phydev, u8 entity, u8 state) ++{ ++ u16 cl45_data; ++ int err; ++ ++ cl45_data = air_mii_cl45_read(phydev, 0x1f, LED_ON_CTRL(entity)); ++ if (LED_ENABLE == state) ++ cl45_data |= LED_ON_EN; ++ else ++ cl45_data &= ~LED_ON_EN; ++ ++ err = air_mii_cl45_write(phydev, 0x1f, LED_ON_CTRL(entity), cl45_data); ++ if (err < 0) ++ return err; ++ return 0; ++} ++ ++static int en8811h_led_init(struct phy_device *phydev) ++{ ++ unsigned int led_gpio = 0, reg_value = 0; ++ u16 cl45_data = led_dur; ++ int ret, led_id; ++ ++ cl45_data = UNIT_LED_BLINK_DURATION << AIR_LED_BLK_DUR_64M; ++ ret = air_mii_cl45_write(phydev, 0x1f, LED_BLK_DUR, cl45_data); ++ if (ret < 0) ++ return ret; ++ cl45_data >>= 1; ++ ret = air_mii_cl45_write(phydev, 0x1f, LED_ON_DUR, cl45_data); ++ if (ret < 0) ++ return ret; ++ ++ ret = airoha_led_set_mode(phydev, AIR_LED_MODE_USER_DEFINE); ++ if (ret != 0) { ++ printf("LED fail to set mode, ret %d !\n", ret); ++ return ret; ++ } ++ for(led_id = 0; led_id < EN8811H_LED_COUNT; led_id++) ++ { ++ /* LED0 <-> GPIO5, LED1 <-> GPIO4, LED0 <-> GPIO3 */ ++ if ( led_cfg[led_id].gpio != (led_id + (AIR_LED0_GPIO5 - (2 * led_id)))) { ++ printf("LED%d uses incorrect GPIO%d !\n", led_id, led_cfg[led_id].gpio); ++ return -EINVAL; ++ } ++ reg_value = 0; ++ if (led_cfg[led_id].en == LED_ENABLE) ++ { ++ led_gpio |= BIT(led_cfg[led_id].gpio); ++ ret = airoha_led_set_state(phydev, led_id, led_cfg[led_id].en); ++ if (ret != 0) { ++ printf("LED fail to set state, ret %d !\n", ret); ++ return ret; ++ } ++ ret = airoha_led_set_usr_def(phydev, led_id, led_cfg[led_id].pol, led_cfg[led_id].on_cfg, led_cfg[led_id].blk_cfg); ++ if (ret != 0) { ++ printf("LED fail to set default, ret %d !\n", ret); ++ return ret; ++ } ++ } ++ } ++ ret = air_buckpbus_reg_write(phydev, 0xcf8b8, led_gpio); ++ if (ret < 0) ++ return ret; ++ printf("LED initialize OK !\n"); ++ return 0; ++} ++#endif /* AIR_LED_SUPPORT */ ++ ++static char *firmware_buf; ++static int en8811h_load_firmware(struct phy_device *phydev) ++{ ++ u32 pbus_value; ++ int ret = 0; ++ ++ if (!firmware_buf) { ++ firmware_buf = malloc(EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); ++ if (!firmware_buf) { ++ printf("[Airoha] cannot allocated buffer for firmware.\n"); ++ return -ENOMEM; ++ } ++ ++#ifdef CONFIG_PHY_AIROHA_FW_IN_UBI ++ ret = ubi_volume_read("en8811h-fw", firmware_buf, EN8811H_MD32_DM_SIZE + EN8811H_MD32_DSP_SIZE); ++ if (ret) { ++ printf("[Airoha] read firmware from UBI failed.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return ret; ++ } ++#elif defined(CONFIG_PHY_AIROHA_FW_IN_MMC) ++ struct mmc *mmc = find_mmc_device(0); ++ if (!mmc) { ++ printf("[Airoha] opening MMC device failed.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return -ENODEV; ++ } ++ if (mmc_init(mmc)) { ++ printf("[Airoha] initializing MMC device failed.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return -ENODEV; ++ } ++ if (IS_SD(mmc)) { ++ printf("[Airoha] SD card is not supported.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return -EINVAL; ++ } ++ ret = mmc_set_part_conf(mmc, 1, 2, 2); ++ if (ret) { ++ printf("[Airoha] cannot access eMMC boot1 hw partition.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return ret; ++ } ++ ret = blk_dread(mmc_get_blk_desc(mmc), 0, 0x120, firmware_buf); ++ mmc_set_part_conf(mmc, 1, 1, 0); ++ if (ret != 0x120) { ++ printf("[Airoha] cannot read firmware from eMMC.\n"); ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return -EIO; ++ } ++#else ++#warning EN8811H firmware loading not implemented ++ free(firmware_buf); ++ firmware_buf = NULL; ++ return -EOPNOTSUPP; ++#endif ++ } ++ ++ ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x0); ++ if (ret < 0) ++ return ret; ++ pbus_value = air_buckpbus_reg_read(phydev, 0x800000); ++ pbus_value |= BIT(11); ++ ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value); ++ if (ret < 0) ++ return ret; ++ /* Download DM */ ++ ret = MDIOWriteBuf(phydev, 0x00000000, EN8811H_MD32_DM_SIZE, firmware_buf); ++ if (ret < 0) { ++ printf("[Airoha] MDIOWriteBuf 0x00000000 fail.\n"); ++ return ret; ++ } ++ /* Download PM */ ++ ret = MDIOWriteBuf(phydev, 0x00100000, EN8811H_MD32_DSP_SIZE, firmware_buf + EN8811H_MD32_DM_SIZE); ++ if (ret < 0) { ++ printf("[Airoha] MDIOWriteBuf 0x00100000 fail.\n"); ++ return ret; ++ } ++ pbus_value = air_buckpbus_reg_read(phydev, 0x800000); ++ pbus_value &= ~BIT(11); ++ ret = air_buckpbus_reg_write(phydev, 0x800000, pbus_value); ++ if (ret < 0) ++ return ret; ++ ret = air_buckpbus_reg_write(phydev, 0x0f0018, 0x01); ++ if (ret < 0) ++ return ret; ++ return 0; ++} ++ ++static int en8811h_config(struct phy_device *phydev) ++{ ++ int ret = 0; ++ int pid1 = 0, pid2 = 0; ++ ++ ret = air_pbus_reg_write(phydev, 0xcf928 , 0x0); ++ if (ret < 0) ++ return ret; ++ ++ pid1 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID1); ++ pid2 = phy_read(phydev, MDIO_DEVAD_NONE, MII_PHYSID2); ++ if ((EN8811H_PHY_ID1 != pid1) || (EN8811H_PHY_ID2 != pid2)) { ++ printf("EN8811H does not exist !\n"); ++ return -ENODEV; ++ } ++ ++ return 0; ++} ++ ++static int en8811h_get_autonego(struct phy_device *phydev, int *an) ++{ ++ int reg; ++ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); ++ if (reg < 0) ++ return -EINVAL; ++ if (reg & BMCR_ANENABLE) ++ *an = AUTONEG_ENABLE; ++ else ++ *an = AUTONEG_DISABLE; ++ return 0; ++} ++ ++static int en8811h_startup(struct phy_device *phydev) ++{ ++ ofnode node = phy_get_ofnode(phydev); ++ int ret = 0, lpagb = 0, lpa = 0, common_adv_gb = 0, common_adv = 0, advgb = 0, adv = 0, reg = 0, an = AUTONEG_DISABLE, bmcr = 0, reg_value; ++ int old_link = phydev->link; ++ u32 pbus_value = 0, retry; ++ ++ eth_phy_reset(phydev->dev, 1); ++ mdelay(10); ++ eth_phy_reset(phydev->dev, 0); ++ mdelay(1); ++ ++ ret = en8811h_load_firmware(phydev); ++ if (ret) { ++ printf("EN8811H load firmware fail.\n"); ++ return ret; ++ } ++ retry = MAX_RETRY; ++ do { ++ mdelay(300); ++ reg_value = air_mii_cl45_read(phydev, 0x1e, 0x8009); ++ if (EN8811H_PHY_READY == reg_value) { ++ printf("EN8811H PHY ready!\n"); ++ break; ++ } ++ retry--; ++ } while (retry); ++ if (0 == retry) { ++ printf("EN8811H PHY is not ready. (MD32 FW Status reg: 0x%x)\n", reg_value); ++ pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c); ++ printf("Check MD32 FW Version(0x3b3c) : %08x\n", pbus_value); ++ printf("EN8811H initialize fail!\n"); ++ return 0; ++ } ++ /* Mode selection*/ ++ printf("EN8811H Mode 1 !\n"); ++ ret = air_mii_cl45_write(phydev, 0x1e, 0x800c, 0x0); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl45_write(phydev, 0x1e, 0x800d, 0x0); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl45_write(phydev, 0x1e, 0x800e, 0x1101); ++ if (ret < 0) ++ return ret; ++ ret = air_mii_cl45_write(phydev, 0x1e, 0x800f, 0x0002); ++ if (ret < 0) ++ return ret; ++ ++ /* Serdes polarity */ ++ pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8); ++ pbus_value &= 0xfffffffc; ++ pbus_value |= ofnode_read_bool(node, "airoha,rx-pol-reverse") ? ++ EN8811H_RX_POLARITY_REVERSE : EN8811H_RX_POLARITY_NORMAL; ++ pbus_value |= ofnode_read_bool(node, "airoha,tx-pol-reverse") ? ++ EN8811H_TX_POLARITY_REVERSE : EN8811H_TX_POLARITY_NORMAL; ++ ret = air_buckpbus_reg_write(phydev, 0xca0f8, pbus_value); ++ if (ret < 0) ++ return ret; ++ pbus_value = air_buckpbus_reg_read(phydev, 0xca0f8); ++ printf("Tx, Rx Polarity(0xca0f8): %08x\n", pbus_value); ++ pbus_value = air_buckpbus_reg_read(phydev, 0x3b3c); ++ printf("MD32 FW Version(0x3b3c) : %08x\n", pbus_value); ++#if defined(AIR_LED_SUPPORT) ++ ret = en8811h_led_init(phydev); ++ if (ret < 0) { ++ printf("en8811h_led_init fail\n"); ++ } ++#endif ++ printf("EN8811H initialize OK ! (%s)\n", EN8811H_DRIVER_VERSION); ++ ++ ret = genphy_update_link(phydev); ++ if (ret) ++ { ++ printf("ret %d!\n", ret); ++ return ret; ++ } ++ ++ ret = genphy_parse_link(phydev); ++ if (ret) ++ { ++ printf("ret %d!\n", ret); ++ return ret; ++ } ++ ++ if (old_link && phydev->link) ++ return 0; ++ ++ phydev->speed = SPEED_100; ++ phydev->duplex = DUPLEX_FULL; ++ phydev->pause = 0; ++ phydev->asym_pause = 0; ++ ++ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); ++ if (reg < 0) ++ { ++ printf("MII_BMSR reg %d!\n", reg); ++ return reg; ++ } ++ reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR); ++ if (reg < 0) ++ { ++ printf("MII_BMSR reg %d!\n", reg); ++ return reg; ++ } ++ if(reg & BMSR_LSTATUS) ++ { ++ pbus_value = air_buckpbus_reg_read(phydev, 0x109D4); ++ if (0x10 & pbus_value) { ++ phydev->speed = SPEED_2500; ++ phydev->duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ ret = en8811h_get_autonego(phydev, &an); ++ if ((AUTONEG_ENABLE == an) && (0 == ret)) ++ { ++ printf("AN mode!\n"); ++ printf("SPEED 1000/100!\n"); ++ lpagb = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000); ++ if (lpagb < 0 ) ++ return lpagb; ++ advgb = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000); ++ if (adv < 0 ) ++ return adv; ++ common_adv_gb = (lpagb & (advgb << 2)); ++ ++ lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA); ++ if (lpa < 0 ) ++ return lpa; ++ adv = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE); ++ if (adv < 0 ) ++ return adv; ++ common_adv = (lpa & adv); ++ ++ phydev->speed = SPEED_10; ++ phydev->duplex = DUPLEX_HALF; ++ if (common_adv_gb & (LPA_1000FULL | LPA_1000HALF)) ++ { ++ phydev->speed = SPEED_1000; ++ if (common_adv_gb & LPA_1000FULL) ++ ++ phydev->duplex = DUPLEX_FULL; ++ } ++ else if (common_adv & (LPA_100FULL | LPA_100HALF)) ++ { ++ phydev->speed = SPEED_100; ++ if (common_adv & LPA_100FULL) ++ phydev->duplex = DUPLEX_FULL; ++ } ++ else ++ { ++ if (common_adv & LPA_10FULL) ++ phydev->duplex = DUPLEX_FULL; ++ } ++ } ++ else ++ { ++ printf("Force mode!\n"); ++ bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); ++ ++ if (bmcr < 0) ++ return bmcr; ++ ++ if (bmcr & BMCR_FULLDPLX) ++ phydev->duplex = DUPLEX_FULL; ++ else ++ phydev->duplex = DUPLEX_HALF; ++ ++ if (bmcr & BMCR_SPEED1000) ++ phydev->speed = SPEED_1000; ++ else if (bmcr & BMCR_SPEED100) ++ phydev->speed = SPEED_100; ++ else ++ phydev->speed = SPEED_100; ++ } ++ } ++ } ++ ++ return ret; ++} ++ ++#if AIR_UBOOT_REVISION > 0x202303 ++U_BOOT_PHY_DRIVER(en8811h) = { ++ .name = "Airoha EN8811H", ++ .uid = EN8811H_PHY_ID, ++ .mask = 0x0ffffff0, ++ .config = &en8811h_config, ++ .startup = &en8811h_startup, ++ .shutdown = &genphy_shutdown, ++}; ++#else ++static struct phy_driver AIR_EN8811H_driver = { ++ .name = "Airoha EN8811H", ++ .uid = EN8811H_PHY_ID, ++ .mask = 0x0ffffff0, ++ .config = &en8811h_config, ++ .startup = &en8811h_startup, ++ .shutdown = &genphy_shutdown, ++}; ++ ++int phy_air_en8811h_init(void) ++{ ++ phy_register(&AIR_EN8811H_driver); ++ return 0; ++} ++#endif +--- /dev/null ++++ b/drivers/net/phy/air_en8811h.h +@@ -0,0 +1,163 @@ ++/* SPDX-License-Identifier: GPL-2.0 */ ++/************************************************* ++ * FILE NAME: air_en8811h.h ++ * PURPOSE: ++ * EN8811H PHY Driver for Uboot ++ * NOTES: ++ * ++ * Copyright (C) 2023 Airoha Technology Corp. ++ *************************************************/ ++ ++#ifndef __EN8811H_H ++#define __EN8811H_H ++ ++#define AIR_UBOOT_REVISION ((((U_BOOT_VERSION_NUM / 1000) % 10) << 20) | \ ++ (((U_BOOT_VERSION_NUM / 100) % 10) << 16) | \ ++ (((U_BOOT_VERSION_NUM / 10) % 10) << 12) | \ ++ ((U_BOOT_VERSION_NUM % 10) << 8) | \ ++ (((U_BOOT_VERSION_NUM_PATCH / 10) % 10) << 4) | \ ++ ((U_BOOT_VERSION_NUM_PATCH % 10) << 0)) ++ ++#define EN8811H_PHY_ID1 0x03a2 ++#define EN8811H_PHY_ID2 0xa411 ++#define EN8811H_PHY_ID ((EN8811H_PHY_ID1 << 16) | EN8811H_PHY_ID2) ++#define EN8811H_SPEED_2500 0x03 ++#define EN8811H_PHY_READY 0x02 ++#define MAX_RETRY 5 ++ ++#define EN8811H_MD32_DM_SIZE 0x4000 ++#define EN8811H_MD32_DSP_SIZE 0x20000 ++ ++#define EN8811H_TX_POLARITY_NORMAL 0x1 ++#define EN8811H_TX_POLARITY_REVERSE 0x0 ++ ++#define EN8811H_RX_POLARITY_NORMAL (0x0 << 1) ++#define EN8811H_RX_POLARITY_REVERSE (0x1 << 1) ++ ++#ifndef BIT ++#define BIT(nr) (1UL << (nr)) ++#endif ++ ++/* CL45 MDIO control */ ++#define MII_MMD_ACC_CTL_REG 0x0d ++#define MII_MMD_ADDR_DATA_REG 0x0e ++#define MMD_OP_MODE_DATA BIT(14) ++/* MultiGBASE-T AN register */ ++#define MULTIG_ANAR_2500M (0x0080) ++#define MULTIG_LPAR_2500M (0x0020) ++ ++#define EN8811H_DRIVER_VERSION "v1.0.4" ++ ++/************************************************************ ++ * For reference only ++ * LED0 Link 2500/Blink 2500 TxRx (GPIO5) <-> BASE_T_LED0, ++ * LED1 Link 1000/Blink 1000 TxRx (GPIO4) <-> BASE_T_LED1, ++ * LED2 Link 100/Blink 100 TxRx (GPIO3) <-> BASE_T_LED2, ++ ************************************************************/ ++/* User-defined.B */ ++#define AIR_LED0_ON (LED_ON_EVT_LINK_2500M) ++#define AIR_LED0_BLK (LED_BLK_EVT_2500M_TX_ACT | LED_BLK_EVT_2500M_RX_ACT) ++#define AIR_LED1_ON (LED_ON_EVT_LINK_1000M) ++#define AIR_LED1_BLK (LED_BLK_EVT_1000M_TX_ACT | LED_BLK_EVT_1000M_RX_ACT) ++#define AIR_LED2_ON (LED_ON_EVT_LINK_100M) ++#define AIR_LED2_BLK (LED_BLK_EVT_100M_TX_ACT | LED_BLK_EVT_100M_RX_ACT) ++/* User-defined.E */ ++ ++#define LED_ON_CTRL(i) (0x024 + ((i)*2)) ++#define LED_ON_EN (1 << 15) ++#define LED_ON_POL (1 << 14) ++#define LED_ON_EVT_MASK (0x1ff) ++/* LED ON Event Option.B */ ++#define LED_ON_EVT_LINK_2500M (1 << 8) ++#define LED_ON_EVT_FORCE (1 << 6) ++#define LED_ON_EVT_HDX (1 << 5) ++#define LED_ON_EVT_FDX (1 << 4) ++#define LED_ON_EVT_LINK_DOWN (1 << 3) ++#define LED_ON_EVT_LINK_100M (1 << 1) ++#define LED_ON_EVT_LINK_1000M (1 << 0) ++/* LED ON Event Option.E */ ++ ++#define LED_BLK_CTRL(i) (0x025 + ((i)*2)) ++#define LED_BLK_EVT_MASK (0xfff) ++/* LED Blinking Event Option.B*/ ++#define LED_BLK_EVT_2500M_RX_ACT (1 << 11) ++#define LED_BLK_EVT_2500M_TX_ACT (1 << 10) ++#define LED_BLK_EVT_FORCE (1 << 9) ++#define LED_BLK_EVT_100M_RX_ACT (1 << 3) ++#define LED_BLK_EVT_100M_TX_ACT (1 << 2) ++#define LED_BLK_EVT_1000M_RX_ACT (1 << 1) ++#define LED_BLK_EVT_1000M_TX_ACT (1 << 0) ++/* LED Blinking Event Option.E*/ ++#define LED_ENABLE 1 ++#define LED_DISABLE 0 ++ ++#define EN8811H_LED_COUNT 3 ++ ++#define LED_BCR (0x021) ++#define LED_BCR_EXT_CTRL (1 << 15) ++#define LED_BCR_CLK_EN (1 << 3) ++#define LED_BCR_TIME_TEST (1 << 2) ++#define LED_BCR_MODE_MASK (3) ++#define LED_BCR_MODE_DISABLE (0) ++#define LED_BCR_MODE_2LED (1) ++#define LED_BCR_MODE_3LED_1 (2) ++#define LED_BCR_MODE_3LED_2 (3) ++ ++#define LED_ON_DUR (0x022) ++#define LED_ON_DUR_MASK (0xffff) ++ ++#define LED_BLK_DUR (0x023) ++#define LED_BLK_DUR_MASK (0xffff) ++ ++#define LED_GPIO_SEL_MASK 0x7FFFFFF ++ ++#define UNIT_LED_BLINK_DURATION 1024 ++ ++#define INVALID_DATA 0xffff ++#define PBUS_INVALID_DATA 0xffffffff ++ ++struct air_base_t_led_cfg_s { ++ u16 en; ++ u16 gpio; ++ u16 pol; ++ u16 on_cfg; ++ u16 blk_cfg; ++}; ++ ++enum { ++ AIR_LED2_GPIO3 = 3, ++ AIR_LED1_GPIO4, ++ AIR_LED0_GPIO5, ++ AIR_LED_LAST ++}; ++ ++enum { ++ AIR_BASE_T_LED0, ++ AIR_BASE_T_LED1, ++ AIR_BASE_T_LED2, ++ AIR_BASE_T_LED3 ++}; ++ ++enum { ++ AIR_LED_BLK_DUR_32M, ++ AIR_LED_BLK_DUR_64M, ++ AIR_LED_BLK_DUR_128M, ++ AIR_LED_BLK_DUR_256M, ++ AIR_LED_BLK_DUR_512M, ++ AIR_LED_BLK_DUR_1024M, ++ AIR_LED_BLK_DUR_LAST ++}; ++ ++enum { ++ AIR_ACTIVE_LOW, ++ AIR_ACTIVE_HIGH, ++}; ++ ++enum { ++ AIR_LED_MODE_DISABLE, ++ AIR_LED_MODE_USER_DEFINE, ++ AIR_LED_MODE_LAST ++}; ++ ++#endif /* End of __EN8811H_MD32_H */ ++ +--- a/drivers/net/eth-phy-uclass.c ++++ b/drivers/net/eth-phy-uclass.c +@@ -155,7 +155,7 @@ static int eth_phy_of_to_plat(struct ude + return 0; + } + +-static void eth_phy_reset(struct udevice *dev, int value) ++void eth_phy_reset(struct udevice *dev, int value) + { + struct eth_phy_device_priv *uc_priv = dev_get_uclass_priv(dev); + u32 delay; +--- a/include/eth_phy.h ++++ b/include/eth_phy.h +@@ -14,5 +14,6 @@ int eth_phy_binds_nodes(struct udevice * + int eth_phy_set_mdio_bus(struct udevice *eth_dev, struct mii_dev *mdio_bus); + struct mii_dev *eth_phy_get_mdio_bus(struct udevice *eth_dev); + int eth_phy_get_addr(struct udevice *dev); ++void eth_phy_reset(struct udevice *dev, int value); + + #endif diff --git a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch index a96345e6fe6..28175e02e87 100644 --- a/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch +++ b/package/boot/uboot-mediatek/patches/200-cmd-add-imsz-and-imszb.patch @@ -1,9 +1,10 @@ --- a/cmd/bootm.c +++ b/cmd/bootm.c -@@ -228,6 +228,65 @@ U_BOOT_CMD( +@@ -245,6 +245,67 @@ U_BOOT_CMD( /* iminfo - print header info for a requested image */ /*******************************************************************/ #if defined(CONFIG_CMD_IMI) ++#if defined(CONFIG_FIT) +#define SECTOR_SHIFT 9 +static int image_totalsize(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[], short int in_blocks) @@ -63,12 +64,13 @@ + "addr [maxhdrlen] [varname]\n" +); + ++#endif static int do_iminfo(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { ---- a/common/image-fit.c -+++ b/common/image-fit.c -@@ -1970,6 +1970,51 @@ static const char *fit_get_image_type_pr +--- a/boot/image-fit.c ++++ b/boot/image-fit.c +@@ -2051,6 +2051,47 @@ static const char *fit_get_image_type_pr return "unknown"; } @@ -87,16 +89,12 @@ + + hdrsize = fdt_totalsize(fit); + -+ /* simple FIT with internal images */ -+ if (hdrsize > 0x1000) -+ return hdrsize; ++ /* take care of simple FIT with internal images */ ++ max_size = hdrsize; + + images_noffset = fdt_path_offset(fit, FIT_IMAGES_PATH); -+ if (images_noffset < 0) { -+ printf("Can't find images parent node '%s' (%s)\n", -+ FIT_IMAGES_PATH, fdt_strerror(images_noffset)); -+ return 0; -+ } ++ if (images_noffset < 0) ++ goto out; + + for (ndepth = 0, + noffset = fdt_next_node(fit, images_noffset, &ndepth); @@ -105,7 +103,7 @@ + if (ndepth == 1) { + ret = fit_image_get_data_and_size(fit, noffset, &data, &data_size); + if (ret) -+ return 0; ++ goto out; + + img_total = data_size + (data - fit); + @@ -113,16 +111,16 @@ + } + } + ++out: + return max_size; +} + -+ - int fit_image_load(bootm_headers_t *images, ulong addr, + int fit_image_load(struct bootm_headers *images, ulong addr, const char **fit_unamep, const char **fit_uname_configp, - int arch, int image_type, int bootstage_id, + int arch, int ph_type, int bootstage_id, --- a/include/image.h +++ b/include/image.h -@@ -1041,6 +1041,7 @@ int fit_parse_subimage(const char *spec, +@@ -1049,6 +1049,7 @@ int fit_parse_subimage(const char *spec, ulong *addr, const char **image_name); int fit_get_subimage_count(const void *fit, int images_noffset); diff --git a/package/boot/uboot-mediatek/patches/210-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch b/package/boot/uboot-mediatek/patches/210-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch deleted file mode 100644 index 82d97f756c3..00000000000 --- a/package/boot/uboot-mediatek/patches/210-cmd-bootmenu-add-ability-to-select-item-by-shortkey.patch +++ /dev/null @@ -1,192 +0,0 @@ -From 26d4e2e58bf0007db74b47c783785c3305ea1fa0 Mon Sep 17 00:00:00 2001 -From: Weijie Gao <weijie.gao@mediatek.com> -Date: Tue, 19 Jan 2021 10:58:48 +0800 -Subject: [PATCH 17/23] cmd: bootmenu: add ability to select item by shortkey - -Add ability to use shortkey to select item for bootmenu command - -Signed-off-by: Weijie Gao <weijie.gao@mediatek.com> ---- - cmd/bootmenu.c | 77 +++++++++++++++++++++++++++++++++++++++++++++----- - 1 file changed, 70 insertions(+), 7 deletions(-) - ---- a/cmd/bootmenu.c -+++ b/cmd/bootmenu.c -@@ -11,6 +11,7 @@ - #include <menu.h> - #include <watchdog.h> - #include <malloc.h> -+#include <linux/ctype.h> - #include <linux/delay.h> - #include <linux/string.h> - -@@ -38,6 +39,7 @@ struct bootmenu_data { - int active; /* active menu entry */ - int count; /* total count of menu entries */ - struct bootmenu_entry *first; /* first menu entry */ -+ bool last_choiced; - }; - - enum bootmenu_key { -@@ -46,8 +48,27 @@ enum bootmenu_key { - KEY_DOWN, - KEY_SELECT, - KEY_QUIT, -+ KEY_CHOICE, - }; - -+static const char choice_chars[] = { -+ '1', '2', '3', '4', '5', '6', '7', '8', '9', -+ 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', -+ 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', -+ 'u', 'v', 'w', 'x', 'y', 'z' -+}; -+ -+static int find_choice(char choice) -+{ -+ int i; -+ -+ for (i = 0; i < ARRAY_SIZE(choice_chars); i++) -+ if (tolower(choice) == choice_chars[i]) -+ return i; -+ -+ return -1; -+} -+ - static char *bootmenu_getoption(unsigned short int n) - { - char name[MAX_ENV_SIZE]; -@@ -82,7 +103,7 @@ static void bootmenu_print_entry(void *d - } - - static void bootmenu_autoboot_loop(struct bootmenu_data *menu, -- enum bootmenu_key *key, int *esc) -+ enum bootmenu_key *key, int *esc, int *choice) - { - int i, c; - -@@ -115,6 +136,19 @@ static void bootmenu_autoboot_loop(struc - break; - default: - *key = KEY_NONE; -+ if (*esc) -+ break; -+ -+ *choice = find_choice(c); -+ if ((*choice >= 0 && -+ *choice < menu->count - 1)) { -+ *key = KEY_CHOICE; -+ } else if (c == '0') { -+ *choice = menu->count - 1; -+ *key = KEY_CHOICE; -+ } else { -+ *key = KEY_NONE; -+ } - break; - } - -@@ -136,10 +170,16 @@ static void bootmenu_autoboot_loop(struc - } - - static void bootmenu_loop(struct bootmenu_data *menu, -- enum bootmenu_key *key, int *esc) -+ enum bootmenu_key *key, int *esc, int *choice) - { - int c; - -+ if (menu->last_choiced) { -+ menu->last_choiced = false; -+ *key = KEY_SELECT; -+ return; -+ } -+ - if (*esc == 1) { - if (tstc()) { - c = getchar(); -@@ -165,6 +205,14 @@ static void bootmenu_loop(struct bootmen - if (c == '\e') { - *esc = 1; - *key = KEY_NONE; -+ } else { -+ *choice = find_choice(c); -+ if ((*choice >= 0 && *choice < menu->count - 1)) { -+ *key = KEY_CHOICE; -+ } else if (c == '0') { -+ *choice = menu->count - 1; -+ *key = KEY_CHOICE; -+ } - } - break; - case 1: -@@ -216,16 +264,17 @@ static char *bootmenu_choice_entry(void - struct bootmenu_data *menu = data; - struct bootmenu_entry *iter; - enum bootmenu_key key = KEY_NONE; -+ int choice = -1; - int esc = 0; - int i; - - while (1) { - if (menu->delay >= 0) { - /* Autoboot was not stopped */ -- bootmenu_autoboot_loop(menu, &key, &esc); -+ bootmenu_autoboot_loop(menu, &key, &esc, &choice); - } else { - /* Some key was pressed, so autoboot was stopped */ -- bootmenu_loop(menu, &key, &esc); -+ bootmenu_loop(menu, &key, &esc, &choice); - } - - switch (key) { -@@ -239,6 +288,12 @@ static char *bootmenu_choice_entry(void - ++menu->active; - /* no menu key selected, regenerate menu */ - return NULL; -+ case KEY_CHOICE: -+ menu->active = choice; -+ if (!menu->last_choiced) { -+ menu->last_choiced = true; -+ return NULL; -+ } - case KEY_SELECT: - iter = menu->first; - for (i = 0; i < menu->active; ++i) -@@ -294,6 +349,7 @@ static struct bootmenu_data *bootmenu_cr - menu->delay = delay; - menu->active = 0; - menu->first = NULL; -+ menu->last_choiced = false; - - default_str = env_get("bootmenu_default"); - if (default_str) -@@ -311,12 +367,19 @@ static struct bootmenu_data *bootmenu_cr - goto cleanup; - - len = sep-option; -- entry->title = malloc(len + 1); -+ entry->title = malloc(len + 4); - if (!entry->title) { - free(entry); - goto cleanup; - } -- memcpy(entry->title, option, len); -+ -+ if (i < ARRAY_SIZE(choice_chars)) { -+ len = sprintf(entry->title, "%c. %.*s", choice_chars[i], -+ len, option); -+ } else { -+ len = sprintf(entry->title, " %.*s", len, option); -+ } -+ - entry->title[len] = 0; - - len = strlen(sep + 1); -@@ -353,7 +416,7 @@ static struct bootmenu_data *bootmenu_cr - if (!entry) - goto cleanup; - -- entry->title = strdup("U-Boot console"); -+ entry->title = strdup("0. U-Boot console"); - if (!entry->title) { - free(entry); - goto cleanup; diff --git a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch index 3f98f13c6e1..a99b77be083 100644 --- a/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch +++ b/package/boot/uboot-mediatek/patches/211-cmd-bootmenu-custom-title.patch @@ -1,19 +1,10 @@ --- a/cmd/bootmenu.c +++ b/cmd/bootmenu.c -@@ -39,6 +39,7 @@ struct bootmenu_data { - int active; /* active menu entry */ - int count; /* total count of menu entries */ - struct bootmenu_entry *first; /* first menu entry */ -+ char *mtitle; /* custom menu title */ - bool last_choiced; - }; - -@@ -471,7 +472,12 @@ static void menu_display_statusline(stru +@@ -452,7 +452,11 @@ static void menu_display_statusline(stru printf(ANSI_CURSOR_POSITION, 1, 1); puts(ANSI_CLEAR_LINE); - printf(ANSI_CURSOR_POSITION, 2, 1); -- puts(" *** U-Boot Boot Menu ***"); -+ + printf(ANSI_CURSOR_POSITION, 2, 3); +- puts("*** U-Boot Boot Menu ***"); + if (menu->mtitle) + puts(menu->mtitle); + else @@ -22,11 +13,21 @@ puts(ANSI_CLEAR_LINE_TO_END); printf(ANSI_CURSOR_POSITION, 3, 1); puts(ANSI_CLEAR_LINE); -@@ -525,6 +531,7 @@ static void bootmenu_show(int delay) - return; +@@ -537,6 +541,7 @@ static enum bootmenu_ret bootmenu_show(i + return BOOTMENU_RET_FAIL; } + bootmenu->mtitle = env_get("bootmenu_title"); for (iter = bootmenu->first; iter; iter = iter->next) { - if (!menu_item_add(menu, iter->key, iter)) + if (menu_item_add(menu, iter->key, iter) != 1) goto cleanup; +--- a/include/menu.h ++++ b/include/menu.h +@@ -45,6 +45,7 @@ struct bootmenu_data { + int active; /* active menu entry */ + int count; /* total count of menu entries */ + struct bootmenu_entry *first; /* first menu entry */ ++ char *mtitle; /* custom menu title */ + bool last_choiced; + }; + diff --git a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch index 00143ccaea6..7bf87ef7b5a 100644 --- a/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch +++ b/package/boot/uboot-mediatek/patches/220-cmd-env-readmem.patch @@ -1,6 +1,6 @@ --- a/cmd/Kconfig +++ b/cmd/Kconfig -@@ -472,6 +472,12 @@ config CMD_ENV_EXISTS +@@ -622,6 +622,12 @@ config CMD_ENV_EXISTS Check if a variable is defined in the environment for use in shell scripting. @@ -15,7 +15,7 @@ help --- a/cmd/nvedit.c +++ b/cmd/nvedit.c -@@ -473,6 +473,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in +@@ -385,6 +385,60 @@ int do_env_ask(struct cmd_tbl *cmdtp, in } #endif @@ -76,7 +76,7 @@ #if defined(CONFIG_CMD_ENV_CALLBACK) static int print_static_binding(const char *var_name, const char *callback_name, void *priv) -@@ -1377,6 +1431,9 @@ static struct cmd_tbl cmd_env_sub[] = { +@@ -1201,6 +1255,9 @@ static struct cmd_tbl cmd_env_sub[] = { U_BOOT_CMD_MKENT(load, 1, 0, do_env_load, "", ""), #endif U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), @@ -86,7 +86,7 @@ #if defined(CONFIG_CMD_RUN) U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), #endif -@@ -1465,6 +1522,9 @@ static char env_help_text[] = +@@ -1284,6 +1341,9 @@ U_BOOT_LONGHELP(env, #if defined(CONFIG_CMD_NVEDIT_EFI) "env print -e [-guid guid] [-n] [name ...] - print UEFI environment\n" #endif @@ -96,7 +96,7 @@ #if defined(CONFIG_CMD_RUN) "env run var [...] - run commands in an environment variable\n" #endif -@@ -1574,6 +1634,17 @@ U_BOOT_CMD( +@@ -1392,6 +1452,17 @@ U_BOOT_CMD( ); #endif diff --git a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch index 587245d2ab0..48556937bd8 100644 --- a/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch +++ b/package/boot/uboot-mediatek/patches/230-cmd-add-pstore-check.patch @@ -1,6 +1,6 @@ --- a/cmd/pstore.c +++ b/cmd/pstore.c -@@ -207,6 +207,58 @@ static int pstore_set(struct cmd_tbl *cm +@@ -208,6 +208,58 @@ static int pstore_set(struct cmd_tbl *cm } /** @@ -59,7 +59,7 @@ * pstore_print_buffer() - Print buffer * @type: buffer type * @buffer: buffer to print -@@ -458,6 +510,7 @@ static int pstore_save(struct cmd_tbl *c +@@ -459,6 +511,7 @@ static int pstore_save(struct cmd_tbl *c static struct cmd_tbl cmd_pstore_sub[] = { U_BOOT_CMD_MKENT(set, 8, 0, pstore_set, "", ""), @@ -67,7 +67,7 @@ U_BOOT_CMD_MKENT(display, 3, 0, pstore_display, "", ""), U_BOOT_CMD_MKENT(save, 4, 0, pstore_save, "", ""), }; -@@ -531,6 +584,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore, +@@ -566,6 +619,8 @@ U_BOOT_CMD(pstore, 10, 0, do_pstore, " 'pmsg-size' is the size of the user space logs record.\n" " 'ecc-size' enables/disables ECC support and specifies ECC buffer size in\n" " bytes (0 disables it, 1 is a special value, means 16 bytes ECC).\n" diff --git a/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch new file mode 100644 index 00000000000..fd5fdd814b8 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/250-fix-mmc-erase-timeout.patch @@ -0,0 +1,11 @@ +--- a/drivers/mmc/mmc_write.c ++++ b/drivers/mmc/mmc_write.c +@@ -80,7 +80,7 @@ ulong mmc_berase(struct blk_desc *block_ + u32 start_rem, blkcnt_rem, erase_args = 0; + struct mmc *mmc = find_mmc_device(dev_num); + lbaint_t blk = 0, blk_r = 0; +- int timeout_ms = 1000; ++ int timeout_ms = blkcnt; + + if (!mmc) + return -1; diff --git a/package/boot/uboot-mediatek/patches/260-add-missing-type-u64.patch b/package/boot/uboot-mediatek/patches/260-add-missing-type-u64.patch deleted file mode 100644 index a6204c7b69e..00000000000 --- a/package/boot/uboot-mediatek/patches/260-add-missing-type-u64.patch +++ /dev/null @@ -1,10 +0,0 @@ ---- a/include/linux/types.h -+++ b/include/linux/types.h -@@ -1,6 +1,7 @@ - #ifndef _LINUX_TYPES_H - #define _LINUX_TYPES_H - -+typedef unsigned long long __u64; - #include <linux/posix_types.h> - #include <asm/types.h> - #include <stdbool.h> diff --git a/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch new file mode 100644 index 00000000000..f087bec72a6 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/280-image-fdt-save-name-of-FIT-configuration-in-chosen-node.patch @@ -0,0 +1,31 @@ +From 5f2d5915f8ea4785bc2b8a26955e176a7898c15b Mon Sep 17 00:00:00 2001 +From: Daniel Golle <daniel@makrotopia.org> +Date: Tue, 12 Apr 2022 21:00:43 +0100 +Subject: [PATCH] image-fdt: save name of FIT configuration in '/chosen' node + +It can be useful for the OS (Linux) to know which configuration has +been chosen by U-Boot when launching a FIT image. +Store the name of the FIT configuration node used in a new string +property called 'u-boot,bootconf' in the '/chosen' node in device tree. + +Signed-off-by: Daniel Golle <daniel@makrotopia.org> +Reviewed-by: Tom Rini <trini@konsulko.com> +--- + boot/image-fdt.c | 6 ++++++ + 1 file changed, 6 insertions(+) + +--- a/boot/image-fdt.c ++++ b/boot/image-fdt.c +@@ -637,6 +637,12 @@ int image_setup_libfdt(struct bootm_head + images->fit_uname_cfg, + strlen(images->fit_uname_cfg) + 1, 1); + ++ /* Store name of configuration node as u-boot,bootconf in /chosen node */ ++ if (images->fit_uname_cfg) ++ fdt_find_and_setprop(blob, "/chosen", "u-boot,bootconf", ++ images->fit_uname_cfg, ++ strlen(images->fit_uname_cfg) + 1, 1); ++ + /* Update ethernet nodes */ + fdt_fixup_ethernet(blob); + #if IS_ENABLED(CONFIG_CMD_PSTORE) diff --git a/package/boot/uboot-mediatek/patches/300-mt7622-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch index f45462eeab4..65990156c22 100644 --- a/package/boot/uboot-mediatek/patches/300-mt7622-generic-reset-button-ignore-env.patch +++ b/package/boot/uboot-mediatek/patches/301-mt7622-generic-reset-button-ignore-env.patch @@ -15,20 +15,22 @@ +#define CONFIG_RESET_BUTTON_LABEL "reset" +#endif - DECLARE_GLOBAL_DATA_PTR; - -@@ -20,7 +27,20 @@ int board_init(void) + #include <mtd.h> + #include <linux/mtd/mtd.h> +@@ -24,7 +31,22 @@ int board_init(void) int board_late_init(void) { - gd->env_valid = 1; //to load environment variable from persistent store + struct udevice *dev; -+ int ret; + + if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { + puts("reset button found\n"); +#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY -+ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } +#endif + if (button_get_state(dev) == BUTTON_ON) { + puts("button pushed, resetting environment\n"); @@ -39,14 +41,17 @@ env_relocate(); return 0; } ---- a/board/mediatek/mt7622/Kconfig -+++ b/board/mediatek/mt7622/Kconfig -@@ -14,4 +14,8 @@ config MTK_BROM_HEADER_INFO - string - default "media=nor" +--- a/arch/arm/mach-mediatek/Kconfig ++++ b/arch/arm/mach-mediatek/Kconfig +@@ -151,4 +151,11 @@ config MTK_BROM_HEADER_INFO + + source "board/mediatek/mt7629/Kconfig" +config RESET_BUTTON_LABEL + string "Button to trigger factory reset" + default "reset" + ++config RESET_BUTTON_SETTLE_DELAY ++ int "Delay to wait for button to settle" ++ default 0 endif diff --git a/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch new file mode 100644 index 00000000000..928dfe8428a --- /dev/null +++ b/package/boot/uboot-mediatek/patches/302-mt7623-generic-reset-button-ignore-env.patch @@ -0,0 +1,46 @@ +--- a/board/mediatek/mt7623/mt7623_rfb.c ++++ b/board/mediatek/mt7623/mt7623_rfb.c +@@ -4,8 +4,17 @@ + */ + + #include <common.h> ++#include <dm.h> ++#include <button.h> ++#include <env.h> ++#include <init.h> + #include <mmc.h> + #include <asm/global_data.h> ++#include <linux/delay.h> ++ ++#ifndef CONFIG_RESET_BUTTON_LABEL ++#define CONFIG_RESET_BUTTON_LABEL "reset" ++#endif + + DECLARE_GLOBAL_DATA_PTR; + +@@ -41,3 +50,25 @@ int mmc_get_env_dev(void) + return mmc_get_boot_dev(); + } + #endif ++ ++int board_late_init(void) ++{ ++ struct udevice *dev; ++ ++ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { ++ puts("reset button found\n"); ++#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } ++#endif ++ if (button_get_state(dev) == BUTTON_ON) { ++ puts("button pushed, resetting environment\n"); ++ gd->env_valid = ENV_INVALID; ++ } ++ } ++ ++ env_relocate(); ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch new file mode 100644 index 00000000000..45290149f3f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/303-mt7986-generic-reset-button-ignore-env.patch @@ -0,0 +1,43 @@ +--- a/board/mediatek/mt7986/mt7986_rfb.c ++++ b/board/mediatek/mt7986/mt7986_rfb.c +@@ -6,9 +6,16 @@ + + #include <common.h> + #include <config.h> ++#include <dm.h> ++#include <button.h> + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <linux/delay.h> ++ ++#ifndef CONFIG_RESET_BUTTON_LABEL ++#define CONFIG_RESET_BUTTON_LABEL "reset" ++#endif + + #include <mtd.h> + #include <linux/mtd/mtd.h> +@@ -24,7 +31,22 @@ int board_init(void) + + int board_late_init(void) + { +- gd->env_valid = 1; //to load environment variable from persistent store ++ struct udevice *dev; ++ ++ gd->env_valid = ENV_VALID; ++ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { ++ puts("reset button found\n"); ++#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } ++#endif ++ if (button_get_state(dev) == BUTTON_ON) { ++ puts("button pushed, resetting environment\n"); ++ gd->env_valid = ENV_INVALID; ++ } ++ } + env_relocate(); + return 0; + } diff --git a/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch new file mode 100644 index 00000000000..fc443349829 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/304-mt7981-generic-reset-button-ignore-env.patch @@ -0,0 +1,43 @@ +--- a/board/mediatek/mt7981/mt7981_rfb.c ++++ b/board/mediatek/mt7981/mt7981_rfb.c +@@ -6,9 +6,16 @@ + + #include <common.h> + #include <config.h> ++#include <dm.h> ++#include <button.h> + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <linux/delay.h> ++ ++#ifndef CONFIG_RESET_BUTTON_LABEL ++#define CONFIG_RESET_BUTTON_LABEL "reset" ++#endif + + #include <mtd.h> + #include <linux/mtd/mtd.h> +@@ -24,7 +31,22 @@ int board_init(void) + + int board_late_init(void) + { +- gd->env_valid = 1; //to load environment variable from persistent store ++ struct udevice *dev; ++ ++ gd->env_valid = ENV_VALID; ++ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { ++ puts("reset button found\n"); ++#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } ++#endif ++ if (button_get_state(dev) == BUTTON_ON) { ++ puts("button pushed, resetting environment\n"); ++ gd->env_valid = ENV_INVALID; ++ } ++ } + env_relocate(); + return 0; + } diff --git a/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch new file mode 100644 index 00000000000..2bbc5c1005f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/305-mt7988-generic-reset-button-ignore-env.patch @@ -0,0 +1,46 @@ +--- a/board/mediatek/mt7988/mt7988_rfb.c ++++ b/board/mediatek/mt7988/mt7988_rfb.c +@@ -4,7 +4,43 @@ + * Author: Sam Shih <sam.shih@mediatek.com> + */ + ++#include <common.h> ++#include <config.h> ++#include <dm.h> ++#include <button.h> ++#include <env.h> ++#include <init.h> ++#include <asm/global_data.h> ++#include <linux/delay.h> ++ ++#ifndef CONFIG_RESET_BUTTON_LABEL ++#define CONFIG_RESET_BUTTON_LABEL "reset" ++#endif ++ + int board_init(void) + { + return 0; + } ++ ++int board_late_init(void) ++{ ++ gd->env_valid = 1; //to load environment variable from persistent store ++ struct udevice *dev; ++ ++ gd->env_valid = ENV_VALID; ++ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { ++ puts("reset button found\n"); ++#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY ++ if (CONFIG_RESET_BUTTON_SETTLE_DELAY > 0) { ++ button_get_state(dev); ++ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); ++ } ++#endif ++ if (button_get_state(dev) == BUTTON_ON) { ++ puts("button pushed, resetting environment\n"); ++ gd->env_valid = ENV_INVALID; ++ } ++ } ++ env_relocate(); ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch new file mode 100644 index 00000000000..28d7e0a3f6e --- /dev/null +++ b/package/boot/uboot-mediatek/patches/310-mt7988-select-rootdisk.patch @@ -0,0 +1,67 @@ +--- a/board/mediatek/mt7988/mt7988_rfb.c ++++ b/board/mediatek/mt7988/mt7988_rfb.c +@@ -11,7 +11,9 @@ + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <asm/io.h> + #include <linux/delay.h> ++#include <linux/libfdt.h> + + #ifndef CONFIG_RESET_BUTTON_LABEL + #define CONFIG_RESET_BUTTON_LABEL "reset" +@@ -44,3 +46,54 @@ int board_late_init(void) + env_relocate(); + return 0; + } ++ ++#define MT7988_BOOT_NOR 0 ++#define MT7988_BOOT_SPIM_NAND 1 ++#define MT7988_BOOT_EMMC 2 ++#define MT7988_BOOT_SNFI_NAND 3 ++ ++int ft_system_setup(void *blob, struct bd_info *bd) ++{ ++ const u32 *media_handle_p; ++ int chosen, len, ret; ++ const char *media; ++ u32 media_handle; ++ ++ switch ((readl(0x1001f6f0) & 0xc00) >> 10) { ++ case MT7988_BOOT_NOR: ++ media = "rootdisk-nor"; ++ break ++ ;; ++ case MT7988_BOOT_SPIM_NAND: ++ media = "rootdisk-spim-nand"; ++ break ++ ;; ++ case MT7988_BOOT_EMMC: ++ media = "rootdisk-emmc"; ++ break ++ ;; ++ case MT7988_BOOT_SNFI_NAND: ++ media = "rootdisk-sd"; ++ break ++ ;; ++ } ++ ++ chosen = fdt_path_offset(blob, "/chosen"); ++ if (chosen <= 0) ++ return 0; ++ ++ media_handle_p = fdt_getprop(blob, chosen, media, &len); ++ if (media_handle_p <= 0 || len != 4) ++ return 0; ++ ++ media_handle = *media_handle_p; ++ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle)); ++ if (ret) { ++ printf("cannot set media phandle %s as rootdisk /chosen node\n", media); ++ return ret; ++ } ++ ++ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle)); ++ ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch new file mode 100644 index 00000000000..33121627655 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/311-mt7986-select-roodisk.patch @@ -0,0 +1,67 @@ +--- a/board/mediatek/mt7986/mt7986_rfb.c ++++ b/board/mediatek/mt7986/mt7986_rfb.c +@@ -11,7 +11,9 @@ + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <asm/io.h> + #include <linux/delay.h> ++#include <linux/libfdt.h> + + #ifndef CONFIG_RESET_BUTTON_LABEL + #define CONFIG_RESET_BUTTON_LABEL "reset" +@@ -83,3 +85,54 @@ int board_nmbm_init(void) + + return 0; + } ++ ++#define MT7986_BOOT_NOR 0 ++#define MT7986_BOOT_SPIM_NAND 1 ++#define MT7986_BOOT_EMMC 2 ++#define MT7986_BOOT_SNFI_NAND 3 ++ ++int ft_system_setup(void *blob, struct bd_info *bd) ++{ ++ const u32 *media_handle_p; ++ int chosen, len, ret; ++ const char *media; ++ u32 media_handle; ++ ++ switch ((readl(0x1001f6f0) & 0x300) >> 8) { ++ case MT7986_BOOT_NOR: ++ media = "rootdisk-nor"; ++ break ++ ;; ++ case MT7986_BOOT_SPIM_NAND: ++ media = "rootdisk-spim-nand"; ++ break ++ ;; ++ case MT7986_BOOT_EMMC: ++ media = "rootdisk-emmc"; ++ break ++ ;; ++ case MT7986_BOOT_SNFI_NAND: ++ media = "rootdisk-sd"; ++ break ++ ;; ++ } ++ ++ chosen = fdt_path_offset(blob, "/chosen"); ++ if (chosen <= 0) ++ return 0; ++ ++ media_handle_p = fdt_getprop(blob, chosen, media, &len); ++ if (media_handle_p <= 0 || len != 4) ++ return 0; ++ ++ media_handle = *media_handle_p; ++ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle)); ++ if (ret) { ++ printf("cannot set media phandle %s as rootdisk /chosen node\n", media); ++ return ret; ++ } ++ ++ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle)); ++ ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch new file mode 100644 index 00000000000..70cbf6b4630 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/312-mt7622-select-rootdisk.patch @@ -0,0 +1,141 @@ +--- a/board/mediatek/mt7622/mt7622_rfb.c ++++ b/board/mediatek/mt7622/mt7622_rfb.c +@@ -11,7 +11,9 @@ + #include <env.h> + #include <init.h> + #include <asm/global_data.h> ++#include <asm/io.h> + #include <linux/delay.h> ++#include <linux/libfdt.h> + + #ifndef CONFIG_RESET_BUTTON_LABEL + #define CONFIG_RESET_BUTTON_LABEL "reset" +@@ -22,10 +24,43 @@ + #include <nmbm/nmbm.h> + #include <nmbm/nmbm-mtd.h> + ++#define MT7622_TOPRGUSTRAP_PAR 0x10212060 ++#define MT7622_BOOT_SEQ_MASK 0x18 ++#define MT7622_BOOT_SEQ_SHIFT 3 ++#define MT7622_BOOT_SEQ_NOR_EMMC_SDXC 0x0 ++#define MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC 0x1 ++#define MT7622_BOOT_SEQ_NAND_EMMC_SDXC 0x2 ++#define MT7622_BOOT_SEQ_SDXC_EMMC_NAND 0x3 ++ ++#define MT7622_GPIO_MODE0 0x10211300 ++#define MT7622_GPIO_NAND_MODE_MASK 0x00f00000 ++#define MT7622_GPIO_NAND_MODE_SHIFT 20 ++#define MT7622_GPIO_NAND_MODE_EMMC 0x2 ++#define MT7622_GPIO_RGMII_MODE_MASK 0x0000f000 ++#define MT7622_GPIO_RGMII_MODE_SHIFT 12 ++#define MT7622_GPIO_RGMII_MODE_SDCX 0x2 ++#define MT7622_GPIO_SPI_MODE_MASK 0x00000f00 ++#define MT7622_GPIO_SPI_MODE_SHIFT 8 ++#define MT7622_GPIO_SPI_MODE_NAND 0x2 ++ ++#define MT7622_MSDC_INT 0x1124000C ++#define MT7622_MSDC_INT_BD_CS_ERR 0x200 ++ + DECLARE_GLOBAL_DATA_PTR; + ++static int gpio_mode0; ++static int msdc_int; ++ + int board_init(void) + { ++ /* ++ * Save content of GPIO_MODE0 as left behind by the BootROM. ++ * Also grab MSDC1 INT status to see if BootROM has been reading ++ * from SD card. ++ * Together this will allow to infer the device used for booting. ++ */ ++ gpio_mode0 = readl(MT7622_GPIO_MODE0); ++ msdc_int = readl(MT7622_MSDC_INT); + return 0; + } + +@@ -83,3 +118,84 @@ int board_nmbm_init(void) + + return 0; + } ++ ++int ft_system_setup(void *blob, struct bd_info *bd) ++{ ++ bool pinctrl_set_mmc = false; ++ bool pinctrl_set_snfi = false; ++ bool pinctrl_set_emmc = false; ++ bool msdc_bd_cs_err = false; ++ ++ const u32 *media_handle_p; ++ int chosen, len, ret; ++ const char *media; ++ u32 media_handle, strap; ++ ++ if ((gpio_mode0 & MT7622_GPIO_RGMII_MODE_MASK) >> ++ MT7622_GPIO_RGMII_MODE_SHIFT == MT7622_GPIO_RGMII_MODE_SDCX) ++ pinctrl_set_mmc = true; ++ ++ if ((gpio_mode0 & MT7622_GPIO_SPI_MODE_MASK) >> ++ MT7622_GPIO_SPI_MODE_SHIFT == MT7622_GPIO_SPI_MODE_NAND) ++ pinctrl_set_snfi = true; ++ ++ if ((gpio_mode0 & MT7622_GPIO_NAND_MODE_MASK) >> ++ MT7622_GPIO_NAND_MODE_SHIFT == MT7622_GPIO_NAND_MODE_EMMC) ++ pinctrl_set_emmc = true; ++ ++ if (msdc_int & MT7622_MSDC_INT_BD_CS_ERR) ++ msdc_bd_cs_err = true; ++ ++ strap = readl(MT7622_TOPRGUSTRAP_PAR); ++ strap &= MT7622_BOOT_SEQ_MASK; ++ strap >>= MT7622_BOOT_SEQ_SHIFT; ++ switch (strap) { ++ case MT7622_BOOT_SEQ_NOR_EMMC_SDXC: ++ if (!pinctrl_set_emmc) ++ media = "rootdisk-nor"; ++ else if (pinctrl_set_mmc) ++ media = "rootdisk-emmc"; ++ else ++ media = "rootdisk-sd"; ++ break ++ ;; ++ case MT7622_BOOT_SEQ_SPI_NAND_EMMC_SDXC: ++ if (pinctrl_set_snfi) ++ media = "rootdisk-snfi"; ++ else if (pinctrl_set_emmc) ++ media = "rootdisk-emmc"; ++ else ++ media = "rootdisk-sd"; ++ break ++ ;; ++ case MT7622_BOOT_SEQ_NAND_EMMC_SDXC: ++ case MT7622_BOOT_SEQ_SDXC_EMMC_NAND: ++ if (!pinctrl_set_emmc && pinctrl_set_mmc) ++ media = "rootdisk-nand"; ++ else if (pinctrl_set_emmc) ++ media = "rootdisk-emmc"; ++ else ++ media = "rootdisk-sd"; ++ break ++ ;; ++ } ++ ++ chosen = fdt_path_offset(blob, "/chosen"); ++ if (chosen <= 0) ++ return 0; ++ ++ media_handle_p = fdt_getprop(blob, chosen, media, &len); ++ if (media_handle_p <= 0 || len != 4) ++ return 0; ++ ++ media_handle = *media_handle_p; ++ ret = fdt_setprop(blob, chosen, "rootdisk", &media_handle, sizeof(media_handle)); ++ if (ret) { ++ printf("cannot set media phandle %s as rootdisk /chosen node\n", media); ++ return ret; ++ } ++ ++ printf("set /chosen/rootdisk to bootrom media: %s (phandle 0x%08x)\n", media, fdt32_to_cpu(media_handle)); ++ ++ return 0; ++} diff --git a/package/boot/uboot-mediatek/patches/350-add-support-for-Winbond-W25Q512JV.patch b/package/boot/uboot-mediatek/patches/350-add-support-for-Winbond-W25Q512JV.patch deleted file mode 100644 index 2a42a6f1c16..00000000000 --- a/package/boot/uboot-mediatek/patches/350-add-support-for-Winbond-W25Q512JV.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/drivers/mtd/spi/spi-nor-ids.c -+++ b/drivers/mtd/spi/spi-nor-ids.c -@@ -329,6 +329,8 @@ const struct flash_info spi_nor_ids[] = - SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) - }, - { INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, -+ { INFO("w25q512jv", 0xef4020, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_DUAL_READ | -+ SPI_NOR_HAS_TB | SPI_NOR_HAS_LOCK) }, - { INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - #endif diff --git a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch index c42a2c628bb..ca011aeca96 100644 --- a/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/400-update-bpir2-defconfig.patch @@ -1,18 +1,17 @@ --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig -@@ -4,53 +4,137 @@ CONFIG_ARCH_MEDIATEK=y - CONFIG_SYS_TEXT_BASE=0x81e00000 - CONFIG_SYS_MALLOC_F_LEN=0x4000 +@@ -7,34 +7,105 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 -CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_SIZE=0x10000 CONFIG_ENV_OFFSET=0x100000 - CONFIG_TARGET_MT7623=y CONFIG_DEFAULT_DEVICE_TREE="mt7623n-bananapi-bpi-r2" -+CONFIG_USE_DEFAULT_ENV_FILE=y - CONFIG_DISTRO_DEFAULTS=y + CONFIG_TARGET_MT7623=y + CONFIG_SYS_LOAD_ADDR=0x84000000 CONFIG_FIT=y --CONFIG_FIT_VERBOSE=y + CONFIG_FIT_VERBOSE=y +CONFIG_FIT_ENABLE_SHA256_SUPPORT=y +CONFIG_LED=y +CONFIG_LED_BLINK=y @@ -22,6 +21,9 @@ +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_MENU_SHOW=y +CONFIG_BOARD_LATE_INIT=y ++# CONFIG_BOOTSTD is not set ++# CONFIG_BOOT_DEFAULTS is not set + CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTDELAY=3 +CONFIG_BOOTP_SEND_HOSTNAME=y CONFIG_DEFAULT_FDT_FILE="mt7623n-bananapi-bpi-r2.dtb" @@ -34,7 +36,11 @@ +CONFIG_CMD_ENV_FLAGS=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SYS_PROMPT="U-Boot> " ++CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_SYS_PROMPT="MT7623> " + CONFIG_SYS_MAXARGS=8 + CONFIG_SYS_PBSIZE=1049 + CONFIG_SYS_BOOTM_LEN=0x4000000 CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_BOOTP=y +CONFIG_CMD_BUTTON=y @@ -62,16 +68,11 @@ +CONFIG_CMD_LINK_LOCAL=y +CONFIG_CMD_MBR=y CONFIG_CMD_MMC=y --CONFIG_CMD_READ=y + CONFIG_CMD_READ=y -# CONFIG_CMD_SETEXPR is not set -+CONFIG_CMD_MTD=y - # CONFIG_CMD_NFS is not set -+CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y +CONFIG_CMD_PXE=y -+CONFIG_CMD_PWM=y -+CONFIG_CMD_SMC=y +CONFIG_CMD_TFTPBOOT=y +CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_ASKENV=y @@ -85,81 +86,65 @@ +CONFIG_CMD_STRINGS=y +CONFIG_CMD_USB=y +CONFIG_CMD_UUID=y -+CONFIG_CMD_MMC=y -+CONFIG_CMD_READ=y +CONFIG_CMD_SCSI=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_DM_ETH=y +CONFIG_DM_GPIO=y +CONFIG_DM_SCSI=y +CONFIG_DM_MMC=y -+CONFIG_DM_MTD=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y -+CONFIG_DM_SERIAL=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_USB=y +CONFIG_DM_PCI=y -+CONFIG_DM_PWM=y +CONFIG_AHCI=y +CONFIG_AHCI_PCI=y +CONFIG_SCSI_AHCI=y +CONFIG_SCSI=y -+CONFIG_PWM_MTK=y +CONFIG_HUSH_PARSER=y -+CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_NETCONSOLE=y - CONFIG_REGMAP=y - CONFIG_SYSCON=y - CONFIG_CLK=y --CONFIG_DM_MMC=y -+CONFIG_LZMA=y -+CONFIG_MEDIATEK_ETH=y - # CONFIG_MMC_QUIRKS is not set + CONFIG_USE_IPADDR=y + CONFIG_IPADDR="192.168.1.1" + CONFIG_USE_SERVERIP=y +@@ -46,6 +117,12 @@ CONFIG_CLK=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y CONFIG_MMC_MTK=y -+CONFIG_MTK_AHCI=y -+CONFIG_MTK_POWER_DOMAIN=y -+CONFIG_MTK_SERIAL=y -+CONFIG_MTK_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_PARTITION_UUIDS=y +CONFIG_PCI=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PHY=y ++CONFIG_PINCONF=y CONFIG_PHY_FIXED=y --CONFIG_DM_ETH=y --CONFIG_MEDIATEK_ETH=y + CONFIG_MEDIATEK_ETH=y CONFIG_PINCTRL=y - CONFIG_PINCONF=y - CONFIG_PINCTRL_MT7623=y - CONFIG_POWER_DOMAIN=y --CONFIG_MTK_POWER_DOMAIN=y --CONFIG_DM_SERIAL=y --CONFIG_MTK_SERIAL=y +@@ -55,10 +132,13 @@ CONFIG_POWER_DOMAIN=y + CONFIG_MTK_POWER_DOMAIN=y + CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y +CONFIG_RANDOM_UUID=y +CONFIG_REGEX=y CONFIG_SYSRESET=y CONFIG_SYSRESET_WATCHDOG=y CONFIG_TIMER=y --CONFIG_MTK_TIMER=y + CONFIG_MTK_TIMER=y +CONFIG_VERSION_VARIABLE=y CONFIG_WDT_MTK=y --CONFIG_LZMA=y + CONFIG_LZMA=y # CONFIG_EFI_GRUB_ARM32_WORKAROUND is not set --- /dev/null +++ b/bananapi_bpi-r2_env -@@ -0,0 +1,64 @@ +@@ -0,0 +1,70 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x88000000 +dtaddr=0x83f00000 -+console=earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200 ++console=earlycon=uart8250,mmio32,0x11004000 console=ttyS2,115200 console=tty1 +initrd_high=0xafffffff +part_default=3 +part_recovery=2 @@ -167,6 +152,8 @@ +bootdelay=0 +bootfile=openwrt-mediatek-mt7623-bananapi_bpi-r2-initramfs-recovery.itb +bootfile_upg=openwrt-mediatek-mt7623-bananapi_bpi-r2-squashfs-sysupgrade.itb ++bootled_pwr=bpi-r2:pio:green ++bootled_rec=bpi-r2:pio:blue +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 +bootmenu_default=0 +bootmenu_delay=0 @@ -176,7 +163,7 @@ +bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever +boot_first=if button factory ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu -+boot_tftp_forever=led bpi-r64:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_forever=led bpi-r2:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run mmc_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run mmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr @@ -193,7 +180,7 @@ +emmc_read_recovery=mmc dev 0 0 ; part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol +mmc_write_production=if test "$bootedfrom" = "SD" ; then run sdmmc_write_production ; else run emmc_write_production ; fi +mmc_write_recovery=if test "$bootedfrom" = "SD" ; run sdmmc_write_recovery ; else run emmc_write_recovery ; fi -+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size +mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 +reset_factory=eraseenv && reset +sdmmc_read_emmc_hdr=mmc dev 1 && mmc read $loadaddr 0x1ff8 0x8 @@ -205,9 +192,13 @@ +sdmmc_write_recovery=iminfo $fileaddr && mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol +_checkbootedfrom=setenv _checkbootedfrom ; if itest.l *81dffff0 == 434d4d65 ; then setenv bootedfrom eMMC ; else setenv bootedfrom SD ; fi +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv -+_firstboot=setenv _firstboot ; led bpi-r64:pio:blue on ; run _checkbootedfrom _switch_to_menu _update_bootdev _update_bootcmd _update_bootcmd2 _init_env boot_first -+_update_bootcmd=setenv _update_bootcmd ; if test "$bootedfrom" = "SD" ; then setenv boot_production "run sdmmc_read_production && bootm $loadaddr" ; else setenv boot_production "run emmc_read_production && bootm $loadaddr" ; fi -+_update_bootcmd2=setenv _update_bootcmd2 ; if test "$bootedfrom" = "SD" ; then setenv boot_recovery "run sdmmc_read_recovery && bootm $loadaddr" ; else setenv boot_recovery "run emmc_read_recovery && bootm $loadaddr" ; fi ++_firstboot=setenv _firstboot ; led $bootled_pwr off ;led $bootled_rec on ; run _checkbootedfrom _switch_to_menu _update_bootdev _update_bootcmd _update_bootcmd2 _init_env boot_first ++_set_bootcmd_sdmmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr ; led $bootled_pwr off" ++_set_bootcmd_emmc=setenv boot_production "led $bootled_rec off ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr ; led $bootled_pwr off" ++_update_bootcmd=setenv _update_bootcmd ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd_sdmmc ; else run _set_bootcmd_emmc ; fi ; setenv _set_bootcmd_sdmmc ; setenv _set_bootcmd_emmc ++_set_bootcmd2_sdmmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr ; led $bootled_rec off" ++_set_bootcmd2_emmc=setenv boot_recovery "led $bootled_pwr off ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr ; led $bootled_rec off" ++_update_bootcmd2=setenv _update_bootcmd2 ; if test "$bootedfrom" = "SD" ; then run _set_bootcmd2_sdmmc ; else run _set_bootcmd2_emmc ; fi ; setenv _set_bootcmd2_sdmmc ; setenv _set_bootcmd2_emmc +_update_bootdev=setenv _update_bootdev ; if test "$bootedfrom" = "SD" ; then setenv bootargs "$console root=/dev/mmcblk1p65" ; else setenv bootargs "$console root=/dev/mmcblk0p65" ; fi +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [0;36m[$bootedfrom][0m [33m$ver[0m" ; run _set_bm2 @@ -221,7 +212,15 @@ +_set_bmf=setenv _set_bmf ; setenv bootmenu_${_menu_next} "Reset all settings to factory defaults.=run reset_factory ; reset" ; setenv _menu_next --- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts -@@ -66,6 +66,15 @@ +@@ -6,6 +6,7 @@ + */ + + /dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> + #include "mt7623.dtsi" + #include "mt7623-u-boot.dtsi" + +@@ -66,6 +67,16 @@ default-state = "off"; }; }; @@ -232,65 +231,9 @@ + factory { + label = "factory"; + gpios = <&gpio 256 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; + }; + }; }; ð { ---- a/board/mediatek/mt7623/mt7623_rfb.c -+++ b/board/mediatek/mt7623/mt7623_rfb.c -@@ -6,6 +6,17 @@ - #include <common.h> - #include <mmc.h> - #include <asm/global_data.h> -+#include <config.h> -+#include <dm.h> -+#include <button.h> -+#include <env.h> -+#include <init.h> -+#include <asm/global_data.h> -+#include <linux/delay.h> -+ -+#ifndef CONFIG_RESET_BUTTON_LABEL -+#define CONFIG_RESET_BUTTON_LABEL "reset" -+#endif - - DECLARE_GLOBAL_DATA_PTR; - -@@ -17,6 +28,25 @@ int board_init(void) - return 0; - } - -+int board_late_init(void) -+{ -+ struct udevice *dev; -+ -+ if (!button_get_by_label(CONFIG_RESET_BUTTON_LABEL, &dev)) { -+ puts("reset button found\n"); -+#ifdef CONFIG_RESET_BUTTON_SETTLE_DELAY -+ mdelay(CONFIG_RESET_BUTTON_SETTLE_DELAY); -+#endif -+ if (button_get_state(dev) == BUTTON_ON) { -+ puts("button pushed, resetting environment\n"); -+ gd->env_valid = ENV_INVALID; -+ } -+ } -+ -+ env_relocate(); -+ return 0; -+} -+ - #ifdef CONFIG_MMC - int mmc_get_boot_dev(void) - { ---- a/board/mediatek/mt7623/Kconfig -+++ b/board/mediatek/mt7623/Kconfig -@@ -10,4 +10,8 @@ config MTK_BROM_HEADER_INFO - string - default "lk=1" - -+config RESET_BUTTON_LABEL -+ string "Button to trigger factory reset" -+ default "reset" -+ - endif diff --git a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch index 37d1b6a6717..6528b165f52 100644 --- a/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch +++ b/package/boot/uboot-mediatek/patches/401-update-u7623-defconfig.patch @@ -1,15 +1,240 @@ --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig -@@ -52,3 +52,12 @@ CONFIG_TIMER=y - CONFIG_MTK_TIMER=y - CONFIG_WDT_MTK=y - CONFIG_LZMA=y +@@ -7,33 +7,109 @@ CONFIG_SYS_MALLOC_F_LEN=0x4000 + CONFIG_NR_DRAM_BANKS=1 + CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y + CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x81ffff10 +-CONFIG_ENV_SIZE=0x1000 ++CONFIG_ENV_SIZE=0x10000 + CONFIG_ENV_OFFSET=0x100000 + CONFIG_DEFAULT_DEVICE_TREE="mt7623a-unielec-u7623-02-emmc" + CONFIG_TARGET_MT7623=y + CONFIG_SYS_LOAD_ADDR=0x84000000 + CONFIG_FIT=y + CONFIG_FIT_VERBOSE=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_BOARD_LATE_INIT=y ++# CONFIG_BOOTSTD is not set ++# CONFIG_BOOT_DEFAULTS is not set + CONFIG_DISTRO_DEFAULTS=y + CONFIG_BOOTDELAY=3 ++CONFIG_BOOTP_SEND_HOSTNAME=y + CONFIG_DEFAULT_FDT_FILE="mt7623a-unielec-u7623-02-emmc.dtb" + CONFIG_SYS_CONSOLE_IS_IN_ENV=y ++CONFIG_DEFAULT_ENV_FILE="unielec_u7623-02_env" ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_RESET_BUTTON_LABEL="factory" ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_CMD_ENV_FLAGS=y + # CONFIG_DISPLAY_BOARDINFO is not set +-CONFIG_SYS_PROMPT="U-Boot> " ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_SYS_PROMPT="MT7623> " + CONFIG_SYS_MAXARGS=8 + CONFIG_SYS_PBSIZE=1049 + CONFIG_SYS_BOOTM_LEN=0x4000000 + CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y +CONFIG_CMD_BOOTZ=y -+CONFIG_OF_LIBFDT_OVERLAY=y -+#enables savenenv-command -+CONFIG_ENV_IS_IN_FAT=y -+CONFIG_ENV_FAT_INTERFACE="mmc" -+CONFIG_ENV_FAT_DEVICE_AND_PART="0:2" -+CONFIG_ENV_FAT_FILE="uboot.env" ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y + # CONFIG_CMD_ELF is not set + # CONFIG_CMD_XIMG is not set + CONFIG_CMD_GPIO=y +-CONFIG_CMD_GPT=y ++# CONFIG_CMD_GPT is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_MBR=y + CONFIG_CMD_MMC=y + CONFIG_CMD_READ=y +-# CONFIG_CMD_SETEXPR is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y +CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SATA=y +CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_CMD_READ=y ++CONFIG_CMD_SCSI=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_ETH=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_DM_MMC=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PCI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_HUSH_PARSER=y + CONFIG_ENV_IS_IN_MMC=y + CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_SYS_MMC_ENV_DEV=0 ++CONFIG_ENV_OVERWRITE=y + CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_NETCONSOLE=y + CONFIG_USE_IPADDR=y + CONFIG_IPADDR="192.168.1.1" + CONFIG_USE_SERVERIP=y +@@ -45,6 +121,11 @@ CONFIG_CLK=y + CONFIG_SUPPORT_EMMC_BOOT=y + CONFIG_MMC_HS400_SUPPORT=y + CONFIG_MMC_MTK=y ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PHY=y + CONFIG_PHY_FIXED=y + CONFIG_MEDIATEK_ETH=y + CONFIG_PINCTRL=y +@@ -54,9 +135,12 @@ CONFIG_POWER_DOMAIN=y + CONFIG_MTK_POWER_DOMAIN=y + CONFIG_DM_SERIAL=y + CONFIG_MTK_SERIAL=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y + CONFIG_SYSRESET=y + CONFIG_SYSRESET_WATCHDOG=y + CONFIG_TIMER=y + CONFIG_MTK_TIMER=y ++CONFIG_VERSION_VARIABLE=y + CONFIG_WDT_MTK=y + CONFIG_LZMA=y +--- /dev/null ++++ b/unielec_u7623-02_env +@@ -0,0 +1,47 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x88000000 ++dtaddr=0x83f00000 ++console=earlycon=uart8250,mmio32,0x11004000 console=ttyS0,115200 ++initrd_high=0xafffffff ++part_default=3 ++part_recovery=2 ++bootcmd=run boot_mmc ++bootdelay=0 ++bootfile=openwrt-mediatek-mt7623-unielec_u7623-02-initramfs-recovery.itb ++bootfile_upg=openwrt-mediatek-mt7623-unielec_u7623-02-squashfs-sysupgrade.itb ++bootled_rec=u7623-01:green:led3 ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=Reboot.=reset ++bootmenu_7=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_first=if button factory ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_production=run emmc_read_production && bootm $loadaddr ++boot_recovery=run emmc_read_recovery && bootm $loadaddr ++boot_tftp_forever=led bpi-r64:pio:blue on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_mmc=run boot_production ; run boot_recovery ++emmc_write_production=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=mmc dev 0 0 ; iminfo $loadaddr && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++emmc_read_production=mmc dev 0 0 ; part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=mmc dev 0 0 ; part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++reset_factory=eraseenv && reset ++_init_env=setenv _init_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu _update_bootdev _init_env boot_first ++_update_bootdev=setenv _update_bootdev ; setenv bootargs "$console root=/dev/mmcblk0p65" ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- a/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts ++++ b/arch/arm/dts/mt7623a-unielec-u7623-02-emmc.dts +@@ -6,6 +6,7 @@ + */ + + /dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> + #include "mt7623.dtsi" + #include "mt7623-u-boot.dtsi" + +@@ -50,6 +51,18 @@ + regulator-always-on; + }; + ++ gpio-keys { ++ compatible = "gpio-keys"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&key_pins_a>; ++ ++ factory { ++ label = "factory"; ++ gpios = <&gpio 256 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ }; ++ + leds { + compatible = "gpio-leds"; + +@@ -109,6 +122,19 @@ + }; + }; + ++ key_pins_a: keys-alt { ++ mux { ++ function = "gpio"; ++ groups = "msdc3"; ++ }; ++ ++ conf { ++ pins = "MSDC0E_DAT0", "MSDC0E_DAT1"; ++ input-enable; ++ bias-pull-up; ++ }; ++ }; ++ + mmc0_pins_default: mmc0default { + mux { + function = "msdc"; diff --git a/package/boot/uboot-mediatek/patches/402-update-bananapi-bpi-r64-device-tree.patch b/package/boot/uboot-mediatek/patches/402-update-bananapi-bpi-r64-device-tree.patch index 781a6857219..c8066a7e2d4 100644 --- a/package/boot/uboot-mediatek/patches/402-update-bananapi-bpi-r64-device-tree.patch +++ b/package/boot/uboot-mediatek/patches/402-update-bananapi-bpi-r64-device-tree.patch @@ -1,6 +1,14 @@ --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts -@@ -20,6 +20,7 @@ +@@ -5,6 +5,7 @@ + */ + + /dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> + #include "mt7622.dtsi" + #include "mt7622-u-boot.dtsi" + +@@ -20,6 +21,7 @@ aliases { spi0 = &snfi; @@ -8,7 +16,7 @@ }; memory@40000000 { -@@ -27,6 +28,42 @@ +@@ -27,6 +29,44 @@ reg = <0x40000000 0x40000000>; }; @@ -18,11 +26,13 @@ + reset { + label = "reset"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; + }; + + wps { + label = "wps"; + gpios = <&gpio 102 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_WPS_BUTTON>; + }; + }; + @@ -51,7 +61,15 @@ reg_1p8v: regulator-1p8v { compatible = "regulator-fixed"; regulator-name = "fixed-1.8V"; -@@ -199,7 +236,7 @@ +@@ -182,6 +222,7 @@ + }; + + &uart0 { ++ mediatek,force-highspeed; + status = "okay"; + }; + +@@ -197,7 +238,7 @@ status = "okay"; bus-width = <8>; max-frequency = <50000000>; @@ -60,7 +78,7 @@ vmmc-supply = <®_3p3v>; vqmmc-supply = <®_3p3v>; non-removable; -@@ -210,7 +247,7 @@ +@@ -208,7 +249,7 @@ pinctrl-0 = <&mmc1_pins_default>; status = "okay"; bus-width = <4>; diff --git a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch index 1dc2a84893a..2ec57708067 100644 --- a/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch +++ b/package/boot/uboot-mediatek/patches/403-add-bananapi_bpi-r64-snand.patch @@ -1,6 +1,6 @@ --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts -@@ -19,7 +19,7 @@ +@@ -20,7 +20,7 @@ }; aliases { @@ -9,7 +9,7 @@ ethernet0 = ð }; -@@ -205,17 +205,11 @@ +@@ -208,16 +208,27 @@ }; }; @@ -20,14 +20,28 @@ +&snand { + pinctrl-names = "default"; + pinctrl-0 = <&snfi_pins>; ++ quad-spi; status = "okay"; -- + - spi-flash@0{ - compatible = "jedec,spi-nor"; - reg = <0>; -- u-boot,dm-pre-reloc; -- }; -+ quad-spi; +- bootph-all; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@80000 { ++ label = "ubi"; ++ reg = <0x80000 0x7f80000>; ++ compatible = "linux,ubi"; ++ }; + }; }; - &uart0 { diff --git a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch index 9e694c9c8b0..1a9b859e7ad 100644 --- a/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch +++ b/package/boot/uboot-mediatek/patches/404-add-bananapi_bpi-r64_defconfigs.patch @@ -1,12 +1,14 @@ --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-sdmmc_defconfig -@@ -0,0 +1,158 @@ +@@ -0,0 +1,164 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7622=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -15,6 +17,7 @@ +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-sdmmc_env" +CONFIG_NET_RANDOM_ETHADDR=y @@ -124,7 +127,6 @@ +CONFIG_PCI=y +CONFIG_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)" +CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PINCTRL=y @@ -159,17 +161,21 @@ +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/bananapi_bpi-r64-sdmmc_env -@@ -0,0 +1,82 @@ +@@ -0,0 +1,81 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x48000000 -+bootargs=root=/dev/mmcblk1p65 ++bootargs=root=/dev/fit0 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi -+bootconf=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata ++bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata +bootdelay=0 +bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb +bootfile_emmcbl2=openwrt-mediatek-mt7622-bananapi_bpi-r64-emmc-preloader.bin @@ -204,7 +210,6 @@ +boot_ubi=ubi part ubi && setenv bootargs && run boot_ubi_production ; run boot_ubi_recovery +boot_ubi_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr ; led $bootled_pwr off +boot_ubi_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off -+check_ubi=ubi part ubi || run ubi_format +emmc_init=run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv +emmc_init_bl=run sdmmc_read_emmc_bl2 && run emmc_write_bl2 && run sdmmc_read_emmc_hdr && run emmc_write_hdr && run sdmmc_read_emmc_fip && run emmc_write_fip +emmc_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run emmc_write_production @@ -213,8 +218,8 @@ +emmc_write_hdr=mmc dev 0 0 && mmc erase 0x0 0x40 && mmc write $loadaddr 0x0 0x40 +emmc_write_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol +emmc_write_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol -+mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $loadaddr 0x$part_addr 0x$image_size -+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 +part_default=production +part_recovery=recovery +reset_factory=eraseenv && reset @@ -227,32 +232,34 @@ +sdmmc_read_snand_fip=mmc dev 1 && part start mmc 1 install part_addr && setexpr offset $part_addr + 0x2400 && mmc read $loadaddr $offset 0x1000 +sdmmc_write_production=mmc dev 1 && part start mmc 1 $part_default part_addr && part size mmc 1 $part_default part_size && run mmc_write_vol +sdmmc_write_recovery=mmc dev 1 && part start mmc 1 $part_recovery part_addr && part size mmc 1 $part_recovery part_size && run mmc_write_vol -+snand_write_fip=mtd erase fip && mtd write fip $loadaddr -+snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr -+ubi_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3 -+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset -+ubi_init=run ubi_init_bl && ubi detach && mtd erase ubi && ubi part ubi && run ubi_create_env && run ubi_init_openwrt ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000 ++ubi_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt +ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production -+ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run snand_write_fip ++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data -+ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize -+ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize +_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv +_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-emmc_defconfig -@@ -0,0 +1,145 @@ +@@ -0,0 +1,152 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7622=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -261,6 +268,7 @@ +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-emmc_env" +CONFIG_NET_RANDOM_ETHADDR=y @@ -392,6 +400,10 @@ +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/bananapi_bpi-r64-emmc_env @@ -0,0 +1,56 @@ @@ -399,10 +411,10 @@ +serverip=192.168.1.254 +loadaddr=0x48000000 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi -+bootargs=root=/dev/mmcblk0p65 -+bootconf=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata ++bootargs=root=/dev/fit0 ++bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata +bootdelay=0 +bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb +bootfile_upg=openwrt-mediatek-mt7622-bananapi_bpi-r64-squashfs-sysupgrade.itb @@ -442,8 +454,8 @@ +emmc_write_fip=mmc dev 0 0 && mmc erase 0x1000 0x1000 && mmc write $loadaddr 0x1000 0x1000 && mmc erase 0x2000 0x800 +emmc_read_production=mmc dev 0 && part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol +emmc_read_recovery=mmc dev 0 && part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol -+mmc_write_vol=imszb $fileaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$part_size && mmc write $fileaddr 0x$part_addr 0x$image_size -+mmc_read_vol=mmc read $loadaddr $part_addr 0x8 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size ++mmc_write_vol=imszb $fileaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $fileaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size +part_default=production +part_recovery=recovery +reset_factory=eraseenv && reset @@ -453,12 +465,14 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- /dev/null +++ b/configs/mt7622_bananapi_bpi-r64-snand_defconfig -@@ -0,0 +1,139 @@ +@@ -0,0 +1,145 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -467,6 +481,7 @@ +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-bananapi-bpi-r64" +CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r64-snand_env" +CONFIG_DISTRO_DEFAULTS=y @@ -560,7 +575,6 @@ +CONFIG_PCI=y +CONFIG_MTD=y +CONFIG_MTD_UBI_FASTMAP=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),2048k(fip),-(ubi)" +CONFIG_DM_PCI=y +CONFIG_PCIE_MEDIATEK=y +CONFIG_PINCTRL=y @@ -593,17 +607,21 @@ +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.3" --- /dev/null +++ b/bananapi_bpi-r64-snand_env -@@ -0,0 +1,57 @@ +@@ -0,0 +1,56 @@ +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x48000000 -+bootargs=root=/dev/ubiblock0_2p1 ++bootargs=ubi.block=0,fit root=/dev/fit0 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi -+bootconf=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_pcie=config-mt7622-bananapi-bpi-r64-pcie1 -+bootconf_sata=config-mt7622-bananapi-bpi-r64-sata ++bootconf=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_pcie=config-1#mt7622-bananapi-bpi-r64-pcie1 ++bootconf_sata=config-1#mt7622-bananapi-bpi-r64-sata +bootdelay=0 +bootfile=openwrt-mediatek-mt7622-bananapi_bpi-r64-initramfs-recovery.itb +bootfile_fip=openwrt-mediatek-mt7622-bananapi_bpi-r64-snand-bl31-uboot.fip @@ -634,22 +652,21 @@ +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi -+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2 -+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery -+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000 -+boot_write_fip=mtd erase fip && mtd write fip $loadaddr ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x20000 && mtd write bl2 $loadaddr 0x20000 0x20000 && mtd write bl2 $loadaddr 0x40000 0x20000 && mtd write bl2 $loadaddr 0x60000 0x20000 +check_ubi=ubi part ubi || run ubi_format -+reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data -+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++reset_factory=mw $loadaddr 0x0 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ; fi +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ; fi -+_create_env=ubi create ubootenv 0x100000 dynamic 0 ; ubi create ubootenv2 0x100000 dynamic 1 ; ubi create fit 0x100000 dynamic 2 ; ubi create recovery 0x100000 dynamic 3 -+_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format -+_firstboot=setenv _firstboot ; run _switch_to_menu ; run check_ubi ; run _init_env ; run boot_first ++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic ++_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/405-dts-mt7623n-bpi-r2-fix-leds.patch b/package/boot/uboot-mediatek/patches/405-dts-mt7623n-bpi-r2-fix-leds.patch new file mode 100644 index 00000000000..2ebbba8a854 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/405-dts-mt7623n-bpi-r2-fix-leds.patch @@ -0,0 +1,25 @@ +--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +@@ -51,19 +51,19 @@ + + blue { + label = "bpi-r2:pio:blue"; +- gpios = <&gpio 241 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio 240 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + green { + label = "bpi-r2:pio:green"; +- gpios = <&gpio 240 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio 241 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + red { + label = "bpi-r2:pio:red"; +- gpios = <&gpio 239 GPIO_ACTIVE_HIGH>; ++ gpios = <&gpio 239 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/406-dts-mt7623n-bpi-r2-uart0-force-highspeed.patch b/package/boot/uboot-mediatek/patches/406-dts-mt7623n-bpi-r2-uart0-force-highspeed.patch new file mode 100644 index 00000000000..6710e3ea4ee --- /dev/null +++ b/package/boot/uboot-mediatek/patches/406-dts-mt7623n-bpi-r2-uart0-force-highspeed.patch @@ -0,0 +1,10 @@ +--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts ++++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts +@@ -245,6 +245,7 @@ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins_a>; ++ mediatek,force-highspeed; + status = "okay"; + }; + diff --git a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch index 5b52206e1c7..08aee125aa8 100644 --- a/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch +++ b/package/boot/uboot-mediatek/patches/410-add-linksys-e8450.patch @@ -1,12 +1,13 @@ --- /dev/null +++ b/configs/mt7622_linksys_e8450_defconfig -@@ -0,0 +1,135 @@ +@@ -0,0 +1,140 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7622=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_BOOTP_SEND_HOSTNAME=y @@ -16,7 +17,6 @@ +CONFIG_DEBUG_UART_CLOCK=25000000 +CONFIG_DEFAULT_DEVICE_TREE="mt7622-linksys-e8450-ubi" +CONFIG_DEBUG_UART=y -+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:512k(bl2),1280k(fip),1024k(factory),256k(reserved),-(ubi)" +CONFIG_SMBIOS_PRODUCT_NAME="" +CONFIG_AUTOBOOT_KEYED=y +CONFIG_BOOTDELAY=30 @@ -57,7 +57,7 @@ +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPART=y ++CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_PCI=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y @@ -125,12 +125,17 @@ +CONFIG_MTK_SPI_NAND=y +CONFIG_MTK_SPI_NAND_MTD=y +CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y +CONFIG_WDT_MTK=y +CONFIG_LZO=y +CONFIG_ZSTD=y +CONFIG_HEXDUMP=y +CONFIG_RANDOM_UUID=y +CONFIG_REGEX=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +CONFIG_USB=y +CONFIG_USB_HOST=y +CONFIG_USB_XHCI_HCD=y @@ -138,7 +143,7 @@ +CONFIG_USB_STORAGE=y --- /dev/null +++ b/arch/arm/dts/mt7622-linksys-e8450-ubi.dts -@@ -0,0 +1,195 @@ +@@ -0,0 +1,214 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. @@ -146,6 +151,7 @@ + */ + +/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> +#include "mt7622.dtsi" +#include "mt7622-u-boot.dtsi" + @@ -169,11 +175,13 @@ + factory { + label = "reset"; + gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; + }; + + wps { + label = "wps"; + gpios = <&gpio 102 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_WPS_BUTTON>; + }; + }; + @@ -298,11 +306,27 @@ + pinctrl-0 = <&snfi_pins>; + status = "okay"; + quad-spi; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@80000 { ++ label = "ubi"; ++ reg = <0x80000 0x7f80000>; ++ compatible = "linux,ubi"; ++ }; ++ }; +}; + +&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; ++ mediatek,force-highspeed; + status = "okay"; +}; + @@ -315,12 +339,12 @@ +ð { + status = "okay"; + mediatek,gmac-id = <0>; -+ phy-mode = "sgmii"; ++ phy-mode = "2500base-x"; + mediatek,switch = "mt7531"; + reset-gpios = <&gpio 54 GPIO_ACTIVE_HIGH>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; +}; @@ -336,18 +360,18 @@ +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1007,6 +1007,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1422,6 +1422,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7622-rfb.dtb \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ + mt7622-linksys-e8450-ubi.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ - mt8512-bm1-emmc.dtb \ + mt7981-rfb.dtb \ --- /dev/null +++ b/linksys_e8450_env -@@ -0,0 +1,57 @@ -+ethaddr_factory=mtd read spi-nand0 0x40080000 0x220000 0x20000 && env readmem -b ethaddr 0x4009fff4 0x6 ; setenv ethaddr_factory +@@ -0,0 +1,54 @@ ++ethaddr_factory=ubi read 0x40080000 factory && env readmem -b ethaddr 0x400ffff4 0x6 ; setenv ethaddr_factory +ipaddr=192.168.1.1 +serverip=192.168.1.254 +loadaddr=0x48000000 @@ -379,28 +403,26 @@ +boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever +boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off +boot_recovery=led $bootled_rec on ; run ubi_read_recovery ; bootm $loadaddr#$bootconf ; ubi remove recovery ; led $bootled_rec off -+boot_serial_write_bl2=loadx $loadaddr 115200 && run boot_write_bl2 -+boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_bl2=loadx $loadaddr 115200 && run snand_write_bl2 ++boot_serial_write_fip=loadx $loadaddr 115200 && run ubi_write_fip +boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf +boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done +boot_tftp_production=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && ubi part ubi && run ubi_write_production ubi_prepare_rootfs ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi +boot_tftp_recovery=tftpboot $loadaddr $bootfile && iminfo $loadaddr && ubi part ubi && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi -+boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run boot_write_bl2 -+boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip +boot_ubi=ubi part ubi && run boot_production ; run boot_recovery -+boot_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000 -+boot_write_fip=mtd erase fip && mtd write fip $loadaddr -+check_ubi=ubi part ubi || run ubi_format -+reset_factory=ubi part ubi ; ubi write 0x0 ubootenv 0x0 ; ubi write 0x0 ubootenv2 0x0 ; ubi remove rootfs_data -+ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++snand_write_bl2=mtd erase bl2 && mtd write spi-nand0 $loadaddr 0x0 0x20000 && mtd write spi-nand0 $loadaddr 0x20000 0x20000 && mtd write spi-nand0 $loadaddr 0x40000 0x20000 && mtd write spi-nand0 $loadaddr 0x60000 0x20000 ++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi part ubi ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data +ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi +ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs +ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery +ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip || ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 +ubi_write_production=ubi check fit && env exists replacevol && ubi remove fit ; if ubi check fit ; then else run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ; fi +ubi_write_recovery=ubi check recovery && env exists replacevol && ubi remove recovery ; if ubi check recovery ; then else run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ; fi -+_create_env=ubi create ubootenv 0x100000 dynamic ; ubi create ubootenv2 0x100000 dynamic ++_create_env=ubi create ubootenv 0x1f000 dynamic ; ubi create ubootenv2 0x1f000 dynamic +_init_env=setenv _init_env ; if ubi check ubootenv && ubi check ubootenv2 ; then else run _create_env ; fi ; setenv _create_env ; saveenv || run ubi_format ; saveenv || run ubi_format -+_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run check_ubi ; run _init_env ; run boot_first ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first +_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch index bac4a86d050..bbd05fe41f9 100644 --- a/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch +++ b/package/boot/uboot-mediatek/patches/412-add-ubnt-unifi-6-lr.patch @@ -1,12 +1,13 @@ --- /dev/null -+++ b/configs/mt7622_ubnt_unifi-6-lr_defconfig -@@ -0,0 +1,140 @@ ++++ b/configs/mt7622_ubnt_unifi-6-lr-v1_defconfig +@@ -0,0 +1,147 @@ +CONFIG_ARM=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TARGET_MT7622=y -+CONFIG_SYS_TEXT_BASE=0x41e00000 ++CONFIG_TEXT_BASE=0x41e00000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" +CONFIG_ENV_IS_IN_MTD=y @@ -63,7 +64,7 @@ +CONFIG_CMD_LINK_LOCAL=y +# CONFIG_CMD_MBR is not set +CONFIG_CMD_MTD=y -+CONFIG_CMD_MTDPART=y ++CONFIG_CMD_MTDPARTS=y +# CONFIG_CMD_PCI is not set +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_PING=y @@ -141,9 +142,314 @@ +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7622_ubnt_unifi-6-lr-v2_defconfig +@@ -0,0 +1,147 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7622=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0xc0000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_RESET_BUTTON_SETTLE_DELAY=400 ++CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr-v2_env" ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr" ++CONFIG_DEBUG_UART=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr" ++CONFIG_SYS_PROMPT="MT7622> " ++# CONFIG_LEGACY_IMAGE_FORMAT is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_EFI is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_BOOTEFI is not set ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_MTDPARTS=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++# CONFIG_CMD_UNLZ4 is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_MMC is not set ++CONFIG_DM_SERIAL=y ++CONFIG_DM_SPI=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_HUSH_PARSER=y ++# CONFIG_PARTITION_UUIDS is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_LED is not set ++# CONFIG_LZ4 is not set ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_PHYLIB_10G=y ++CONFIG_PHY_AQUANTIA=y ++CONFIG_PHY_ADDR_ENABLE=y ++CONFIG_PHY_ADDR=8 ++CONFIG_MEDIATEK_ETH=y ++CONFIG_MTD=y ++# CONFIG_MMC is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_MTK_SNFI_SPI=y ++CONFIG_MTK_SNOR=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_UNLOCK_ALL=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7622_ubnt_unifi-6-lr-v3_defconfig +@@ -0,0 +1,146 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7622=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_LOAD_ADDR=0x40080000 ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTDPARTS_DEFAULT="mtdparts=nor0:128k(bl2),640k(fip),64k(u-boot-env),256k(factory),64k(eeprom),15232k(recovery),-(firmware)" ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x4000 ++CONFIG_ENV_SIZE=0x4000 ++CONFIG_ENV_OFFSET=0xc0000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_RESET_BUTTON_SETTLE_DELAY=400 ++CONFIG_BOOTP_SEND_HOSTNAME=y ++CONFIG_DEFAULT_ENV_FILE="ubnt_unifi-6-lr_env" ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=25000000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7622-ubnt-unifi-6-lr-v3" ++CONFIG_DEBUG_UART=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_DEFAULT_FDT_FILE="mt7622-ubnt-unifi-6-lr-v3" ++CONFIG_SYS_PROMPT="MT7622> " ++# CONFIG_LEGACY_IMAGE_FORMAT is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_EFI is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_BOOTEFI is not set ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_MTDPARTS=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++# CONFIG_CMD_UNLZ4 is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_MMC is not set ++CONFIG_DM_SERIAL=y ++CONFIG_DM_SPI=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_HUSH_PARSER=y ++# CONFIG_PARTITION_UUIDS is not set ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_LED is not set ++# CONFIG_LZ4 is not set ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_PHY_REALTEK=y ++CONFIG_PHY_ADDR_ENABLE=y ++CONFIG_PHY_ADDR=0 ++CONFIG_MEDIATEK_ETH=y ++CONFIG_MTD=y ++# CONFIG_MMC is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_MTK_SNFI_SPI=y ++CONFIG_MTK_SNOR=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_SPI_FLASH=y ++CONFIG_SPI_FLASH_BAR=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_UNLOCK_ALL=y ++CONFIG_SPI_FLASH_EON=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_SST=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_USE_4K_SECTORS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" --- /dev/null +++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr.dts -@@ -0,0 +1,202 @@ +@@ -0,0 +1,193 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 MediaTek Inc. @@ -151,6 +457,7 @@ + */ + +/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> +#include "mt7622.dtsi" +#include "mt7622-u-boot.dtsi" + @@ -165,18 +472,22 @@ + tick-timer = &timer0; + }; + ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ + aliases { + spi0 = &snor; + }; + + gpio-keys { + compatible = "gpio-keys"; -+ u-boot,dm-pre-reloc; + + reset { + label = "reset"; + gpios = <&gpio 62 GPIO_ACTIVE_LOW>; -+ u-boot,dm-pre-reloc; ++ linux,code = <KEY_RESTART>; + }; + }; + @@ -282,19 +593,202 @@ + }; +}; + -+&snfi { -+ pinctrl-names = "default", "snfi"; ++&snor { ++ pinctrl-names = "default"; + pinctrl-0 = <&snor_pins>; -+ pinctrl-1 = <&snfi_pins>; + status = "okay"; + + spi-flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; ++ spi-tx-bus-width = <1>; ++ spi-rx-bus-width = <4>; + u-boot,dm-pre-reloc; + }; +}; + ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&watchdog { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&watchdog_pins>; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <ð_pins>; ++ ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ phy-handle = <&gphy>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++ ++ mdio-bus { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ gphy: ethernet-phy@8 { ++ /* Marvell AQRate AQR112W - no driver */ ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ reg = <0x8>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7622-ubnt-unifi-6-lr-v3.dts +@@ -0,0 +1,193 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2019 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> ++#include "mt7622.dtsi" ++#include "mt7622-u-boot.dtsi" ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "mt7622-ubnt-unifi-6-lr-v3"; ++ compatible = "mediatek,mt7622", "ubnt,unifi-6-lr-v3"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ aliases { ++ spi0 = &snor; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 62 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_5v: regulator-5v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-5V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&pcie { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>; ++ status = "okay"; ++ ++ pcie@0,0 { ++ status = "okay"; ++ }; ++ ++ pcie@1,0 { ++ status = "okay"; ++ }; ++}; ++ ++&pinctrl { ++ eth_pins: eth-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio", "rgmii_via_gmac2"; ++ }; ++ }; ++ ++ pcie0_pins: pcie0-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie0_pad_perst", ++ "pcie0_1_waken", ++ "pcie0_1_clkreq"; ++ }; ++ }; ++ ++ pcie1_pins: pcie1-pins { ++ mux { ++ function = "pcie"; ++ groups = "pcie1_pad_perst", ++ "pcie1_0_waken", ++ "pcie1_0_clkreq"; ++ }; ++ }; ++ ++ snfi_pins: snfi-pins { ++ mux { ++ function = "flash"; ++ groups = "snfi"; ++ }; ++ }; ++ ++ snor_pins: snor-pins { ++ mux { ++ function = "flash"; ++ groups = "spi_nor"; ++ }; ++ }; ++ ++ uart0_pins: uart0 { ++ mux { ++ function = "uart"; ++ groups = "uart0_0_tx_rx" ; ++ }; ++ }; ++ ++ watchdog_pins: watchdog-default { ++ mux { ++ function = "watchdog"; ++ groups = "watchdog"; ++ }; ++ }; ++}; ++ +&snor { + pinctrl-names = "default"; + pinctrl-0 = <&snor_pins>; @@ -310,8 +804,7 @@ +}; + +&uart0 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&uart0_pins>; ++ mediatek,force-highspeed; + status = "okay"; +}; + @@ -331,7 +824,7 @@ + phy-handle = <&gphy>; + + fixed-link { -+ speed = <1000>; ++ speed = <2500>; + full-duplex; + }; + @@ -339,23 +832,24 @@ + #address-cells = <1>; + #size-cells = <0>; + -+ gphy: ethernet-phy@8 { -+ /* Marvell AQRate AQR112W - no driver */ -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x8>; ++ gphy: ethernet-phy@0 { ++ /* RealTek RTL8211FS */ ++ compatible = "ethernet-phy-ieee802.3-c22"; ++ reg = <0x0>; + }; + }; +}; --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile -@@ -1008,6 +1008,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ +@@ -1423,6 +1423,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623a-unielec-u7623-02-emmc.dtb \ mt7622-bananapi-bpi-r64.dtb \ mt7622-linksys-e8450-ubi.dtb \ + mt7622-ubnt-unifi-6-lr.dtb \ ++ mt7622-ubnt-unifi-6-lr-v3.dtb \ mt7623n-bananapi-bpi-r2.dtb \ mt7629-rfb.dtb \ - mt8512-bm1-emmc.dtb \ + mt7981-rfb.dtb \ --- /dev/null +++ b/ubnt_unifi-6-lr_env @@ -0,0 +1,50 @@ @@ -365,10 +859,63 @@ +loadaddr=0x48000000 +bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi +bootdelay=0 -+bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-initramfs-recovery.itb -+bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-preloader.bin -+bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-bl31-uboot.fip -+bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-ubootmod-squashfs-sysupgrade.itb ++bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v1-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )[0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to flash.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to flash.[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run nor_read_production && bootm $loadaddr ++boot_recovery=run nor_read_recovery ; bootm $loadaddr ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader ++boot_nor=run boot_production ; run boot_recovery ++boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000 ++boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000 ++reset_factory=mtd erase nor0 0xc0000 0x10000 && reset ++nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size ++nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/ubnt_unifi-6-lr-v2_env +@@ -0,0 +1,50 @@ ++ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x48000000 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v2-ubootmod-squashfs-sysupgrade.itb +bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 +bootmenu_default=0 +bootmenu_delay=0 @@ -402,7 +949,60 @@ +reset_factory=mtd erase nor0 0xc0000 0x10000 && reset +nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size +nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size -+nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb $image_size / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000 ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m"--- /dev/null +--- /dev/null ++++ b/ubnt_unifi-6-lr-v3_env +@@ -0,0 +1,50 @@ ++ethaddr_factory=mtd read nor0 $loadaddr 0x110000 0x10000 && env readmem -b ethaddr $loadaddr 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x48000000 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-mt7622-ubnt_unifi-6-lr-v3-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )[0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to flash.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to flash.[0m=run boot_tftp_write_preloader ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run nor_read_production && bootm $loadaddr ++boot_recovery=run nor_read_recovery ; bootm $loadaddr ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run boot_write_fip ++boot_tftp_write_preloader=tftpboot $loadaddr $bootfile_bl2 && run boot_write_preloader ++boot_nor=run boot_production ; run boot_recovery ++boot_write_fip=mtd erase nor0 0x20000 0x80000 && mtd write nor0 $loadaddr 0x20000 0x80000 ++boot_write_preloader=mtd erase nor0 0x0 0x20000 && mtd write nor0 $loadaddr 0x0 0x20000 ++reset_factory=mtd erase nor0 0xc0000 0x10000 && reset ++nor_read_production=mtd read nor0 $loadaddr 0x1000000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x1000000 $image_size ++nor_read_recovery=mtd read nor0 $loadaddr 0x120000 0x1000 && imsz $loadaddr image_size && mtd read nor0 $loadaddr 0x120000 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x1000 ; setexpr tmp1 0x$image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb 0x$image_eb * 0x1000 +nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase nor0 0x1000000 0x$image_eb && mtd write nor0 $loadaddr 0x1000000 $filesize +nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0xee0000 && mtd erase nor0 0x120000 0x$image_eb && mtd write nor0 $loadaddr 0x120000 $filesize +_init_env=setenv _init_env ; saveenv @@ -411,15 +1011,15 @@ +_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" --- a/common/board_r.c +++ b/common/board_r.c -@@ -77,6 +77,7 @@ - #ifdef CONFIG_EFI_SETUP_EARLY +@@ -66,6 +66,7 @@ + #include <asm-generic/gpio.h> #include <efi_loader.h> - #endif + #include <relocate.h> +#include <spi_flash.h> DECLARE_GLOBAL_DATA_PTR; -@@ -410,6 +411,21 @@ static int initr_onenand(void) +@@ -397,6 +398,20 @@ static int initr_onenand(void) } #endif @@ -429,11 +1029,10 @@ +{ + struct udevice *new; + -+ spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, -+ CONFIG_SF_DEFAULT_CS, -+ CONFIG_SF_DEFAULT_SPEED, -+ CONFIG_SF_DEFAULT_MODE, -+ &new); ++spi_flash_probe_bus_cs(CONFIG_SF_DEFAULT_BUS, ++ CONFIG_SF_DEFAULT_CS, ++ &new); ++ + return 0; +} +#endif @@ -441,9 +1040,9 @@ #ifdef CONFIG_MMC static int initr_mmc(void) { -@@ -697,6 +713,9 @@ static init_fnc_t init_sequence_r[] = { - #ifdef CONFIG_CMD_ONENAND - initr_onenand, +@@ -692,6 +707,9 @@ static init_fnc_t init_sequence_r[] = { + #ifdef CONFIG_NMBM_MTD + initr_nmbm, #endif +#ifdef CONFIG_SPI_FLASH + initr_spiflash, diff --git a/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch new file mode 100644 index 00000000000..4ee87ce3d22 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/420-add-support-for-RAVPower-RP-WD009.patch @@ -0,0 +1,244 @@ +From 593db38363297247df731566c2aa307a5d795005 Mon Sep 17 00:00:00 2001 +From: David Bauer <mail@david-bauer.net> +Date: Thu, 18 Jun 2020 00:13:11 +0200 +Subject: [PATCH] add support for RAVPower RP-WD009 + +--- + arch/mips/dts/Makefile | 3 +- + arch/mips/dts/ravpower-rp-wd009.dts | 50 +++++++++++++++++++++ + arch/mips/mach-mtmips/Kconfig | 9 ++++ + board/ravpower/rp-wd009/Kconfig | 12 +++++ + board/ravpower/rp-wd009/Makefile | 3 ++ + board/ravpower/rp-wd009/board.c | 16 +++++++ + configs/ravpower-rp-wd009-ram_defconfig | 59 +++++++++++++++++++++++++ + include/configs/ravpower-rp-wd009.h | 48 ++++++++++++++++++++ + 8 files changed, 199 insertions(+), 1 deletion(-) + create mode 100644 arch/mips/dts/ravpower-rp-wd009.dts + create mode 100644 board/ravpower/rp-wd009/Kconfig + create mode 100644 board/ravpower/rp-wd009/Makefile + create mode 100644 board/ravpower/rp-wd009/board.c + create mode 100644 configs/ravpower-rp-wd009-ram_defconfig + create mode 100644 include/configs/ravpower-rp-wd009.h + +--- a/arch/mips/dts/Makefile ++++ b/arch/mips/dts/Makefile +@@ -26,6 +26,7 @@ dtb-$(CONFIG_TARGET_OCTEON_EBB7304) += m + dtb-$(CONFIG_TARGET_OCTEON_NIC23) += mrvl,octeon-nic23.dtb + dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb + dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb ++dtb-$(CONFIG_BOARD_RAVPOWER_RP_WD009) += ravpower-rp-wd009.dtb + dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb + dtb-$(CONFIG_BOARD_SFR_NB4_SER) += sfr,nb4-ser.dtb + dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb +--- /dev/null ++++ b/arch/mips/dts/ravpower-rp-wd009.dts +@@ -0,0 +1,50 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2018 Stefan Roese <sr@denx.de> ++ */ ++ ++/dts-v1/; ++ ++#include "mt7628a.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ compatible = "ravpower,rp-wd009", "ralink,mt7628a-soc"; ++ model = "RAVPower RP-WD009"; ++ ++ aliases { ++ serial0 = &uart0; ++ spi0 = &spi0; ++ }; ++ ++ memory@0 { ++ device_type = "memory"; ++ reg = <0x0 0x4000000>; ++ }; ++ ++ chosen { ++ stdout-path = "serial0:115200n8"; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&spi0 { ++ status = "okay"; ++ num-cs = <2>; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ spi-max-frequency = <40000000>; ++ reg = <0>; ++ }; ++}; ++ ++ð { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&ephy_router_mode>; ++}; +--- /dev/null ++++ b/board/ravpower/rp-wd009/Kconfig +@@ -0,0 +1,12 @@ ++if BOARD_RAVPOWER_RP_WD009 ++ ++config SYS_BOARD ++ default "rp-wd009" ++ ++config SYS_VENDOR ++ default "ravpower" ++ ++config SYS_CONFIG_NAME ++ default "ravpower-rp-wd009" ++ ++endif +--- /dev/null ++++ b/board/ravpower/rp-wd009/Makefile +@@ -0,0 +1,3 @@ ++# SPDX-License-Identifier: GPL-2.0+ ++ ++obj-y += board.o +--- /dev/null ++++ b/board/ravpower/rp-wd009/board.c +@@ -0,0 +1,16 @@ ++// SPDX-License-Identifier: GPL-2.0+ ++/* ++ * Copyright (C) 2018 Stefan Roese <sr@denx.de> ++ */ ++ ++ ++int board_early_init_f(void) ++{ ++ return 0; ++} ++ ++ ++int board_late_init(void) ++{ ++ return 0; ++} +--- /dev/null ++++ b/configs/ravpower-rp-wd009-ram_defconfig +@@ -0,0 +1,71 @@ ++CONFIG_MIPS=y ++CONFIG_SYS_LOAD_ADDR=0x80010000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_MEMTEST_START=0x80100000 ++CONFIG_SYS_MEMTEST_END=0x80400000 ++CONFIG_ARCH_MTMIPS=y ++CONFIG_SOC_MT7628=y ++CONFIG_MIPS_BOOT_FDT=y ++CONFIG_LEGACY_IMAGE_FORMAT=y ++CONFIG_OF_STDOUT_VIA_ALIAS=y ++CONFIG_USE_BOOTCOMMAND=y ++CONFIG_BOOTCOMMAND="sf probe && mtd read firmware 82000000 && bootm 82000000" ++CONFIG_USE_PREBOOT=y ++CONFIG_SYS_CONSOLE_INFO_QUIET=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_BOARD_RAVPOWER_RP_WD009=y ++CONFIG_SYS_MIPS_TIMER_FREQ=290000000 ++CONFIG_SYS_BOOTPARAMS_LEN=0x20000 ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_LICENSE=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_XIMG is not set ++CONFIG_CMD_MEMINFO=y ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_LOADS is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_SPI=y ++CONFIG_CMD_WDT=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_TIME=y ++CONFIG_CMD_UUID=y ++CONFIG_CMD_MTDPARTS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_MTDIDS_DEFAULT="nor0=spi0.0" ++CONFIG_MTDPARTS_DEFAULT="spi0.0:192k(factory-uboot),64k(config),64k(factory),1536k(loader),64k(params),64k(user_backup),64k(user),14272k(firmware),64k(mode)" ++CONFIG_DEFAULT_DEVICE_TREE="ravpower-rp-wd009" ++CONFIG_NET_RANDOM_ETHADDR=y ++# CONFIG_DM_DEVICE_REMOVE is not set ++CONFIG_HAVE_BLOCK_DEVICE=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_SPI_FLASH_GIGADEVICE=y ++CONFIG_SPI_FLASH_MACRONIX=y ++CONFIG_SPI_FLASH_SPANSION=y ++CONFIG_SPI_FLASH_STMICRO=y ++CONFIG_SPI_FLASH_WINBOND=y ++CONFIG_SPI_FLASH_XMC=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MTD_UBI_BEB_LIMIT=22 ++CONFIG_MT7628_ETH=y ++CONFIG_PHY=y ++CONFIG_SPI=y ++CONFIG_MT7621_SPI=y ++CONFIG_SYSRESET_SYSCON=y ++CONFIG_WDT=y ++CONFIG_WDT_MT7621=y ++CONFIG_LZMA=y ++CONFIG_BAUDRATE=57600 ++CONFIG_SYS_MAXARGS=64 ++CONFIG_SYS_CBSIZE=512 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/include/configs/ravpower-rp-wd009.h +@@ -0,0 +1,17 @@ ++/* SPDX-License-Identifier: GPL-2.0+ */ ++/* ++ * Copyright (C) 2018 Stefan Roese <sr@denx.de> ++ */ ++ ++#ifndef __CONFIG_RAVPOWER_RP_WD009_H ++#define __CONFIG_RAVPOWER_RP_WD009_H ++ ++/* RAM */ ++#define CFG_SYS_SDRAM_BASE 0x80000000 ++ ++#define CFG_SYS_INIT_SP_OFFSET 0x400000 ++ ++/* UART */ ++#define CFG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, \ ++ 230400, 460800, 921600 } ++#endif /* __CONFIG_RAVPOWER_RP_WD009_H */ +--- a/arch/mips/mach-mtmips/mt7628/Kconfig ++++ b/arch/mips/mach-mtmips/mt7628/Kconfig +@@ -27,6 +27,14 @@ config BOARD_MT7628_RFB + SPI-NOR flash, 1 built-in switch with 5 ports, 1 UART, 1 USB host, + 1 SDXC, 1 PCIe socket and JTAG pins. + ++config BOARD_RAVPOWER_RP_WD009 ++ bool "RAVPower RP-WD009" ++ depends on SOC_MT7628 ++ select BOARD_LATE_INIT ++ select SUPPORTS_BOOT_RAM ++ help ++ RAVPower RP-WD009 ++ + config BOARD_VOCORE2 + bool "VoCore2" + select SPL_SERIAL +@@ -53,6 +61,7 @@ config SYS_CONFIG_NAME + default "mt7628" if BOARD_MT7628_RFB + + source "board/gardena/smart-gateway-mt7688/Kconfig" ++source "board/ravpower/rp-wd009/Kconfig" + source "board/seeed/linkit-smart-7688/Kconfig" + source "board/vocore/vocore2/Kconfig" + diff --git a/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch new file mode 100644 index 00000000000..b9b241a51d4 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/421-zbtlink_zbt-wg3526-16m.patch @@ -0,0 +1,314 @@ +--- /dev/null ++++ b/configs/mt7621_zbtlink_zbt-wg3526-16m_defconfig +@@ -0,0 +1,138 @@ ++CONFIG_MIPS=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_SYS_MALLOC_LEN=0x100000 ++CONFIG_SPL_LIBCOMMON_SUPPORT=y ++CONFIG_SPL_LIBGENERIC_SUPPORT=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x1000 ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="nor0" ++CONFIG_ENV_SIZE_REDUND=0x10000 ++CONFIG_ENV_SIZE=0x10000 ++CONFIG_ENV_OFFSET=0x30000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_RESET_BUTTON_SETTLE_DELAY=400 ++CONFIG_BOOTP_SEND_HOSTNAME=y ++# CONFIG_BOOTSTD is not set ++CONFIG_DEFAULT_ENV_FILE="zbtlink_zbt-wg3526-16m_env" ++CONFIG_DEFAULT_DEVICE_TREE="zbtlink,zbt-wg3526" ++CONFIG_SPL_BSS_MAX_SIZE=0x80000 ++CONFIG_SPL_BSS_START_ADDR=0x80140000 ++CONFIG_SPL_SERIAL=y ++CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 ++CONFIG_SPL=y ++CONFIG_DEBUG_UART_BASE=0xbe000c00 ++CONFIG_DEBUG_UART_CLOCK=50000000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_SYS_LOAD_ADDR=0x83000000 ++CONFIG_SYS_MIPS_TIMER_FREQ=440000000 ++CONFIG_ARCH_MTMIPS=y ++CONFIG_SOC_MT7621=y ++# CONFIG_MIPS_CACHE_SETUP is not set ++# CONFIG_MIPS_CACHE_DISABLE is not set ++CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y ++CONFIG_MIPS_BOOT_FDT=y ++CONFIG_DEBUG_UART=y ++CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++# CONFIG_FIT_ENABLE_SHA256_SUPPORT is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_LOGLEVEL=6 ++# CONFIG_LOG is not set ++# CONFIG_SYS_LONGHELP is not set ++# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set ++CONFIG_SYS_CONSOLE_INFO_QUIET=y ++CONFIG_SPL_SYS_MALLOC_SIMPLE=y ++CONFIG_SPL_NOR_SUPPORT=y ++CONFIG_TPL=y ++# CONFIG_TPL_FRAMEWORK is not set ++CONFIG_LEGACY_IMAGE_FORMAT=y ++# CONFIG_BOOTM_NETBSD is not set ++# CONFIG_BOOTM_PLAN9 is not set ++# CONFIG_BOOTM_RTEMS is not set ++# CONFIG_BOOTM_VXWORKS is not set ++# CONFIG_EFI is not set ++# CONFIG_EFI_LOADER is not set ++CONFIG_CMD_BOOTMENU=y ++# CONFIG_CMD_BOOTEFI is not set ++# CONFIG_CMD_BOOTD is not set ++# CONFIG_CMD_BOOTP is not set ++CONFIG_CMD_BOOTM=y ++# CONFIG_CMD_BOOTDEV is not set ++# CONFIG_CMD_BOOTFLOW is not set ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_ECHO=y ++# CONFIG_CMD_ELF is not set ++# CONFIG_CMD_BOOTEFI_BOOTMGR is not set ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_MTDPART=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_TFTPBOOT=y ++# CONFIG_CMD_UNLZ4 is not set ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_DOS_PARTITION=y ++# CONFIG_SPL_DOS_PARTITION is not set ++# CONFIG_ISO_PARTITION is not set ++# CONFIG_EFI_PARTITION is not set ++# CONFIG_SPL_EFI_PARTITION is not set ++CONFIG_PARTITION_TYPE_GUID=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++# CONFIG_NET_RANDOM_ETHADDR is not set ++# CONFIG_I2C is not set ++# CONFIG_INPUT is not set ++CONFIG_MMC=y ++# CONFIG_MMC_QUIRKS is not set ++# CONFIG_MMC_HW_PARTITIONING is not set ++CONFIG_MMC_MTK=y ++CONFIG_MTD=y ++CONFIG_DM_MTD=y ++CONFIG_SF_DEFAULT_SPEED=20000000 ++# CONFIG_SPI_FLASH_BAR is not set ++# CONFIG_SPI_FLASH_EON is not set ++# CONFIG_SPI_FLASH_GIGADEVICE is not set ++# CONFIG_SPI_FLASH_ISSI is not set ++# CONFIG_SPI_FLASH_MACRONIX is not set ++# CONFIG_SPI_FLASH_SPANSION is not set ++# CONFIG_SPI_FLASH_STMICRO is not set ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_XMC is not set ++# CONFIG_SPI_FLASH_XTX is not set ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_DEBUG_UART_SHIFT=2 ++CONFIG_SPI=y ++CONFIG_MT7621_SPI=y ++CONFIG_SYSRESET=y ++CONFIG_SYSRESET_RESETCTL=y ++# CONFIG_SYS_XTRACE is not set ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_WDT=y ++CONFIG_WDT_MT7621=y ++# CONFIG_BINMAN_FDT is not set ++CONFIG_LZMA=y ++CONFIG_SPL_LZMA=y ++# CONFIG_GZIP is not set +--- /dev/null ++++ b/zbtlink_zbt-wg3526-16m_env +@@ -0,0 +1,36 @@ ++ethaddr_factory=mtd read factory $loadaddr 0x0 0x10000 ; setexpr macoffs $loadaddr + 0xe000 ; env readmem -b ethaddr $macoffs 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x83000000 ++bootcmd=run boot_nor ++bootdelay=0 ++bootfile=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-initramfs-kernel.bin ++bootfile_uboot=u-boot-mt7621.bin ++bootfile_upg=openwrt-ramips-mt7621-zbtlink_zbt-wg3526-16m-squashfs-sysupgrade.bin ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) )[0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot system from flash.=run boot_nor ; run bootmenu_confirm_return ++bootmenu_3=Load system via TFTP then write to flash.=run boot_tftp_sysupgrade ; run bootmenu_confirm_return ++bootmenu_4=[31mLoad U-Boot via TFTP then write to flash.[0m=run boot_tftp_write_uboot ; run bootmenu_confirm_return ++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset ++bootmenu_6=Reboot.=reset ++boot_first=if button reset ; then run boot_tftp ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_tftp_forever ++boot_nor=bootm 0x1fc50000 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr ++boot_tftp_forever=while true ; do run boot_tftp ; sleep 1 ; done ++boot_tftp_sysupgrade=tftpboot $loadaddr $bootfile_upg && iminfo $loadaddr && run nor_write_production ++boot_tftp_write_uboot=tftpboot $loadaddr $bootfile_uboot && run nor_write_uboot ++reset_factory=mtd erase u-boot-env 0x0 0x10000 && reset ++nor_pad_size=setexpr image_eb $filesize / 0x1000 ; setexpr tmp1 image_size % 0x1000 ; test 0x$tmp1 -gt 0 && setexpr image_eb $image_eb + 1 ; setexpr image_eb $image_eb * 0x1000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0xfb0000 && mtd erase firmware 0x0 0x$image_eb && mtd write firmware $loadaddr 0x0 $filesize ++nor_write_uboot=mtd erase u-boot 0x0 0x30000 && mtd write u-boot $loadaddr 0x0 0x30000 ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run ethaddr_factory ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/arch/mips/dts/zbtlink,zbt-wg3526.dts +@@ -0,0 +1,131 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2022 MediaTek Inc. All rights reserved. ++ * ++ * Author: Weijie Gao <weijie.gao@mediatek.com> ++ */ ++ ++/dts-v1/; ++ ++#include "mt7621.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ compatible = "zbtlink,zbt-wg3526", "mediatek,mt7621-rfb", "mediatek,mt7621-soc"; ++ model = "Zbtlink WG3526"; ++ ++ aliases { ++ ethernet0 = ð ++ serial0 = &uart0; ++ spi0 = &spi; ++ }; ++ ++ chosen { ++ stdout-path = &uart0; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 18 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status: status { ++ label = "green:status"; ++ gpios = <&gpio 24 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&pinctrl { ++ state_default: pin_state { ++ gpios { ++ groups = "i2c", "uart3", "pcie reset"; ++ function = "gpio"; ++ }; ++ ++ wdt { ++ groups = "wdt"; ++ function = "wdt rst"; ++ }; ++ ++ jtag { ++ groups = "jtag"; ++ function = "jtag"; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&gpio { ++ status = "okay"; ++}; ++ ++&spi { ++ status = "okay"; ++ num-cs = <2>; ++ ++ spi-flash@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "jedec,spi-nor"; ++ spi-max-frequency = <25000000>; ++ reg = <0>; ++ ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "u-boot"; ++ reg = <0x0 0x30000>; ++ }; ++ ++ partition@30000 { ++ label = "u-boot-env"; ++ reg = <0x30000 0x10000>; ++ }; ++ ++ factory: partition@40000 { ++ label = "factory"; ++ reg = <0x40000 0x10000>; ++ read-only; ++ }; ++ ++ firmware: partition@50000 { ++ compatible = "denx,uimage"; ++ label = "firmware"; ++ reg = <0x50000 0xfb0000>; ++ }; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++}; ++ ++&mmc { ++ cap-sd-highspeed; ++ ++ status = "okay"; ++}; ++ ++&ssusb { ++ status = "okay"; ++}; ++ ++&u3phy { ++ status = "okay"; ++}; diff --git a/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch new file mode 100644 index 00000000000..398621537a3 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/430-add-bpi-r3.patch @@ -0,0 +1,1113 @@ +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-emmc_defconfig +@@ -0,0 +1,197 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-nor_defconfig +@@ -0,0 +1,193 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_nor_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MTD=y ++CONFIG_ENV_MTD_NAME="u-boot-env" ++CONFIG_ENV_OFFSET=0x0 ++CONFIG_ENV_OFFSET_REDUND=0x20000 ++CONFIG_ENV_SIZE=0x20000 ++CONFIG_ENV_SIZE_REDUND=0x20000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++#CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-sd_defconfig +@@ -0,0 +1,197 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-sd" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_sdmmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-sd.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-snand_defconfig +@@ -0,0 +1,198 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3_snand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++#CONFIG_DM_SPI_FLASH=y ++#CONFIG_SPI_FLASH_MTD=y ++#CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++#CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/bananapi_bpi-r3_sdmmc_env +@@ -0,0 +1,81 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3 ++bootconf_base=config-mt7986a-bananapi-bpi-r3 ++bootconf_nor=mt7986a-bananapi-bpi-r3-nor ++bootconf_nand=mt7986a-bananapi-bpi-r3-nand ++bootconf_sd=mt7986a-bananapi-bpi-r3-sd ++bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SD card][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mInstall bootloader, recovery and production to NOR.[0m=if sf probe ; then run nor_init ; else echo "NOR not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_7=[31mInstall bootloader, recovery and production to NAND.[0m=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_update_conf=if nand info ; then setenv bootconf $bootconf_base#$bootconf_sd#$bootconf_nand ; else if sf probe ; then setenv bootconf $bootconf_base#$bootconf_sd#$bootconf_nor ; else setenv bootconf $bootconf_base#$bootconf_sd ; fi ; fi ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run boot_update_conf ; run sdmmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run boot_update_conf ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_sdmmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400 ++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_nor_bl2=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x2800 && mmc read $loadaddr $offset 0x400 ++sdmmc_read_nor_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3000 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000 ++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000 ++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++nor_write_fip=mtd erase fip && mtd write fip $loadaddr ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000 ++nor_erase_env=mtd erase u-boot-env ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb ++nor_init=run nor_init_bl && run nor_init_openwrt ++nor_init_bl=run sdmmc_read_nor_bl2 && run nor_write_bl2 && run sdmmc_read_nor_fip && run nor_write_fip && run nor_erase_env ++nor_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run nor_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run nor_write_production ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ++ubi_init=run ubi_format && run ubi_init_bl && run ubi_init_openwrt && run ubi_init_emmc_install ++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production ++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip ++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r3_nor_env +@@ -0,0 +1,60 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_nor ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3 ++bootconf_base=config-mt7986a-bananapi-bpi-r3 ++bootconf_nor=mt7986a-bananapi-bpi-r3-nor ++bootconf_nand=mt7986a-bananapi-bpi-r3-nand ++bootconf_sd=mt7986a-bananapi-bpi-r3-sd ++bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-nor-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-nor-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NOR][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from flash.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from flash.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to flash.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to flash.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to flash.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run nor_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run nor_read_recovery ; bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_serial_write_fip=loadx $loadaddr 115200 && run boot_write_fip ++boot_serial_write_preloader=loadx $loadaddr 115200 && run boot_write_preloader ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run nor_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run nor_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run nor_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run nor_write_bl2 ++boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nor#$bootconf_sd ; fi ++boot_nor=run boot_production ; run boot_recovery ++reset_factory=mtd erase u-boot-env ++nor_write_fip=mtd erase fip && mtd write fip $loadaddr ++nor_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++nor_read_production=mtd read fit $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read fit $loadaddr 0x0 $image_size ++nor_read_recovery=mtd read recovery $loadaddr 0x0 0x20000 && imsz $loadaddr image_size && mtd read recovery $loadaddr 0x0 $image_size ++nor_pad_size=imsz $loadaddr image_size ; setexpr image_eb 0x$image_size / 0x10000 ; setexpr tmp1 0x$image_size % 0x10000 ; test 0x$tmp1 -gt 0 && setexpr image_eb 0x$image_eb + 1 ; setexpr image_eb $image_eb * 0x10000 ++nor_write_production=run nor_pad_size ; test 0x$image_eb -le 0x3000000 && mtd erase fit && mtd write fit $loadaddr 0x0 $image_eb ++nor_write_recovery=run nor_pad_size ; test 0x$image_eb -le 0x900000 && mtd erase recovery 0x0 0x$image_eb && mtd write recovery $loadaddr 0x0 $image_eb ++_init_env=setenv _init_env ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r3_snand_env +@@ -0,0 +1,73 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 ++bootconf=config-mt7986a-bananapi-bpi-r3 ++bootconf_base=config-mt7986a-bananapi-bpi-r3 ++bootconf_nor=mt7986a-bananapi-bpi-r3-nor ++bootconf_nand=mt7986a-bananapi-bpi-r3-nand ++bootconf_sd=mt7986a-bananapi-bpi-r3-sd ++bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-snand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-snand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NAND][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=[31mInstall bootloader, recovery and production to eMMC.[0m=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++boot_update_conf=if mmc partconf 0 ; then setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_emmc ; else setenv bootconf $bootconf_base#$bootconf_nand#$bootconf_sd ; fi ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ++snand_write_bl2=mtd erase bl2 0x0 0x100000 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv ++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr ++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r3_emmc_env +@@ -0,0 +1,61 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3 ++bootconf_base=config-mt7986a-bananapi-bpi-r3 ++bootconf_nor=mt7986a-bananapi-bpi-r3-nor ++bootconf_nand=mt7986a-bananapi-bpi-r3-nand ++bootconf_sd=mt7986a-bananapi-bpi-r3-sd ++bootconf_emmc=mt7986a-bananapi-bpi-r3-emmc ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run boot_update_conf ; led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=run boot_update_conf ; led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=run boot_update_conf ; tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=run boot_update_conf ; tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=run boot_update_conf ; tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_update_conf=if nand info ; then setenv bootconf $bootconf_base#$bootconf_emmc#$bootconf_nand ; else setenv bootconf $bootconf_base#$bootconf_emmc#$bootconf_nor ; fi ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- a/arch/arm/dts/mt7986a-bpi-r3-sd.dts ++++ b/arch/arm/dts/mt7986a-bpi-r3-sd.dts +@@ -235,22 +235,13 @@ + + partition@0 { + label = "bl2"; +- reg = <0x0 0x80000>; ++ reg = <0x0 0x200000>; + }; + +- partition@80000 { +- label = "factory"; +- reg = <0x80000 0x300000>; +- }; +- +- partition@380000 { +- label = "fip"; +- reg = <0x380000 0x200000>; +- }; +- +- partition@580000 { ++ partition@200000 { + label = "ubi"; +- reg = <0x580000 0x7a80000>; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; + }; + }; + }; diff --git a/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch new file mode 100644 index 00000000000..88b2c63632d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/431-add-xiaomi_redmi-ax6000.patch @@ -0,0 +1,404 @@ +--- /dev/null ++++ b/configs/mt7986_xiaomi_redmi-ax6000_defconfig +@@ -0,0 +1,179 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-xiaomi_redmi-ax6000" ++CONFIG_DEFAULT_ENV_FILE="xiaomi_redmi-ax6000_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-xiaomi_redmi-ax6000.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++# CONFIG_LED is not set ++# CONFIG_LED_BLINK is not set ++# CONFIG_LED_GPIO is not set ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++# CONFIG_CMD_EXT4 is not set ++# CONFIG_CMD_FAT is not set ++CONFIG_CMD_FDT=y ++# CONFIG_CMD_FS_GENERIC is not set ++# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_GPIO=y ++# CONFIG_CMD_GPT is not set ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++# CONFIG_CMD_LED is not set ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++# CONFIG_CMD_PWM is not set ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++# CONFIG_CMD_USB is not set ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_USB is not set ++# CONFIG_DM_PWM is not set ++# CONFIG_PWM_MTK is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++# CONFIG_DM_SCSI is not set ++# CONFIG_AHCI is not set ++CONFIG_PHY=y ++# CONFIG_PHY_MTK_TPHY is not set ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++# CONFIG_PCI is not set ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_DM_PCI is not set ++# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++# CONFIG_PINCTRL_MT7622 is not set ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++# CONFIG_I2C is not set ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++# CONFIG_USB is not set ++# CONFIG_USB_HOST is not set ++# CONFIG_USB_XHCI_HCD is not set ++# CONFIG_USB_XHCI_MTK is not set ++# CONFIG_USB_STORAGE is not set ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7986a-xiaomi_redmi-ax6000.dts +@@ -0,0 +1,161 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Xiaomi Redmi AX6000"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ factory { ++ label = "reset"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ mesh { ++ label = "mesh"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_WPS_BUTTON>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "nvram"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "bdata"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@600000 { ++ label = "ubi"; ++ reg = <0x580000 0x7a80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/xiaomi_redmi-ax6000_env +@@ -0,0 +1,55 @@ ++ethaddr_factory=mtd read factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x40080004 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=console=ttyS0,115200n8 console_msg_format=syslog ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-xiaomi_redmi-router-ax6000-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run ubi_read_production && bootm $loadaddr#$bootconf ++boot_recovery=run ubi_read_recovery && bootm $loadaddr#$bootconf ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_fit=fit ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch new file mode 100644 index 00000000000..365f280947d --- /dev/null +++ b/package/boot/uboot-mediatek/patches/432-add-tplink-xdr608x.patch @@ -0,0 +1,934 @@ +--- /dev/null ++++ b/configs/mt7986_tplink_tl-xdr4288_defconfig +@@ -0,0 +1,182 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" ++CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr4288_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986_tplink_tl-xdr6086_defconfig +@@ -0,0 +1,182 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" ++CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr6086_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986_tplink_tl-xdr6088_defconfig +@@ -0,0 +1,182 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-tplink-tl-xdr608x" ++CONFIG_DEFAULT_ENV_FILE="tplink_tl-xdr6088_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-tplink-tl-xdr608x.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7986a-tplink-tl-xdr608x.dts +@@ -0,0 +1,196 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2021 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "TP-Link TL-XDR608x"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ turbo { ++ label = "turbo"; ++ linux,code = <BTN_1>; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ status_green { ++ label = "green:status"; ++ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ turbo { ++ label = "green:turbo"; ++ gpios = <&gpio 12 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@1 { ++ compatible = "spi-nand"; ++ reg = <1>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x80000>; ++ }; ++ ++ partition@100000 { ++ label = "config"; ++ reg = <0x100000 0x60000>; ++ }; ++ ++ partition@160000 { ++ label = "factory"; ++ reg = <0x160000 0x60000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7800000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/tplink_tl-xdr4288_env +@@ -0,0 +1,57 @@ ++ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-tplink_tl-xdr4288-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-tplink_tl-xdr4288-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-tplink_tl-xdr4288-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-tplink_tl-xdr4288-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/tplink_tl-xdr6086_env +@@ -0,0 +1,57 @@ ++ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-tplink_tl-xdr6086-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-tplink_tl-xdr6086-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-tplink_tl-xdr6086-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-tplink_tl-xdr6086-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/tplink_tl-xdr6088_env +@@ -0,0 +1,57 @@ ++ethaddr_factory=mtd read config 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008001c 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-tplink_tl-xdr6088-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-tplink_tl-xdr6088-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-tplink_tl-xdr6088-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-tplink_tl-xdr6088-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch new file mode 100644 index 00000000000..4f98c95893b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/433-add-qihoo_360t7.patch @@ -0,0 +1,425 @@ +--- /dev/null ++++ b/configs/mt7981_qihoo-360t7_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_qihoo-360t7" ++CONFIG_DEFAULT_ENV_FILE="qihoo-360t7_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_qihoo-360t7.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_qihoo-360t7.dts +@@ -0,0 +1,185 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Qihoo 360T7"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 3 GPIO_ACTIVE_LOW>; ++ }; ++ ++ status_green { ++ label = "green:status"; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "orig-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@160000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x6c00000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/qihoo-360t7_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-qihoo_360t7-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-qihoo_360t7-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-qihoo_360t7-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-qihoo_360t7-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch new file mode 100644 index 00000000000..2bd1afe7a8f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/434-add-xiaomi_mi-router-wr30u.patch @@ -0,0 +1,461 @@ +--- /dev/null ++++ b/configs/mt7981_xiaomi_mi-router-wr30u_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-wr30u" ++CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-wr30u_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-wr30u.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_xiaomi_mi-router-wr30u.dts +@@ -0,0 +1,221 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Xiaomi Router WR30U"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ config { ++ blink_led = "yellow:network"; ++ system_led = "yellow:system"; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ ++ mesh { ++ label = "mesh"; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ linux,code = <BTN_9>; ++ linux,input-type = <EV_SW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_system_blue { ++ label = "blue:system"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_system_yellow { ++ label = "yellow:system"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_network_blue { ++ label = "blue:network"; ++ gpios = <&gpio 11 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_network_yellow { ++ label = "yellow:network"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "sgmii"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "Nvram"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "Bdata"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "crash"; ++ reg = <0x580000 0x40000>; ++ }; ++ ++ partition@5c0000 { ++ label = "crash_log"; ++ reg = <0x5c0000 0x40000>; ++ }; ++ ++ partition@600000 { ++ label = "ubi"; ++ reg = <0x600000 0x7000000>; ++ }; ++ ++ partition@7600000 { ++ label = "KF"; ++ reg = <0x7600000 0x40000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/xiaomi_mi-router-wr30u_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-xiaomi_mi-router-wr30u-ubootmod-squashfs-sysupgrade.itb ++bootled_pwr=yellow:system ++bootled_rec=yellow:network ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch new file mode 100644 index 00000000000..d5a149b903b --- /dev/null +++ b/package/boot/uboot-mediatek/patches/435-add-h3c_magic-nx30-pro.patch @@ -0,0 +1,445 @@ +--- /dev/null ++++ b/configs/mt7981_h3c_magic-nx30-pro_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_h3c_magic-nx30-pro" ++CONFIG_DEFAULT_ENV_FILE="h3c_magic-nx30-pro_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_h3c_magic-nx30-pro.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_h3c_magic-nx30-pro.dts +@@ -0,0 +1,205 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "H3C Magic NX30 Pro"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ wps { ++ label = "wps"; ++ linux,code = <KEY_WPS_BUTTON>; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 4 GPIO_ACTIVE_LOW>; ++ }; ++ ++ status_green { ++ label = "green:status"; ++ gpios = <&gpio 5 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0000000 0x0100000>; ++ }; ++ ++ partition@100000 { ++ label = "orig-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x0180000 0x0200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x0380000 0x0200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x0580000 0x4000000>; ++ }; ++ ++ partition@4580000 { ++ label = "pdt_data"; ++ reg = <0x4580000 0x0600000>; ++ }; ++ ++ partition@4b80000 { ++ label = "pdt_data_1"; ++ reg = <0x4b80000 0x0600000>; ++ }; ++ ++ partition@5180000 { ++ label = "exp"; ++ reg = <0x5180000 0x0100000>; ++ }; ++ ++ partition@5280000 { ++ label = "plugin"; ++ reg = <0x5280000 0x2580000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/h3c_magic-nx30-pro_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-h3c_magic-nx30-pro-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-h3c_magic-nx30-pro-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-h3c_magic-nx30-pro-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-h3c_magic-nx30-pro-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch new file mode 100644 index 00000000000..e0a059eb7bd --- /dev/null +++ b/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch @@ -0,0 +1,274 @@ +--- /dev/null ++++ b/arch/arm/dts/mt7986a-glinet-gl-mt6000.dts +@@ -0,0 +1,135 @@ ++// SPDX-License-Identifier: GPL-2.0 ++ ++/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> ++#include <dt-bindings/gpio/gpio.h> ++ ++#include "mt7986.dtsi" ++ ++/ { ++ model = "GL.iNet GL-MT6000"; ++ compatible = "glinet,gl-mt6000", "mediatek,mt7986-emmc-rfb", "mediatek,mt7986"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "reset"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_blue: green { ++ label = "blue:status"; ++ gpios = <&gpio 28 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_status_white: blue { ++ label = "white:status"; ++ gpios = <&gpio 27 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&wmcpu_emi { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/configs/mt7986a_glinet_gl-mt6000_defconfig +@@ -0,0 +1,105 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x80000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000" ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++CONFIG_AHCI=y ++CONFIG_FIT=y ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-glinet-gl-mt6000.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="glinet_gl-mt6000_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_USB=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_HEXDUMP=y ++CONFIG_LMB_MAX_REGIONS=64 +--- /dev/null ++++ b/glinet_gl-mt6000_env +@@ -0,0 +1,25 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++bootdelay=3 ++bootfile_bl2=openwrt-mediatek-filogic-glinet_gl-mt6000-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-glinet_gl-mt6000-bl31-uboot.fip ++bootfile_firmware=openwrt-mediatek-filogic-glinet_gl-mt6000-squashfs-factory.bin ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_title= *** U-Boot Boot Menu for GL-iNet GL-MT6000 *** ++bootmenu_0=Startup system (Default).=run boot_system ++bootmenu_1=Load Firmware via TFTP then write to eMMC.=run boot_tftp_firmware ; run bootmenu_confirm_return ++bootmenu_2=Load BL31+U-Boot FIP via TFTP then write to eMMC.=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_3=Load BL2 preloader via TFTP then write to eMMC.=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_4=Reboot.=reset ++bootmenu_5=Reset all settings to factory defaults.=run reset_factory ; reset ++filesize_to_blk=setexpr cnt $filesize + 0x1ff && setexpr cnt $cnt / 0x200 ++mmc_read_kernel=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr $part_addr $image_size ++boot_system=part start mmc 0 kernel part_addr && part size mmc 0 kernel part_size && run mmc_read_kernel && bootm ++boot_tftp_firmware=tftpboot $loadaddr $bootfile_firmware && run emmc_write_firmware ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++emmc_write_firmware=part start mmc 0 kernel part_addr && run filesize_to_blk && mmc write $loadaddr $part_addr $cnt ++emmc_write_bl2=run filesize_to_blk && test 0x$cnt -le 0x800 && mmc partconf 0 1 1 1 && && mmc write $loadaddr 0x0 0x800 ; mmc partconf 0 1 1 0 ++emmc_write_fip=part start mmc 0 fip part_addr && part size mmc 0 fip part_size && run filesize_to_blk && test 0x$cnt -le 0x$part_size && mmc write $loadaddr $part_addr $cnt ++reset_factory=eraseenv && reset diff --git a/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch new file mode 100644 index 00000000000..26e0e30a996 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/437-add-cmcc_rax3000m.patch @@ -0,0 +1,697 @@ +--- /dev/null ++++ b/configs/mt7981_cmcc_rax3000m-emmc_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-emmc" ++CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_CMD_SF=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7981_cmcc_rax3000m-nand_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981-cmcc-rax3000m-nand" ++CONFIG_DEFAULT_ENV_FILE="cmcc_rax3000m-nand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981-cmcc-rax3000m-nand.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981-cmcc-rax3000m.dtsi +@@ -0,0 +1,85 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "CMCC RAX3000M"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ button-reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button-mesh { ++ label = "mesh"; ++ linux,code = <BTN_9>; ++ linux,input-type = <EV_SW>; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "green:status"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-1 { ++ label = "blue:status"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led-2 { ++ label = "red:status"; ++ gpios = <&gpio 35 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7981-cmcc-rax3000m-emmc.dts +@@ -0,0 +1,53 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/dts-v1/; ++#include "mt7981-cmcc-rax3000m.dtsi" ++ ++/ { ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ max-frequency = <26000000>; ++ bus-width = <8>; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ conf-cmd-dat { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO", ++ "SPI0_CS", "SPI0_HOLD", "SPI0_WP", ++ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO"; ++ input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ conf-clk { ++ pins = "SPI1_CS"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ conf-rst { ++ pins = "PWM0"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7981-cmcc-rax3000m-nand.dts +@@ -0,0 +1,77 @@ ++// SPDX-License-Identifier: GPL-2.0-only ++ ++/dts-v1/; ++#include "mt7981-cmcc-rax3000m.dtsi" ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "orig-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@160000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7200000>; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/cmcc_rax3000m-emmc_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/mmcblk0p65 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-1#mt7981b-cmcc-rax3000m-emmc ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb ++bootled_pwr=red:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/cmcc_rax3000m-nand_env +@@ -0,0 +1,56 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootconf=config-1#mt7981b-cmcc-rax3000m-nand ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-cmcc_rax3000m-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-cmcc_rax3000m-nand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-cmcc_rax3000m-nand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-cmcc_rax3000m-squashfs-sysupgrade.itb ++bootled_pwr=red:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NAND][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch new file mode 100644 index 00000000000..639cae174e7 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/438-add-jcg_q30-pro.patch @@ -0,0 +1,420 @@ +--- /dev/null ++++ b/configs/mt7981_jcg_q30-pro_defconfig +@@ -0,0 +1,175 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_jcg_q30-pro" ++CONFIG_DEFAULT_ENV_FILE="jcg_q30-pro_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_jcg_q30-pro.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_jcg_q30-pro.dts +@@ -0,0 +1,179 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "JCG Q30 PRO"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ factory { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_red { ++ label = "red:status"; ++ gpios = <&gpio 8 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ status_blue { ++ label = "blue:status"; ++ gpios = <&gpio 13 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++ ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0_1", "pwm1_0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "orig-env"; ++ reg = <0x100000 0x80000>; ++ }; ++ ++ partition@160000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x7000000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/jcg_q30-pro_env +@@ -0,0 +1,57 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-jcg_q30-pro-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-jcg_q30-pro-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-jcg_q30-pro-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-jcg_q30-pro-squashfs-sysupgrade.itb ++bootled_pwr=blue:status ++bootled_rec=red:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++ethaddr_factory=mtd read factory 0x40080000 0xa0000 0x800 && env readmem -b ethaddr 0x4008002a 0x6 ; setenv ethaddr_factory ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch new file mode 100644 index 00000000000..7f0564fd497 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/439-add-zyxel_ex5601-t0.patch @@ -0,0 +1,431 @@ +--- /dev/null ++++ b/configs/mt7986_zyxel_ex5601-t0_defconfig +@@ -0,0 +1,186 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-zyxel_ex5601-t0" ++CONFIG_DEFAULT_ENV_FILE="zyxel_ex5601-t0_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-zyxel_ex5601-t0.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="EX5601> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_DM_PCI is not set ++# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++# CONFIG_I2C is not set ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7986a-zyxel_ex5601-t0.dts +@@ -0,0 +1,181 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Author: Valerio 'ftp21' Mancini <ftp21@ftp21.eu> ++ * Author: Nicolò Veronese <nicveronese@gmail.com> ++ */ ++ ++/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Zyxel EX5601-T0 ubootmod"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-sd-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x20000000>; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ factory { ++ label = "reset"; ++ gpios = <&gpio 21 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ ++ wps { ++ label = "wps"; ++ gpios = <&gpio 56 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_WPS_BUTTON>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_green: pwr { ++ label = "green:status"; ++ gpios = <&gpio 13 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led_sfp_green: sfp { ++ label = "green:sfp"; ++ gpios = <&gpio 24 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&uart1_pins>; ++ status = "disabled"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_2"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_00>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ spi-tx-buswidth = <4>; ++ spi-rx-buswidth = <4>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "u-boot-env"; ++ reg = <0x0100000 0x0080000>; ++ }; ++ ++ partition@180000 { ++ label = "Factory"; ++ reg = <0x180000 0x0200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x0200000>; ++ }; ++ ++ partition@540000 { ++ label = "zloader"; ++ reg = <0x540000 0x0040000>; ++ read-only; ++ }; ++ partition@580000 { ++ label = "ubi"; ++ reg = <0x580000 0x1da80000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; ++ +--- /dev/null ++++ b/zyxel_ex5601-t0_env +@@ -0,0 +1,55 @@ ++ethaddr_factory=mtd read Factory 0x40080000 0x0 0x20000 && env readmem -b ethaddr 0x4008002A 0x6 ; setenv ethaddr_factory ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=console=ttyS0,115200n8 console_msg_format=syslog ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-zyxel_ex5601-t0-ubootmod-squashfs-sysupgrade.itb ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=run ubi_read_production && bootm $loadaddr#$bootconf ++boot_recovery=run ubi_read_recovery && bootm $loadaddr#$bootconf ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++part_fit=fit ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr $part_fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run ethaddr_factory ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/440-add-jdcloud_re-cp-03.patch b/package/boot/uboot-mediatek/patches/440-add-jdcloud_re-cp-03.patch new file mode 100644 index 00000000000..e0f3a6e2354 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/440-add-jdcloud_re-cp-03.patch @@ -0,0 +1,324 @@ +--- /dev/null ++++ b/configs/mt7986a_jdcloud_re-cp-03_defconfig +@@ -0,0 +1,112 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-jdcloud_re-cp-03" ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_TARGET_MT7986=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_DEBUG_UART=y ++CONFIG_FIT=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-jdcloud_re-cp-03.dtb" ++CONFIG_LOGLEVEL=7 ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_LOG=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_HUSH_PARSER=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_LINK_LOCAL=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_UUID=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_DEFAULT_ENV_FILE="jdcloud_re-cp-03_env" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_NETCONSOLE=y ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_CLK=y ++CONFIG_GPIO_HOG=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_MDIO=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_RAM=y ++CONFIG_SCSI=y ++CONFIG_DM_SCSI=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_LMB_MAX_REGIONS=64 +--- /dev/null ++++ b/arch/arm/dts/mt7986a-jdcloud_re-cp-03.dts +@@ -0,0 +1,148 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++ ++/dts-v1/; ++#include <dt-bindings/input/linux-event-codes.h> ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "JDCloud RE-CP-03"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x40000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ button-joylink { ++ label = "joylink"; ++ linux,code = <BTN_0>; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ ++ button-reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ gpio-leds { ++ compatible = "gpio-leds"; ++ ++ led-0 { ++ label = "blue:status"; ++ gpios = <&gpio 7 GPIO_ACTIVE_HIGH>; ++ default-state = "off"; ++ }; ++ ++ led-1 { ++ label = "red:status"; ++ gpios = <&gpio 11 GPIO_ACTIVE_HIGH>; ++ default-state = "on"; ++ }; ++ ++ led-2 { ++ label = "green:status"; ++ gpios = <&gpio 12 GPIO_ACTIVE_LOW>; ++ default-state = "off"; ++ }; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&mmc0 { ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ max-frequency = <200000000>; ++ non-removable; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/jdcloud_re-cp-03_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/mmcblk0p65 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-jdcloud_re-cp-03-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-jdcloud_re-cp-03-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-jdcloud_re-cp-03-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-jdcloud_re-cp-03-squashfs-sysupgrade.itb ++bootled_pwr=red:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch new file mode 100644 index 00000000000..9b50166a941 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/440-add-xiaomi_mi-router-ax3000t.patch @@ -0,0 +1,414 @@ +--- /dev/null ++++ b/configs/mt7981_xiaomi_mi-router-ax3000t_defconfig +@@ -0,0 +1,163 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7981=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7981_xiaomi_mi-router-ax3000t" ++CONFIG_DEFAULT_ENV_FILE="xiaomi_mi-router-ax3000t_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7981_xiaomi_mi-router-ax3000t.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7981> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++# CONFIG_CMD_EXT4 is not set ++# CONFIG_CMD_FAT is not set ++CONFIG_CMD_FDT=y ++# CONFIG_CMD_FS_GENERIC is not set ++# CONFIG_CMD_FS_UUID is not set ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MTD=y ++# CONFIG_CMD_PCI is not set ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++# CONFIG_CMD_PWM is not set ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++# CONFIG_CMD_USB is not set ++# CONFIG_CMD_FLASH is not set ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++# CONFIG_DM_USB is not set ++# CONFIG_DM_PWM is not set ++# CONFIG_PWM_MTK is not set ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++# CONFIG_DM_SCSI is not set ++# CONFIG_AHCI is not set ++CONFIG_PHY=y ++# CONFIG_PHY_MTK_TPHY is not set ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++# CONFIG_PCI is not set ++# CONFIG_MMC is not set ++# CONFIG_DM_MMC is not set ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++# CONFIG_DM_PCI is not set ++# CONFIG_PCIE_MEDIATEK is not set ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7981=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++# CONFIG_USB is not set ++# CONFIG_USB_HOST is not set ++# CONFIG_USB_XHCI_HCD is not set ++# CONFIG_USB_XHCI_MTK is not set ++# CONFIG_USB_STORAGE is not set ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/arch/arm/dts/mt7981_xiaomi_mi-router-ax3000t.dts +@@ -0,0 +1,187 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7981.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Xiaomi Router AX3000T"; ++ compatible = "mediatek,mt7981", "mediatek,mt7981-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x10000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ reset { ++ label = "reset"; ++ gpios = <&gpio 1 GPIO_ACTIVE_LOW>; ++ linux,code = <KEY_RESTART>; ++ }; ++ ++ mesh { ++ label = "mesh"; ++ gpios = <&gpio 0 GPIO_ACTIVE_LOW>; ++ linux,code = <BTN_9>; ++ linux,input-type = <EV_SW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_blue { ++ label = "blue:status"; ++ gpios = <&gpio 9 GPIO_ACTIVE_LOW>; ++ }; ++ ++ led_status_yellow { ++ label = "yellow:status"; ++ gpios = <&gpio 10 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ mediatek,force-highspeed; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ mediatek,switch = "mt7531"; ++ reset-gpios = <&gpio 39 GPIO_ACTIVE_HIGH>; ++ ++ fixed-link { ++ speed = <2500>; ++ full-duplex; ++ }; ++}; ++ ++&pinctrl { ++ spic_pins: spi1-pins-func-1 { ++ mux { ++ function = "spi"; ++ groups = "spi1_1"; ++ }; ++ }; ++ ++ uart1_pins: spi1-pins-func-3 { ++ mux { ++ function = "uart"; ++ groups = "uart1_2"; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ }; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x00 0x100000>; ++ }; ++ ++ partition@100000 { ++ label = "Nvram"; ++ reg = <0x100000 0x40000>; ++ }; ++ ++ partition@140000 { ++ label = "Bdata"; ++ reg = <0x140000 0x40000>; ++ }; ++ ++ partition@180000 { ++ label = "factory"; ++ reg = <0x180000 0x200000>; ++ }; ++ ++ partition@380000 { ++ label = "fip"; ++ reg = <0x380000 0x200000>; ++ }; ++ ++ partition@580000 { ++ label = "crash"; ++ reg = <0x580000 0x40000>; ++ }; ++ ++ partition@5c0000 { ++ label = "crash_log"; ++ reg = <0x5c0000 0x40000>; ++ }; ++ ++ partition@600000 { ++ label = "ubi"; ++ reg = <0x600000 0x7000000>; ++ }; ++ ++ partition@7600000 { ++ label = "KF"; ++ reg = <0x7600000 0x40000>; ++ }; ++ }; ++ }; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; +--- /dev/null ++++ b/xiaomi_mi-router-ax3000t_env +@@ -0,0 +1,55 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=console=ttyS0,115200n8 console_msg_format=syslog ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-1 ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-xiaomi_mi-router-ax3000t-ubootmod-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-xiaomi_mi-router-ax3000t-ubootmod-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-xiaomi_mi-router-ax3000t-ubootmod-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-xiaomi_mi-router-ax3000t-ubootmod-squashfs-sysupgrade.itb ++bootled_pwr=yellow:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ; run boot_tftp_forever ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run mtd_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run mtd_write_bl2 ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++mtd_write_fip=mtd erase fip && mtd write fip $loadaddr ++mtd_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 0 || run ubi_format ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 1 || run ubi_format ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ; reset ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic 2 && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic 3 && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" diff --git a/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch new file mode 100644 index 00000000000..e54220878c2 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/442-add-bpi-r3-mini.patch @@ -0,0 +1,779 @@ +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-mini-emmc_defconfig +@@ -0,0 +1,203 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MDIO=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MDIO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_ETHERNET_ID=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY_AIROHA=y ++CONFIG_PHY_AIROHA_EN8811H=y ++CONFIG_PHY_AIROHA_FW_IN_MMC=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7986a_bpi-r3-mini-snand_defconfig +@@ -0,0 +1,203 @@ ++CONFIG_ARM=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TARGET_MT7986=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_DEFAULT_DEVICE_TREE="mt7986a-bpi-r3-mini" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r3-mini_snand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7986a-bpi-r3-mini.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_DEBUG_UART_BASE=0x11002000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_LOAD_ADDR=0x46000000 ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_SYS_PROMPT="MT7986> " ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MDIO=y ++CONFIG_CMD_MII=y ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_DM_MDIO=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_PHY_ETHERNET_ID=y ++CONFIG_PHY_FIXED=y ++CONFIG_MTK_AHCI=y ++CONFIG_DM_ETH=y ++CONFIG_DM_ETH_PHY=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7622=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PHY_AIROHA=y ++CONFIG_PHY_AIROHA_EN8811H=y ++CONFIG_PHY_AIROHA_FW_IN_UBI=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7986=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_HEXDUMP=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++#CONFIG_DM_SPI_FLASH=y ++#CONFIG_SPI_FLASH_MTD=y ++#CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++#CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y +--- /dev/null ++++ b/bananapi_bpi-r3-mini_snand_env +@@ -0,0 +1,61 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=ubi.block=0,fit root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3-mini ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-snand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb ++bootfile_en8811h_fw=EthMD32.bin ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NAND][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad Airoha EN8811H firmware via TFTP then write to NAND.[0m=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_8=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run ubi_write_en8811h_fw ++part_default=production ++part_recovery=recovery ++reset_factory=mw $loadaddr 0xff 0x1f000 ; ubi write $loadaddr ubootenv 0x1f000 ; ubi write $loadaddr ubootenv2 0x1f000 ; ubi remove rootfs_data ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x40000 && mtd write bl2 $loadaddr 0x40000 0x40000 && mtd write bl2 $loadaddr 0x80000 0x40000 && mtd write bl2 $loadaddr 0xc0000 0x40000 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x1f000 dynamic ; ubi check ubootenv2 || ubi create ubootenv2 0x1f000 dynamic ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_en8811h_fw=ubi check en8811h-fw && ubi remove en8811h-fw ; ubi create en8811h-fw 0x24000 static ; ubi write $loadaddr en8811h-fw 0x24000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r3-mini_emmc_env +@@ -0,0 +1,59 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x46000000 ++console=earlycon=uart8250,mmio32,0x11002000 console=ttyS0 ++bootargs=root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-mt7986a-bananapi-bpi-r3-mini ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r3-mini-squashfs-sysupgrade.itb ++bootfile_en8811h_fw=EthMD32.bin ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad Airoha EN8811H firmware via TFTP then write to eMMC.[0m=run boot_tftp_write_en8811h_fw ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_8=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp_write_en8811h_fw=tftpboot $loadaddr $bootfile_en8811h_fw && run emmc_write_en8811h_fw ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_en8811h_fw=mmc partconf 0 1 2 2 && mmc erase 0x0 0x120 && mmc write $fileaddr 0x0 0x120 ; mmc partconf 0 1 1 0 ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/arch/arm/dts/mt7986a-bpi-r3-mini.dts +@@ -0,0 +1,238 @@ ++// SPDX-License-Identifier: GPL-2.0-or-later ++ ++/dts-v1/; ++#include "mt7986.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ model = "Bananapi BPi-R3 Mini"; ++ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb"; ++ ++ chosen { ++ stdout-path = &uart0; ++ tick-timer = &timer0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0x40000000 0x80000000>; ++ }; ++ ++ gpio-keys { ++ compatible = "gpio-keys"; ++ ++ button-reset { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 7 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ status_led: led-0 { ++ label = "green:status"; ++ gpios = <&gpio 19 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-1 { ++ label = "blue:wlan2g"; ++ gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led-2 { ++ label = "blue:wlan5g"; ++ gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++}; ++ ++ð { ++ status = "okay"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mdio_pins>; ++ ++ mediatek,gmac-id = <0>; ++ phy-mode = "2500base-x"; ++ phy-handle = <&phy14>; ++ ++ phy14: eth-phy@e { ++ compatible = "ethernet-phy-id03a2.a411"; ++ reg = <14>; ++ ++ airoha,rx-pol-reverse; ++ ++ reset-gpios = <&gpio 49 GPIO_ACTIVE_LOW>; ++ reset-assert-us = <10000>; ++ reset-deassert-us = <20000>; ++ }; ++}; ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ bus-width = <8>; ++ max-frequency = <200000000>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; ++ ++&pinctrl { ++ mdio_pins: mdio-pins { ++ mux { ++ function = "eth"; ++ groups = "mdc_mdio"; ++ }; ++ ++ conf-en8811-pwr-a { ++ pins = "GPIO_11"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ output-low; ++ }; ++ ++ conf-en8811-pwr-b { ++ pins = "GPIO_12"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ output-low; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ drive-strength = <MTK_DRIVE_6mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_10>; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ drive-strength = <MTK_DRIVE_4mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_01>; ++ }; ++ }; ++ ++ spi_flash_pins: spi0-pins-func-1 { ++ mux { ++ function = "flash"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ ++ conf-pu { ++ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-up = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ ++ conf-pd { ++ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; ++ drive-strength = <MTK_DRIVE_8mA>; ++ bias-pull-down = <MTK_PUPD_SET_R1R0_11>; ++ }; ++ }; ++ ++ pwm_pins: pwm0-pins-func-1 { ++ mux { ++ function = "pwm"; ++ groups = "pwm0"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi_flash_pins>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <1>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <20000000>; ++ ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x200000>; ++ }; ++ ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; ++ }; ++ }; ++ }; ++ ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&watchdog { ++ status = "disabled"; ++}; diff --git a/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch new file mode 100644 index 00000000000..0f08c032946 --- /dev/null +++ b/package/boot/uboot-mediatek/patches/450-add-bpi-r4.patch @@ -0,0 +1,998 @@ +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-emmc_defconfig +@@ -0,0 +1,180 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_emmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-sdmmc_defconfig +@@ -0,0 +1,180 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-sd" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_sdmmc_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-sd.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_MMC=y ++CONFIG_ENV_OFFSET=0x400000 ++CONFIG_ENV_OFFSET_REDUND=0x440000 ++CONFIG_ENV_SIZE=0x40000 ++CONFIG_ENV_SIZE_REDUND=0x40000 ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/configs/mt7988a_bananapi_bpi-r4-snand_defconfig +@@ -0,0 +1,182 @@ ++CONFIG_ARM=y ++CONFIG_SYS_HAS_NONCACHED_MEMORY=y ++CONFIG_POSITION_INDEPENDENT=y ++CONFIG_ARCH_MEDIATEK=y ++CONFIG_TEXT_BASE=0x41e00000 ++CONFIG_SYS_MALLOC_F_LEN=0x4000 ++CONFIG_NR_DRAM_BANKS=1 ++CONFIG_SYS_PROMPT="MT7988> " ++CONFIG_TARGET_MT7988=y ++CONFIG_DEBUG_UART_BASE=0x11000000 ++CONFIG_DEBUG_UART_CLOCK=40000000 ++CONFIG_SYS_LOAD_ADDR=0x50000000 ++CONFIG_DEBUG_UART=y ++CONFIG_SYS_CBSIZE=512 ++CONFIG_SYS_PBSIZE=1049 ++CONFIG_DEFAULT_DEVICE_TREE="mt7988a-bananapi-bpi-r4-emmc" ++CONFIG_DEFAULT_ENV_FILE="bananapi_bpi-r4_snand_env" ++CONFIG_DEFAULT_FDT_FILE="mediatek/mt7988a-bpi-r4-emmc.dtb" ++CONFIG_OF_LIBFDT_OVERLAY=y ++CONFIG_OF_SYSTEM_SETUP=y ++CONFIG_SMBIOS_PRODUCT_NAME="" ++CONFIG_AUTOBOOT_KEYED=y ++CONFIG_BOOTDELAY=30 ++CONFIG_AUTOBOOT_MENU_SHOW=y ++CONFIG_CFB_CONSOLE_ANSI=y ++CONFIG_BOARD_LATE_INIT=y ++CONFIG_BUTTON=y ++CONFIG_BUTTON_GPIO=y ++CONFIG_GPIO_HOG=y ++CONFIG_CMD_ENV_FLAGS=y ++CONFIG_FIT=y ++CONFIG_FIT_ENABLE_SHA256_SUPPORT=y ++CONFIG_LED=y ++CONFIG_LED_BLINK=y ++CONFIG_LED_GPIO=y ++CONFIG_LOGLEVEL=7 ++CONFIG_LOG=y ++CONFIG_CMD_BOOTMENU=y ++CONFIG_CMD_BOOTP=y ++CONFIG_CMD_BUTTON=y ++CONFIG_CMD_CACHE=y ++CONFIG_CMD_CDP=y ++CONFIG_CMD_CPU=y ++CONFIG_CMD_DHCP=y ++CONFIG_CMD_DM=y ++CONFIG_CMD_DNS=y ++CONFIG_CMD_ECHO=y ++CONFIG_CMD_ENV_READMEM=y ++CONFIG_CMD_ERASEENV=y ++CONFIG_CMD_EXT4=y ++CONFIG_CMD_FAT=y ++CONFIG_CMD_FDT=y ++CONFIG_CMD_FS_GENERIC=y ++CONFIG_CMD_FS_UUID=y ++CONFIG_CMD_GPIO=y ++CONFIG_CMD_GPT=y ++CONFIG_CMD_HASH=y ++CONFIG_CMD_ITEST=y ++CONFIG_CMD_LED=y ++CONFIG_CMD_LICENSE=y ++CONFIG_CMD_LINK_LOCAL=y ++# CONFIG_CMD_MBR is not set ++CONFIG_CMD_MMC=y ++CONFIG_CMD_MTD=y ++CONFIG_CMD_PCI=y ++CONFIG_CMD_PSTORE=y ++CONFIG_CMD_PSTORE_MEM_ADDR=0x42ff0000 ++CONFIG_CMD_SF_TEST=y ++CONFIG_CMD_PING=y ++CONFIG_CMD_PXE=y ++CONFIG_CMD_PWM=y ++CONFIG_CMD_SMC=y ++CONFIG_CMD_TFTPBOOT=y ++CONFIG_CMD_TFTPSRV=y ++CONFIG_CMD_UBI=y ++CONFIG_CMD_UBI_RENAME=y ++CONFIG_CMD_UBIFS=y ++CONFIG_CMD_ASKENV=y ++CONFIG_CMD_PART=y ++CONFIG_CMD_RARP=y ++CONFIG_CMD_SETEXPR=y ++CONFIG_CMD_SLEEP=y ++CONFIG_CMD_SNTP=y ++CONFIG_CMD_SOURCE=y ++CONFIG_CMD_STRINGS=y ++CONFIG_CMD_USB=y ++CONFIG_CMD_UUID=y ++CONFIG_DISPLAY_CPUINFO=y ++CONFIG_DM_MMC=y ++CONFIG_DM_MTD=y ++CONFIG_DM_REGULATOR=y ++CONFIG_DM_REGULATOR_FIXED=y ++CONFIG_DM_REGULATOR_GPIO=y ++CONFIG_DM_USB=y ++CONFIG_DM_PWM=y ++CONFIG_PWM_MTK=y ++CONFIG_HUSH_PARSER=y ++CONFIG_SYS_REDUNDAND_ENVIRONMENT=y ++CONFIG_SYS_RELOC_GD_ENV_ADDR=y ++CONFIG_VERSION_VARIABLE=y ++CONFIG_PARTITION_UUIDS=y ++CONFIG_NETCONSOLE=y ++CONFIG_DM_GPIO=y ++CONFIG_DM_SCSI=y ++CONFIG_AHCI=y ++CONFIG_AHCI_PCI=y ++CONFIG_SCSI_AHCI=y ++CONFIG_SCSI=y ++CONFIG_CMD_SCSI=y ++CONFIG_PHY=y ++CONFIG_PHY_MTK_TPHY=y ++CONFIG_MTK_AHCI=y ++CONFIG_PCI=y ++CONFIG_MTD=y ++CONFIG_MTD_UBI_FASTMAP=y ++CONFIG_DM_PCI=y ++CONFIG_PCIE_MEDIATEK=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_PRE_CONSOLE_BUFFER=y ++CONFIG_PRE_CON_BUF_ADDR=0x4007EF00 ++CONFIG_RAM=y ++CONFIG_DM_SERIAL=y ++CONFIG_MTK_SERIAL=y ++CONFIG_MMC=y ++CONFIG_MMC_DEFAULT_DEV=1 ++CONFIG_MMC_SUPPORTS_TUNING=y ++CONFIG_SPI=y ++CONFIG_DM_SPI=y ++CONFIG_MTK_SPI_NAND=y ++CONFIG_MTK_SPI_NAND_MTD=y ++CONFIG_SYSRESET_WATCHDOG=y ++CONFIG_WDT_MTK=y ++CONFIG_LZO=y ++CONFIG_ZSTD=y ++CONFIG_HEXDUMP=y ++CONFIG_RANDOM_UUID=y ++CONFIG_REGEX=y ++CONFIG_USB=y ++CONFIG_USB_HOST=y ++CONFIG_USB_XHCI_HCD=y ++CONFIG_USB_XHCI_MTK=y ++CONFIG_USB_STORAGE=y ++CONFIG_OF_EMBED=y ++CONFIG_ENV_OVERWRITE=y ++CONFIG_ENV_IS_IN_UBI=y ++CONFIG_ENV_UBI_PART="ubi" ++CONFIG_ENV_SIZE=0x1f000 ++CONFIG_ENV_SIZE_REDUND=0x1f000 ++CONFIG_ENV_UBI_VOLUME="ubootenv" ++CONFIG_ENV_UBI_VOLUME_REDUND="ubootenv2" ++CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y ++CONFIG_NET_RANDOM_ETHADDR=y ++CONFIG_REGMAP=y ++CONFIG_SYSCON=y ++CONFIG_CLK=y ++CONFIG_SUPPORT_EMMC_BOOT=y ++CONFIG_MMC_HS200_SUPPORT=y ++CONFIG_MMC_MTK=y ++CONFIG_PHY_FIXED=y ++CONFIG_DM_ETH=y ++CONFIG_MEDIATEK_ETH=y ++CONFIG_PINCTRL=y ++CONFIG_PINCONF=y ++CONFIG_PINCTRL_MT7988=y ++CONFIG_POWER_DOMAIN=y ++CONFIG_MTK_POWER_DOMAIN=y ++CONFIG_USE_DEFAULT_ENV_FILE=y ++CONFIG_MTD_SPI_NAND=y ++CONFIG_MTK_SPIM=y ++#CONFIG_MTK_SNOR=y ++CONFIG_DM_SPI_FLASH=y ++CONFIG_SPI_FLASH_MTD=y ++CONFIG_SPI_FLASH_WINBOND=y ++# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set ++CONFIG_CMD_SF=y ++CONFIG_CMD_NAND=y ++CONFIG_CMD_NAND_TRIMFFS=y ++CONFIG_LMB_MAX_REGIONS=64 ++CONFIG_USE_IPADDR=y ++CONFIG_IPADDR="192.168.1.1" ++CONFIG_USE_SERVERIP=y ++CONFIG_SERVERIP="192.168.1.254" +--- /dev/null ++++ b/bananapi_bpi-r4_sdmmc_env +@@ -0,0 +1,66 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_sdmmc ; fi ++bootconf=config-mt7988a-bananapi-bpi-r4 ++bootconf_sd=mt7988a-bananapi-bpi-r4-sd ++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc ++bootconf_extra= ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SD card][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from SD card.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from SD card.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to SD card.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mInstall bootloader, recovery and production to NAND.[0m=if nand info ; then run ubi_init ; else echo "NAND not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_7=Reboot.=reset ++bootmenu_8=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run sdmmc_read_production && bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run sdmmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc ; led $bootled_rec off ++boot_sdmmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run sdmmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run sdmmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_sd ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf#$bootconf_sd ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++sdmmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++sdmmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++sdmmc_read_snand_bl2=part start mmc 0 install part_addr && mmc read $loadaddr $part_addr 0x400 ++sdmmc_read_snand_fip=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x800 && mmc read $loadaddr $offset 0x1000 ++sdmmc_read_emmc_install=part start mmc 0 install part_addr && setexpr offset $part_addr + 0x3800 && mmc read $loadaddr $offset 0x4000 ++sdmmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++sdmmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 ++ubi_create_env=ubi create ubootenv 0x100000 dynamic 1 ; ubi create ubootenv2 0x100000 dynamic 2 ++ubi_format=ubi detach ; mtd erase ubi && ubi part ubi ++ubi_init=run ubi_format && run ubi_init_bl && run ubi_create_env && run ubi_init_openwrt && run ubi_init_emmc_install ++ubi_init_openwrt=run sdmmc_read_recovery && iminfo $loadaddr && run ubi_write_recovery ; run sdmmc_read_production && iminfo $loadaddr && run ubi_write_production ++ubi_init_bl=run sdmmc_read_snand_bl2 && run snand_write_bl2 && run sdmmc_read_snand_fip && run ubi_write_fip ++ubi_init_emmc_install=run sdmmc_read_emmc_install && run ubi_write_emmc_install ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_emmc_install=ubi check emmc_install && ubi remove emmc_install ; ubi create emmc_install 0x800000 dynamic ; ubi write $loadaddr emmc_install 0x800000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r4_snand_env +@@ -0,0 +1,67 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 ubi.block=0,fit ++bootconf=config-mt7988a-bananapi-bpi-r4 ++bootconf_extra=mt7988a-bananapi-bpi-r4-emmc ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_ubi ; fi ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-snand-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-snand-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[SPI-NAND][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from NAND.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from NAND.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to NAND.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to NAND.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to NAND.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=[31mInstall bootloader, recovery and production to eMMC.[0m=if mmc partconf 0 ; then run emmc_init ; else echo "eMMC not detected" ; fi ; run bootmenu_confirm_return ++bootmenu_9=Reboot.=reset ++bootmenu_10=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run ubi_read_production && bootm $loadaddr#$bootconf#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run ubi_read_recovery && bootm $loadaddr#$bootconf ; led $bootled_rec off ++boot_ubi=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run ubi_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run ubi_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf ; fi ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run ubi_write_fip && run reset_factory ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run snand_write_bl2 ++part_default=production ++part_recovery=recovery ++reset_factory=ubi part ubi ; mw $loadaddr 0x0 0x800 ; ubi write $loadaddr ubootenv 0x800 ; ubi write $loadaddr ubootenv2 0x800 ++snand_write_bl2=mtd erase bl2 && mtd write bl2 $loadaddr 0x0 0x80000 && mtd write bl2 $loadaddr 0x80000 0x80000 && mtd write bl2 $loadaddr 0x100000 0x80000 && mtd write bl2 $loadaddr 0x180000 0x80000 ++ubi_create_env=ubi check ubootenv || ubi create ubootenv 0x100000 dynamic 1 ; ubi check ubootenv2 || ubi create ubootenv2 0x100000 dynamic 2 ++ubi_prepare_rootfs=if ubi check rootfs_data ; then else if env exists rootfs_data_max ; then ubi create rootfs_data $rootfs_data_max dynamic || ubi create rootfs_data - dynamic ; else ubi create rootfs_data - dynamic ; fi ; fi ++ubi_read_production=ubi read $loadaddr fit && iminfo $loadaddr && run ubi_prepare_rootfs ++ubi_read_recovery=ubi check recovery && ubi read $loadaddr recovery ++ubi_read_emmc_install=ubi check emmc_install && ubi read $loadaddr emmc_install ++ubi_remove_rootfs=ubi check rootfs_data && ubi remove rootfs_data ++ubi_write_fip=ubi check fip && ubi remove fip ; ubi create fip 0x200000 static ; ubi write $loadaddr fip 0x200000 ++ubi_write_production=ubi check fit && ubi remove fit ; run ubi_remove_rootfs ; ubi create fit $filesize dynamic && ubi write $loadaddr fit $filesize ++ubi_write_recovery=ubi check recovery && ubi remove recovery ; run ubi_remove_rootfs ; ubi create recovery $filesize dynamic && ubi write $loadaddr recovery $filesize ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++emmc_init=mmc dev 0 && mmc bootbus 0 0 0 0 && run emmc_init_bl && run emmc_init_openwrt ; env default bootcmd ; saveenv ; saveenv ++emmc_init_bl=run ubi_read_emmc_install && setenv fileaddr $loadaddr && run emmc_write_bl2 && setexpr fileaddr $loadaddr + 0x100000 && run emmc_write_fip && setexpr fileaddr $loadaddr + 0x500000 && run emmc_write_hdr ++emmc_init_openwrt=run ubi_read_recovery && iminfo $loadaddr && run emmc_write_recovery ; run ubi_read_production && iminfo $loadaddr && run emmc_write_production ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_hdr=mmc erase 0x0 0x40 && mmc write $fileaddr 0x0 0x40 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; run ubi_create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/bananapi_bpi-r4_emmc_env +@@ -0,0 +1,57 @@ ++ipaddr=192.168.1.1 ++serverip=192.168.1.254 ++loadaddr=0x50000000 ++bootargs=console=ttyS0,115200n1 pci=pcie_bus_perf root=/dev/fit0 ++bootcmd=if pstore check ; then run boot_recovery ; else run boot_emmc ; fi ++bootconf=config-mt7988a-bananapi-bpi-r4 ++bootconf_base=config-mt7988a-bananapi-bpi-r4 ++bootconf_emmc=mt7988a-bananapi-bpi-r4-emmc ++bootconf_extra= ++bootdelay=0 ++bootfile=openwrt-mediatek-filogic-bananapi_bpi-r4-initramfs-recovery.itb ++bootfile_bl2=openwrt-mediatek-filogic-bananapi_bpi-r4-emmc-preloader.bin ++bootfile_fip=openwrt-mediatek-filogic-bananapi_bpi-r4-emmc-bl31-uboot.fip ++bootfile_upg=openwrt-mediatek-filogic-bananapi_bpi-r4-squashfs-sysupgrade.itb ++bootled_pwr=green:status ++bootled_rec=blue:status ++bootmenu_confirm_return=askenv - Press ENTER to return to menu ; bootmenu 60 ++bootmenu_default=0 ++bootmenu_delay=0 ++bootmenu_title= [0;34m( ( ( [1;39mOpenWrt[0;34m ) ) ) [0;36m[eMMC][0m ++bootmenu_0=Initialize environment.=run _firstboot ++bootmenu_0d=Run default boot command.=run boot_default ++bootmenu_1=Boot system via TFTP.=run boot_tftp ; run bootmenu_confirm_return ++bootmenu_2=Boot production system from eMMC.=run boot_production ; run bootmenu_confirm_return ++bootmenu_3=Boot recovery system from eMMC.=run boot_recovery ; run bootmenu_confirm_return ++bootmenu_4=Load production system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_production ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_5=Load recovery system via TFTP then write to eMMC.=setenv noboot 1 ; setenv replacevol 1 ; run boot_tftp_recovery ; setenv noboot ; setenv replacevol ; run bootmenu_confirm_return ++bootmenu_6=[31mLoad BL31+U-Boot FIP via TFTP then write to eMMC.[0m=run boot_tftp_write_fip ; run bootmenu_confirm_return ++bootmenu_7=[31mLoad BL2 preloader via TFTP then write to eMMC.[0m=run boot_tftp_write_bl2 ; run bootmenu_confirm_return ++bootmenu_8=Reboot.=reset ++bootmenu_9=Reset all settings to factory defaults.=run reset_factory ; reset ++boot_first=if button reset ; then led $bootled_rec on ; run boot_tftp_recovery ; setenv flag_recover 1 ; run boot_default ; fi ; bootmenu ++boot_default=if env exists flag_recover ; then else run bootcmd ; fi ; run boot_recovery ; setenv replacevol 1 ; run boot_tftp_forever ++boot_production=led $bootled_pwr on ; run emmc_read_production && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_pwr off ++boot_recovery=led $bootled_rec on ; run emmc_read_recovery && bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; led $bootled_rec off ++boot_emmc=run boot_production ; run boot_recovery ++boot_tftp_forever=led $bootled_rec on ; while true ; do run boot_tftp_recovery ; sleep 1 ; done ++boot_tftp_production=tftpboot $loadaddr $bootfile_upg && env exists replacevol && iminfo $loadaddr && run emmc_write_production ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc#$bootconf_extra ; fi ++boot_tftp_recovery=tftpboot $loadaddr $bootfile && env exists replacevol && iminfo $loadaddr && run emmc_write_recovery ; if env exists noboot ; then else bootm $loadaddr#$bootconf#$bootconf_emmc ; fi ++boot_tftp_write_fip=tftpboot $loadaddr $bootfile_fip && run emmc_write_fip ++boot_tftp_write_bl2=tftpboot $loadaddr $bootfile_bl2 && run emmc_write_bl2 ++boot_tftp=tftpboot $loadaddr $bootfile && bootm $loadaddr#$bootconf ++mmc_write_vol=imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc erase 0x$part_addr 0x$image_size && mmc write $loadaddr 0x$part_addr 0x$image_size ++mmc_read_vol=mmc read $loadaddr $part_addr 0x100 && imszb $loadaddr image_size && test 0x$image_size -le 0x$part_size && mmc read $loadaddr 0x$part_addr 0x$image_size && setexpr filesize $image_size * 0x200 ++part_default=production ++part_recovery=recovery ++reset_factory=eraseenv && reset ++emmc_read_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_read_vol ++emmc_read_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_read_vol ++emmc_write_bl2=mmc partconf 0 1 1 1 && mmc erase 0x0 0x400 && mmc write $fileaddr 0x0 0x400 ; mmc partconf 0 1 1 0 ++emmc_write_fip=mmc erase 0x3400 0x2000 && mmc write $fileaddr 0x3400 0x2000 && mmc erase 0x2000 0x800 ++emmc_write_production=part start mmc 0 $part_default part_addr && part size mmc 0 $part_default part_size && run mmc_write_vol ++emmc_write_recovery=part start mmc 0 $part_recovery part_addr && part size mmc 0 $part_recovery part_size && run mmc_write_vol ++_init_env=setenv _init_env ; setenv _create_env ; saveenv ; saveenv ++_firstboot=setenv _firstboot ; run _switch_to_menu ; run _init_env ; run boot_first ++_switch_to_menu=setenv _switch_to_menu ; setenv bootdelay 3 ; setenv bootmenu_delay 3 ; setenv bootmenu_0 $bootmenu_0d ; setenv bootmenu_0d ; run _bootmenu_update_title ++_bootmenu_update_title=setenv _bootmenu_update_title ; setenv bootmenu_title "$bootmenu_title [33m$ver[0m" +--- /dev/null ++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4.dtsi +@@ -0,0 +1,199 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7988.dtsi" ++#include <dt-bindings/gpio/gpio.h> ++#include <dt-bindings/input/linux-event-codes.h> ++ ++/ { ++ model = "Bananapi BPI-R4"; ++ compatible = "bananapi,bpi-r4", "mediatek,mt7988"; ++ ++ chosen { ++ stdout-path = &uart0; ++ }; ++ ++ memory@40000000 { ++ device_type = "memory"; ++ reg = <0 0x40000000 0 0x10000000>; ++ }; ++ ++ reg_3p3v: regulator-3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-3.3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_1p8v: regulator-1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "fixed-1.8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ keys { ++ compatible = "gpio-keys"; ++ ++ wps { ++ label = "reset"; ++ linux,code = <KEY_RESTART>; ++ gpios = <&gpio 14 GPIO_ACTIVE_LOW>; ++ }; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led_status_green: led-green { ++ label = "green:status"; ++ gpios = <&gpio 79 GPIO_ACTIVE_HIGH>; ++ }; ++ ++ led_status_blue: led-blue { ++ label = "blue:status"; ++ gpios = <&gpio 63 GPIO_ACTIVE_HIGH>; ++ }; ++ }; ++}; ++ ++&uart0 { ++ status = "okay"; ++}; ++ ++&i2c1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&i2c1_pins>; ++ status = "okay"; ++}; ++ ++ð { ++ status = "okay"; ++ mediatek,gmac-id = <0>; ++ phy-mode = "usxgmii"; ++ mediatek,switch = "mt7988"; ++ ++ fixed-link { ++ speed = <1000>; ++ full-duplex; ++ pause; ++ }; ++}; ++ ++&pinctrl { ++ i2c1_pins: i2c1-pins { ++ mux { ++ function = "i2c"; ++ groups = "i2c1_0"; ++ }; ++ }; ++ ++ pwm_pins: pwm-pins { ++ mux { ++ function = "pwm"; ++ groups = "pwm0", "pwm1", "pwm2", "pwm3", "pwm4", ++ "pwm5", "pwm6", "pwm7"; ++ }; ++ }; ++ ++ spi0_pins: spi0-pins { ++ mux { ++ function = "spi"; ++ groups = "spi0", "spi0_wp_hold"; ++ }; ++ }; ++ ++ mmc0_pins_default: mmc0default { ++ mux { ++ function = "flash"; ++ groups = "emmc_51"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", ++ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", ++ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; ++ input-enable; ++ }; ++ ++ conf-clk { ++ pins = "EMMC_CK"; ++ }; ++ ++ conf-dsl { ++ pins = "EMMC_DSL"; ++ }; ++ ++ conf-rst { ++ pins = "EMMC_RSTB"; ++ }; ++ }; ++ ++ mmc1_pins_default: mmc1default { ++ mux { ++ function = "flash"; ++ groups = "emmc_45"; ++ }; ++ ++ conf-cmd-dat { ++ pins = "SPI2_CSB", "SPI2_MISO", "SPI2_MOSI", ++ "SPI2_CLK", "SPI2_HOLD"; ++ input-enable; ++ }; ++ ++ conf-clk { ++ pins = "SPI2_WP"; ++ }; ++ }; ++}; ++ ++&pwm { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pwm_pins>; ++ status = "okay"; ++}; ++ ++&spi0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&spi0_pins>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ must_tx; ++ enhance_timing; ++ dma_ext; ++ ipm_design; ++ support_quad; ++ tick_dly = <2>; ++ sample_sel = <0>; ++ ++ spi_nand@0 { ++ compatible = "spi-nand"; ++ reg = <0>; ++ spi-max-frequency = <52000000>; ++ partitions { ++ compatible = "fixed-partitions"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ++ partition@0 { ++ label = "bl2"; ++ reg = <0x0 0x200000>; ++ }; ++ ++ partition@200000 { ++ label = "ubi"; ++ reg = <0x200000 0x7e00000>; ++ compatible = "linux,ubi"; ++ }; ++ }; ++ }; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-sd.dts +@@ -0,0 +1,19 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7988a-bananapi-bpi-r4.dtsi" ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc1_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <4>; ++ cap-sd-highspeed; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/dts/mt7988a-bananapi-bpi-r4-emmc.dts +@@ -0,0 +1,21 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (c) 2022 MediaTek Inc. ++ * Author: Sam Shih <sam.shih@mediatek.com> ++ */ ++ ++/dts-v1/; ++#include "mt7988a-bananapi-bpi-r4.dtsi" ++ ++&mmc0 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&mmc0_pins_default>; ++ max-frequency = <52000000>; ++ bus-width = <8>; ++ cap-mmc-highspeed; ++ cap-mmc-hw-reset; ++ vmmc-supply = <®_3p3v>; ++ vqmmc-supply = <®_1p8v>; ++ non-removable; ++ status = "okay"; ++}; diff --git a/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch b/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch new file mode 100644 index 00000000000..2f0ed85e53f --- /dev/null +++ b/package/boot/uboot-mediatek/patches/500-board-mt7623-fix-mmc-detect.patch @@ -0,0 +1,21 @@ +--- a/board/mediatek/mt7623/mt7623_rfb.c ++++ b/board/mediatek/mt7623/mt7623_rfb.c +@@ -9,6 +9,7 @@ + #include <env.h> + #include <init.h> + #include <mmc.h> ++#include <part.h> + #include <asm/global_data.h> + #include <linux/delay.h> + +@@ -31,8 +32,9 @@ int mmc_get_boot_dev(void) + { + int g_mmc_devid = -1; + char *uflag = (char *)0x81DFFFF0; ++ struct blk_desc *desc; + +- if (!find_mmc_device(1)) ++ if (blk_get_device_by_str("mmc", "1", &desc) < 0) + return 0; + + if (strncmp(uflag,"eMMC",4)==0) { |