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authorJo-Philipp Wich <jo@mein.io>2018-08-30 13:19:18 +0200
committerJo-Philipp Wich <jo@mein.io>2018-08-30 13:19:26 +0200
commit4302c917cc4dc244c007c6c1902b8e138a74ed0e (patch)
tree138d1614bef3f5288ce6dedbafbb4061a8bc669a /target
parent77e2bccde8f7f98603f60473023dadec4f473cf6 (diff)
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Revert "ramips: mmc: Fix init for MT7628AN"
This reverts commit 3a8efaef00d6b7317c46fe6b7e923912d8bf3500. The change reportedly breaks UART2 on some boards. Furthermore it uses bitwise logic on an uninitialized variable and fails to explain what it is fixing exactly. Signed-off-by: Jo-Philipp Wich <jo@mein.io>
Diffstat (limited to 'target')
-rw-r--r--target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h1
-rw-r--r--target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c16
2 files changed, 1 insertions, 16 deletions
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
index a3c50d0528..33fa59a019 100644
--- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
+++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/mt6575_sd.h
@@ -234,7 +234,6 @@ enum {
#define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */
#define MSDC_IOCON_RSPL (0x1 << 1) /* RW */
#define MSDC_IOCON_DSPL (0x1 << 2) /* RW */
-#define MSDC_IOCON_WDSPL (0x1 << 8) /* RW */
#define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */
#define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */
#define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */
diff --git a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
index e1493290a0..97ae927d2d 100644
--- a/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
+++ b/target/linux/ramips/files-4.14/drivers/mmc/host/mtk-mmc/sd.c
@@ -1796,9 +1796,6 @@ static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
MSDC_SMPL_FALLING);
sdr_set_field(MSDC_IOCON, MSDC_IOCON_DSPL,
MSDC_SMPL_FALLING);
- /* sdxc: set sample crc by clock falling edge. Added by zhangzf */
- if (ralink_soc == MT762X_SOC_MT7628AN)
- sdr_set_field(MSDC_IOCON, MSDC_IOCON_WDSPL, MSDC_SMPL_FALLING);
//} /* for tuning debug */
} else { /* default value */
sdr_write32(MSDC_IOCON, 0x00000000);
@@ -2208,7 +2205,7 @@ static int msdc_drv_probe(struct platform_device *pdev)
struct msdc_host *host;
struct msdc_hw *hw;
int ret;
- u32 reg, reg1;
+ u32 reg;
// Set the pins for sdxc to sdxc mode
//FIXME: this should be done by pinctl and not by the sd driver
@@ -2218,17 +2215,6 @@ static int msdc_drv_probe(struct platform_device *pdev)
0x60)) & ~(0x3 << 18);
if (ralink_soc == MT762X_SOC_MT7620A)
reg |= 0x1 << 18;
- }
- else if (ralink_soc == MT762X_SOC_MT7628AN) {
- /* Fixed MT7628 SDXC init by zhangzf */
- reg &= ~((0x3 << 0)|(0x3 << 6)|(0x3 << 10)|(0x1 << 15)|(0x3 << 20)|(0x3 << 24));
- reg |= ((0x1 << 0)|(0x1 << 6)|(0x1 << 10)|(0x1 << 15)|(0x1 << 20)|(0x1 << 24));
-#if defined (CONFIG_MTK_MMC_EMMC_8BIT)
- reg |= 0x3 << 26 | 0x3 << 28 | 0x3 << 30;
-#endif
- reg1 = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340));
- reg1 |= (0x1 << 11); //Normal mode(AP mode), SDXC CLK=PAD_GPIO0=GPIO11, driving = 8mA
- sdr_write32((void __iomem *)(RALINK_SYSCTL_BASE + 0x1340), reg1);
} else {
reg = sdr_read32((void __iomem *)(RALINK_SYSCTL_BASE + 0x3c));
reg |= 0x1e << 16;