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-rw-r--r--cfe/cfe/arch/mips/cpu/bcmcore/include/bcm4710.h58
-rw-r--r--cfe/cfe/arch/mips/cpu/bcmcore/include/bcm47xx.h8
-rw-r--r--cfe/cfe/arch/mips/cpu/bcmcore/include/bcmnvram.h123
-rwxr-xr-xcfe/cfe/arch/mips/cpu/bcmcore/include/cpu_config.h62
-rw-r--r--cfe/cfe/arch/mips/cpu/bcmcore/include/sbmips.h670
-rw-r--r--cfe/cfe/arch/mips/cpu/bcmcore/include/sbsdram.h92
-rwxr-xr-xcfe/cfe/arch/mips/cpu/bcmcore/src/Makefile8
-rwxr-xr-xcfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_arena.c170
-rwxr-xr-xcfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_cpuinit.S490
-rwxr-xr-xcfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_l1cache.S219
10 files changed, 1900 insertions, 0 deletions
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm4710.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm4710.h
new file mode 100644
index 0000000..f499bc9
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm4710.h
@@ -0,0 +1,58 @@
+/*
+ Copyright 2001, Broadcom Corporation
+ All Rights Reserved.
+
+ This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
+ the contents of this file may not be disclosed to third parties, copied or
+ duplicated in any form, in whole or in part, without the prior written
+ permission of Broadcom Corporation.
+*/
+/*
+ * BCM4710 address space map and definitions
+ *
+ * Think twice before adding to this file, this is not the kitchen sink
+ * These definitions are not guaranteed for all 47xx chips, only the 4710
+ *
+ * Copyright (C) 2000 Broadcom Corporation
+ * $Id: bcm4710.h,v 1.1 2001/10/31 18:49:25 mpl Exp $
+ */
+
+#ifndef _bcm4710_h_
+#define _bcm4710_h_
+
+/* Address map */
+#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
+#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
+#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
+#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
+#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
+#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
+
+/* Core register space */
+#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
+#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
+#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
+#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
+#define BCM4710_REG_USB 0x18004000 /* USB core registers */
+#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
+#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
+#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
+#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
+
+#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
+#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
+
+#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
+
+#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
+#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
+
+#ifdef CONFIG_VSIM
+#define BCM4710_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); } while (0)
+#else
+#define BCM4710_TRACE(trval) do { *((unsigned char *)KSEG1ADDR(BCM4710_LED)) = (trval); \
+ *((int *)0xa0002ff8) = (trval); } while (0)
+#endif
+
+
+#endif /* _bcm4710_h_ */
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm47xx.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm47xx.h
new file mode 100644
index 0000000..eb752e5
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcm47xx.h
@@ -0,0 +1,8 @@
+#ifndef _BCM47XX_H
+#define _BCM47XX_H
+
+/* uart defaults */
+#define DIV_LO 0x36
+#define DIV_HI 0
+
+#endif
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/bcmnvram.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcmnvram.h
new file mode 100644
index 0000000..b9d37e6
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/bcmnvram.h
@@ -0,0 +1,123 @@
+/*
+ Copyright 2001, Broadcom Corporation
+ All Rights Reserved.
+
+ This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
+ the contents of this file may not be disclosed to third parties, copied or
+ duplicated in any form, in whole or in part, without the prior written
+ permission of Broadcom Corporation.
+*/
+/*
+ * NVRAM variable manipulation
+ *
+ * Copyright (C) 2001 Broadcom Corporation
+ *
+ * $Id: bcmnvram.h,v 1.1 2001/10/31 18:49:25 mpl Exp $
+ */
+
+#ifndef _bcmnvram_h_
+#define _bcmnvram_h_
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+struct nvram_header {
+ unsigned long magic;
+ unsigned long len;
+ unsigned long crc_ver_init; /* 0:7 crc, 8:15 ver, 16:27 init, mem. test 28, 29-31 reserved */
+ unsigned long config_refresh; /* 0:15 config, 16:31 refresh */
+ unsigned long reserved;
+};
+
+struct nvram_tuple {
+ char *name;
+ char *value;
+ struct nvram_tuple *next;
+};
+
+/* Compatibility */
+typedef struct nvram_tuple EnvRec;
+
+/*
+ * Get the value of an NVRAM variable
+ * @param name name of variable to get
+ * @return value of variable or NULL if undefined
+ */
+extern char * nvram_get(const char *name);
+
+/*
+ * Get the value of an NVRAM variable
+ * @param name name of variable to get
+ * @return value of variable or NUL if undefined
+ */
+#define nvram_safe_get(name) (nvram_get(name) ? : "")
+
+/*
+ * Match an NVRAM variable
+ * @param name name of variable to match
+ * @param match value to compare against value of variable
+ * @return TRUE if variable is defined and its value is string equal to match or FALSE otherwise
+ */
+#define nvram_match(name, match) ({ \
+ const char *value = nvram_get(name); \
+ (value && !strcmp(value, match)); \
+})
+
+/*
+ * Match an NVRAM variable
+ * @param name name of variable to match
+ * @param match value to compare against value of variable
+ * @return TRUE if variable is defined and its value is not string equal to invmatch or FALSE otherwise
+ */
+#define nvram_invmatch(name, invmatch) ({ \
+ const char *value = nvram_get(name); \
+ (value && strcmp(value, invmatch)); \
+})
+
+/*
+ * Set the value of an NVRAM variable
+ * @param name name of variable to set
+ * @param value value of variable
+ * @return 0 on success and errno on failure
+ * NOTE: use nvram_commit to commit this change to flash.
+ */
+extern int nvram_set(const char *name, const char *value);
+
+/*
+ * Unset an NVRAM variable
+ * @param name name of variable to unset
+ * @return 0 on success and errno on failure
+ * NOTE: use nvram_commit to commit this change to flash.
+ */
+extern int nvram_unset(const char *name);
+
+/*
+ * Permanently commit NVRAM variables
+ * @return 0 on success and errno on failure
+ */
+extern int nvram_commit(void);
+
+/*
+ * Get all NVRAM variables (format name=value\0 ... \0\0)
+ * @param buf buffer to store variables
+ * @param count size of buffer in bytes
+ * @return 0 on success and errno on failure
+ */
+extern int nvram_getall(char *buf, int count);
+
+/*
+ * Invalidate the current NVRAM header
+ * @return 0 on success and errno on failure
+ */
+extern int nvram_invalidate(void);
+
+#endif /* _LANGUAGE_ASSEMBLY */
+
+#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
+#define NVRAM_VERSION 1
+#define NVRAM_HEADER_SIZE 20
+#define NVRAM_FIRST_LOC 0xbfcf8000
+#define NVRAM_LAST_LOC 0xbfff8000
+#define NVRAM_LOC_GAP 0x100000
+#define NVRAM_SPACE 0x8000
+
+#endif /* _bcmnvram_h_ */
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/cpu_config.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/cpu_config.h
new file mode 100755
index 0000000..51cf4e1
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/cpu_config.h
@@ -0,0 +1,62 @@
+/* *********************************************************************
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * CPU Configuration file File: cpu_config.h
+ *
+ * This file contains the names of the routines to be used
+ * in the dispatch table in init_mips.S
+ *
+ * It lives here in the CPU directory so we can direct
+ * the init calls to routines named in this directory.
+ *
+ * Author: Mitch Lichtenberg (mpl@broadcom.com)
+ *
+ *********************************************************************
+ *
+ * XX Copyright 2000,2001
+ * Broadcom Corporation. All rights reserved.
+ *
+ * BROADCOM PROPRIETARY AND CONFIDENTIAL
+ *
+ * This software is furnished under license and may be used and
+ * copied only in accordance with the license.
+ ********************************************************************* */
+
+/*
+ */
+
+#define CPUCFG_CPUINIT bcmcore_cpuinit
+#define CPUCFG_ALTCPU_START1 bcmcore_null
+#define CPUCFG_ALTCPU_START2 bcmcore_null
+#define CPUCFG_ALTCPU_RESET bcmcore_null
+#define CPUCFG_CPURESTART bcmcore_cpurestart
+#define CPUCFG_DRAMINIT board_draminit /* no dram on CPU */
+#define CPUCFG_CACHEOPS bcmcore_cacheops
+#define CPUCFG_ARENAINIT bcmcore_arena_init
+#define CPUCFG_PAGETBLINIT bcmcore_pagetable_init
+#define CPUCFG_TLBHANDLER bcmcore_tlbhandler
+#define CPUCFG_DIAG_TEST1 bcmcore_null
+#define CPUCFG_DIAG_TEST2 bcmcore_null
+#if CFG_CMT
+#define CPUCFG_TP1_SWITCH bcmcore_tp1_switch
+#else
+#define CPUCFG_TP1_SWITCH bcmcore_null
+#endif
+/*
+ * The BCMCORE ticks CP0 every other cycle.
+ */
+
+#define CPUCFG_CYCLESPERCPUTICK 2
+
+/*
+ * Hazard macro
+ */
+
+#define HAZARD nop ; nop ; nop ; nop ; nop ; nop ; nop
+#define ERET \
+ .set push ; \
+ .set mips4 ; \
+ eret ; \
+ .set pop
+
+
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/sbmips.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/sbmips.h
new file mode 100644
index 0000000..0f4e055
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/sbmips.h
@@ -0,0 +1,670 @@
+/* *********************************************************************
+ * SB1250 Board Support Package
+ *
+ * MIPS64 CPU definitions File: sbmips.h
+ *
+ * This module contains constants and macros specific to the
+ * SB1 MIPS64 core.
+ *
+ * Author: Mitch Lichtenberg (mitch@sibyte.com)
+ *
+ *********************************************************************
+ *
+ * Copyright 2000,2001,2002,2003
+ * Broadcom Corporation. All rights reserved.
+ *
+ * This software is furnished under license and may be used and
+ * copied only in accordance with the following terms and
+ * conditions. Subject to these conditions, you may download,
+ * copy, install, use, modify and distribute modified or unmodified
+ * copies of this software in source and/or binary form. No title
+ * or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce
+ * and retain this copyright notice and list of conditions
+ * as they appear in the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or
+ * logo of Broadcom Corporation. The "Broadcom Corporation"
+ * name may not be used to endorse or promote products derived
+ * from this software without the prior written permission of
+ * Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+ * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
+ * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
+ * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ ********************************************************************* */
+
+#ifndef _SB_MIPS_H
+#define _SB_MIPS_H
+
+/* *********************************************************************
+ * Configure language
+ ********************************************************************* */
+
+#if defined(__ASSEMBLER__)
+#define _ATYPE_
+#define _ATYPE32_
+#define _ATYPE64_
+#else
+#define _ATYPE_ (__SIZE_TYPE__)
+#define _ATYPE32_ (int)
+#define _ATYPE64_ (long long)
+#endif
+
+
+/* *********************************************************************
+ * Bitfield macros
+ ********************************************************************* */
+
+/*
+ * Make a mask for 1 bit at position 'n'
+ */
+
+#define _MM_MAKEMASK1(n) (1 << (n))
+
+/*
+ * Make a mask for 'v' bits at position 'n'
+ */
+
+#define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n))
+
+/*
+ * Make a value at 'v' at bit position 'n'
+ */
+
+#define _MM_MAKEVALUE(v,n) ((v) << (n))
+
+/*
+ * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits
+ */
+
+#define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n))
+
+
+
+/* *********************************************************************
+ * 32-bit MIPS Address Spaces
+ ********************************************************************* */
+
+#ifdef __ASSEMBLER__
+#define _ACAST32_
+#define _ACAST64_
+#else
+#define _ACAST32_ _ATYPE_ _ATYPE32_ /* widen if necessary */
+#define _ACAST64_ _ATYPE64_ /* do _not_ narrow */
+#endif
+
+/* 32-bit address map */
+#define UBASE 0x00000000 /* user+ mapped */
+#define USIZE 0x80000000
+#define K0BASE (_ACAST32_ 0x80000000) /* kernel unmapped cached */
+#define K0SIZE 0x20000000
+#define K1BASE (_ACAST32_ 0xa0000000) /* kernel unmapped uncached */
+#define K1SIZE 0x20000000
+#define KSBASE (_ACAST32_ 0xc0000000) /* supervisor+ mapped */
+#define KSSIZE 0x20000000
+#define K3BASE (_ACAST32_ 0xe0000000) /* kernel mapped */
+#define K3SIZE 0x20000000
+
+/* 64-bit address map additions to the above (sign-extended) ranges */
+#define XUBASE (_ACAST64_ 0x0000000080000000) /* user+ mapped */
+#define XUSIZE (_ACAST64_ 0x00000FFF80000000)
+#define XSSEGBASE (_ACAST64_ 0x4000000000000000) /* supervisor+ mapped */
+#define XSSEGSIZE (_ACAST64_ 0x0000100000000000)
+#define XKPHYSBASE (_ACAST64_ 0x8000000000000000) /* kernel unmapped */
+#define XKPHYSSIZE (_ACAST64_ 0x0000100000000000)
+#define XKSEGBASE (_ACAST64_ 0xC000000000000000) /* kernel mapped */
+#define XKSEGSIZE (_ACAST64_ 0x00000FFF80000000)
+
+#define GEN_VECT (_ACAST32_ 0x80000080)
+#define UTLB_VECT (_ACAST32_ 0x80000000)
+
+/* *********************************************************************
+ * Address space coercion macros
+ ********************************************************************* */
+
+#define PHYS_TO_K0(pa) (K0BASE | (pa))
+#define PHYS_TO_K1(pa) (K1BASE | (pa))
+#define K0_TO_PHYS(va) ((va) & (K0SIZE-1))
+#define K1_TO_PHYS(va) ((va) & (K1SIZE-1))
+#define K0_TO_K1(va) ((va) | K1SIZE)
+#define K1_TO_K0(va) ((va) & ~K1SIZE)
+
+#define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p)))
+#define XK1_TO_PHYS(p) ((p) & (K1SIZE-1))
+#define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p))
+#define PHYS_TO_XKSEG_UNCACHED(p) PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
+#define PHYS_TO_XKSEG_CACHED(p) PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
+#define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(0,59))
+
+
+#if !defined(__ASSEMBLER__)
+#define mips_wbflush() __asm__ __volatile__ ("sync" : : : "memory")
+#define ISK0SEG(va) ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1))
+#define ISK1SEG(va) ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1))
+#endif
+
+/* *********************************************************************
+ * Register aliases
+ ********************************************************************* */
+
+#if defined(__ASSEMBLER__)
+#define zero $0
+#define AT $1 /* assembler temporaries */
+#define v0 $2 /* value holders */
+#define v1 $3
+#define a0 $4 /* arguments */
+#define a1 $5
+#define a2 $6
+#define a3 $7
+#define t0 $8 /* temporaries */
+#define t1 $9
+#define t2 $10
+#define t3 $11
+#define t4 $12
+#define t5 $13
+#define t6 $14
+#define t7 $15
+#define ta0 $12
+#define ta1 $13
+#define ta2 $14
+#define ta3 $15
+#define s0 $16 /* saved registers */
+#define s1 $17
+#define s2 $18
+#define s3 $19
+#define s4 $20
+#define s5 $21
+#define s6 $22
+#define s7 $23
+#define t8 $24 /* temporaries */
+#define t9 $25
+#define k0 $26 /* kernel registers */
+#define k1 $27
+#define gp $28 /* global pointer */
+#define sp $29 /* stack pointer */
+#define s8 $30 /* saved register */
+#define fp $30 /* frame pointer */
+#define ra $31 /* return address */
+#endif
+
+/* *********************************************************************
+ * CP0 Registers
+ ********************************************************************* */
+
+#if defined(__ASSEMBLER__)
+#define C0_INX $0 /* CP0: TLB Index */
+#define C0_RAND $1 /* CP0: TLB Random */
+#define C0_TLBLO0 $2 /* CP0: TLB EntryLo0 */
+#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
+#define C0_TLBLO1 $3 /* CP0: TLB EntryLo1 */
+#define C0_CTEXT $4 /* CP0: Context */
+#define C0_PGMASK $5 /* CP0: TLB PageMask */
+#define C0_WIRED $6 /* CP0: TLB Wired */
+#define C0_BADVADDR $8 /* CP0: Bad Virtual Address */
+#define C0_COUNT $9 /* CP0: Count */
+#define C0_TLBHI $10 /* CP0: TLB EntryHi */
+#define C0_COMPARE $11 /* CP0: Compare */
+#define C0_SR $12 /* CP0: Processor Status */
+#define C0_STATUS C0_SR /* CP0: Processor Status */
+#define C0_CAUSE $13 /* CP0: Exception Cause */
+#define C0_EPC $14 /* CP0: Exception PC */
+#define C0_PRID $15 /* CP0: Processor Revision Indentifier */
+#define C0_CONFIG $16 /* CP0: Config */
+#define C0_LLADDR $17 /* CP0: LLAddr */
+#define C0_WATCHLO $18 /* CP0: WatchpointLo */
+#define C0_WATCHHI $19 /* CP0: WatchpointHi */
+#define C0_XCTEXT $20 /* CP0: XContext */
+#define C0_ECC $26 /* CP0: ECC */
+#define C0_CACHEERR $27 /* CP0: CacheErr */
+#define C0_TAGLO $28 /* CP0: TagLo */
+#define C0_TAGHI $29 /* CP0: TagHi */
+#define C0_ERREPC $30 /* CP0: ErrorEPC */
+#else
+#define C0_INX 0 /* CP0: TLB Index */
+#define C0_RAND 1 /* CP0: TLB Random */
+#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
+#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
+#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
+#define C0_CTEXT 4 /* CP0: Context */
+#define C0_PGMASK 5 /* CP0: TLB PageMask */
+#define C0_WIRED 6 /* CP0: TLB Wired */
+#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
+#define C0_COUNT 9 /* CP0: Count */
+#define C0_TLBHI 10 /* CP0: TLB EntryHi */
+#define C0_COMPARE 11 /* CP0: Compare */
+#define C0_SR 12 /* CP0: Processor Status */
+#define C0_STATUS C0_SR /* CP0: Processor Status */
+#define C0_CAUSE 13 /* CP0: Exception Cause */
+#define C0_EPC 14 /* CP0: Exception PC */
+#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
+#define C0_CONFIG 16 /* CP0: Config */
+#define C0_LLADDR 17 /* CP0: LLAddr */
+#define C0_WATCHLO 18 /* CP0: WatchpointLo */
+#define C0_WATCHHI 19 /* CP0: WatchpointHi */
+#define C0_XCTEXT 20 /* CP0: XContext */
+#define C0_ECC 26 /* CP0: ECC */
+#define C0_CACHEERR 27 /* CP0: CacheErr */
+#define C0_TAGLO 28 /* CP0: TagLo */
+#define C0_TAGHI 29 /* CP0: TagHi */
+#define C0_ERREPC 30 /* CP0: ErrorEPC */
+#endif
+
+/* *********************************************************************
+ * CP1 (floating point) control registers
+ ********************************************************************* */
+
+#define FPA_IRR 0 /* CP1: Implementation/Revision */
+#define FPA_CSR 31 /* CP1: Control/Status */
+
+/* *********************************************************************
+ * Macros for generating assembly language routines
+ ********************************************************************* */
+
+#if defined(__ASSEMBLER__)
+
+/* global leaf function (does not call other functions) */
+#define LEAF(name) \
+ .globl name; \
+ .ent name; \
+name:
+
+/* global alternate entry to (local or global) leaf function */
+#define XLEAF(name) \
+ .globl name; \
+ .aent name; \
+name:
+
+/* end of a global function */
+#define END(name) \
+ .size name,.-name; \
+ .end name
+
+/* local leaf function (does not call other functions) */
+#define SLEAF(name) \
+ .ent name; \
+name:
+
+/* local alternate entry to (local or global) leaf function */
+#define SXLEAF(name) \
+ .aent name; \
+name:
+
+/* end of a local function */
+#define SEND(name) \
+ END(name)
+
+/* define & export a symbol */
+#define EXPORT(name) \
+ .globl name; \
+name:
+
+/* import a symbol */
+#define IMPORT(name, size) \
+ .extern name,size
+
+/* define a zero-fill common block (BSS if not overridden) with a global name */
+#define COMM(name,size) \
+ .comm name,size
+
+/* define a zero-fill common block (BSS if not overridden) with a local name */
+#define LCOMM(name,size) \
+ .lcomm name,size
+
+#endif
+
+
+/* Floating-Point Control register bits */
+#define CSR_C 0x00800000
+#define CSR_EXC 0x0003f000
+#define CSR_EE 0x00020000
+#define CSR_EV 0x00010000
+#define CSR_EZ 0x00008000
+#define CSR_EO 0x00004000
+#define CSR_EU 0x00002000
+#define CSR_EI 0x00001000
+#define CSR_TV 0x00000800
+#define CSR_TZ 0x00000400
+#define CSR_TO 0x00000200
+#define CSR_TU 0x00000100
+#define CSR_TI 0x00000080
+#define CSR_SV 0x00000040
+#define CSR_SZ 0x00000020
+#define CSR_SO 0x00000010
+#define CSR_SU 0x00000008
+#define CSR_SI 0x00000004
+#define CSR_RM 0x00000003
+
+/* Status Register */
+#define M_SR_CUMASK _MM_MAKEMASK(4,28) /* coprocessor usable bits */
+#define M_SR_CU3 _MM_MAKEMASK1(31) /* coprocessor 3 usable */
+#define M_SR_CU2 _MM_MAKEMASK1(30) /* coprocessor 2 usable */
+#define M_SR_CU1 _MM_MAKEMASK1(29) /* coprocessor 1 usable */
+#define M_SR_CU0 _MM_MAKEMASK1(28) /* coprocessor 0 usable */
+
+#define M_SR_RP _MM_MAKEMASK1(27) /* reduced power mode */
+#define M_SR_FR _MM_MAKEMASK1(26) /* fpu regs any data */
+#define M_SR_RE _MM_MAKEMASK1(25) /* reverse endian */
+#define M_SR_MX _MM_MAKEMASK1(24) /* MDMX */
+#define M_SR_PX _MM_MAKEMASK1(23) /* 64-bit ops in user mode */
+#define M_SR_BEV _MM_MAKEMASK1(22) /* boot exception vectors */
+#define M_SR_TS _MM_MAKEMASK1(21) /* TLB is shut down */
+#define M_SR_SR _MM_MAKEMASK1(20) /* soft reset */
+#define M_SR_NMI _MM_MAKEMASK1(19) /* nonmaskable interrupt */
+
+#define M_SR_IMASK _MM_MAKEMASK(8,8) /* all interrupt mask bits */
+
+#define M_SR_IBIT8 _MM_MAKEMASK1(15) /* individual bits */
+#define M_SR_IBIT7 _MM_MAKEMASK1(14)
+#define M_SR_IBIT6 _MM_MAKEMASK1(13)
+#define M_SR_IBIT5 _MM_MAKEMASK1(12)
+#define M_SR_IBIT4 _MM_MAKEMASK1(11)
+#define M_SR_IBIT3 _MM_MAKEMASK1(10)
+#define M_SR_IBIT2 _MM_MAKEMASK1(9)
+#define M_SR_IBIT1 _MM_MAKEMASK1(8)
+
+#define M_SR_IMASK8 0 /* masks for nested int levels */
+#define M_SR_IMASK7 _MM_MAKEMASK(1,15)
+#define M_SR_IMASK6 _MM_MAKEMASK(2,14)
+#define M_SR_IMASK5 _MM_MAKEMASK(3,13)
+#define M_SR_IMASK4 _MM_MAKEMASK(4,12)
+#define M_SR_IMASK3 _MM_MAKEMASK(5,11)
+#define M_SR_IMASK2 _MM_MAKEMASK(6,10)
+#define M_SR_IMASK1 _MM_MAKEMASK(7,9)
+#define M_SR_IMASK0 _MM_MAKEMASK(8,8)
+
+#define M_SR_KX _MM_MAKEMASK1(7) /* 64-bit access for kernel */
+#define M_SR_SX _MM_MAKEMASK1(6) /* .. for supervisor */
+#define M_SR_UX _MM_MAKEMASK1(5) /* .. for user */
+
+#define S_SR_KSU 3 /* base operating mode mode */
+#define M_SR_KSU _MM_MAKEMASK(2,S_SR_KSU)
+#define V_SR_KSU(x) _MM_MAKEVALUE(x,S_SR_KSU)
+#define G_SR_KSU(x) _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU)
+#define K_SR_KSU_KERNEL 0
+#define K_SR_KSU_SUPR 1
+#define K_SR_KSU_USER 2
+
+#define M_SR_UM _MM_MAKEMASK1(4)
+#define M_SR_ERL _MM_MAKEMASK1(2)
+#define M_SR_EXL _MM_MAKEMASK1(1)
+#define M_SR_IE _MM_MAKEMASK1(0)
+
+/*
+ * Cause Register
+ */
+#define M_CAUSE_BD _MM_MAKEMASK1(31) /* exception in BD slot */
+
+#define S_CAUSE_CE 28 /* coprocessor error */
+#define M_CAUSE_CE _MM_MAKEMASK(2,S_CAUSE_CE)
+#define V_CAUSE_CE(x) _MM_MAKEVALUE(x,S_CAUSE_CE)
+#define G_CAUSE_CE(x) _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE)
+
+#define M_CAUSE_IV _MM_MAKEMASK1(23) /* special interrupt */
+#define M_CAUSE_WP _MM_MAKEMASK1(22) /* watch interrupt deferred */
+
+#define S_CAUSE_IPMASK 8
+#define M_CAUSE_IPMASK _MM_MAKEMASK(8,S_CAUSE_IPMASK)
+#define M_CAUSE_IP8 _MM_MAKEMASK1(15) /* hardware interrupts */
+#define M_CAUSE_IP7 _MM_MAKEMASK1(14)
+#define M_CAUSE_IP6 _MM_MAKEMASK1(13)
+#define M_CAUSE_IP5 _MM_MAKEMASK1(12)
+#define M_CAUSE_IP4 _MM_MAKEMASK1(11)
+#define M_CAUSE_IP3 _MM_MAKEMASK1(10)
+#define M_CAUSE_SW2 _MM_MAKEMASK1(9) /* software interrupts */
+#define M_CAUSE_SW1 _MM_MAKEMASK1(8)
+
+#define S_CAUSE_EXC 2
+#define M_CAUSE_EXC _MM_MAKEMASK(5,S_CAUSE_EXC)
+#define V_CAUSE_EXC(x) _MM_MAKEVALUE(x,S_CAUSE_EXC)
+#define G_CAUSE_EXC(x) _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC)
+
+/* Exception Code */
+#define K_CAUSE_EXC_INT 0 /* External interrupt */
+#define K_CAUSE_EXC_MOD 1 /* TLB modification */
+#define K_CAUSE_EXC_TLBL 2 /* TLB miss (Load or Ifetch) */
+#define K_CAUSE_EXC_TLBS 3 /* TLB miss (Save) */
+#define K_CAUSE_EXC_ADEL 4 /* Address error (Load or Ifetch) */
+#define K_CAUSE_EXC_ADES 5 /* Address error (Save) */
+#define K_CAUSE_EXC_IBE 6 /* Bus error (Ifetch) */
+#define K_CAUSE_EXC_DBE 7 /* Bus error (data load or store) */
+#define K_CAUSE_EXC_SYS 8 /* System call */
+#define K_CAUSE_EXC_BP 9 /* Break point */
+#define K_CAUSE_EXC_RI 10 /* Reserved instruction */
+#define K_CAUSE_EXC_CPU 11 /* Coprocessor unusable */
+#define K_CAUSE_EXC_OVF 12 /* Arithmetic overflow */
+#define K_CAUSE_EXC_TRAP 13 /* Trap exception */
+#define K_CAUSE_EXC_VCEI 14 /* Virtual Coherency Exception (I) */
+#define K_CAUSE_EXC_FPE 15 /* Floating Point Exception */
+#define K_CAUSE_EXC_CP2 16 /* Cp2 Exception */
+#define K_CAUSE_EXC_WATCH 23 /* Watchpoint exception */
+#define K_CAUSE_EXC_VCED 31 /* Virtual Coherency Exception (D) */
+
+#define K_NTLBENTRIES 64
+
+#define HI_HALF(x) ((x) >> 16)
+#define LO_HALF(x) ((x) & 0xffff)
+
+/* FPU stuff */
+
+#if defined(__ASSEMBLER__)
+#define C1_CSR $31
+#define C1_FRID $0
+#else
+#define C1_CSR 31
+#define C1_FRID 0
+#endif
+
+#define S_FCSR_CAUSE 12
+#define M_FCSR_CAUSE _MM_MAKEMASK(5,S_FCSR_CAUSE)
+#define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE)
+#define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE)
+
+#define S_FCSR_ENABLES 7
+#define M_FCSR_ENABLES _MM_MAKEMASK(5,S_FCSR_ENABLES)
+#define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES)
+#define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES)
+
+#define S_FCSR_FLAGS 2
+#define M_FCSR_FLAGS _MM_MAKEMASK(5,S_FCSR_FLAGS)
+#define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS)
+#define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS)
+
+
+/*
+ * MIPS64 Config Register (select 0)
+ */
+#define M_CFG_CFG1 _MM_MAKEMASK1(31) /* config1 select1 is impl */
+#define M_CFG_BE _MM_MAKEMASK1(15) /* big-endian mode */
+
+#define S_CFG_AT 13 /* Architecture Type */
+#define M_CFG_AT _MM_MAKEMASK(2,S_CFG_AT)
+#define V_CFG_AT(x) _MM_MAKEVALUE(x,S_CFG_AT)
+#define G_CFG_AT(x) _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT)
+#define K_CFG_AT_MIPS32 0
+#define K_CFG_AT_MIPS64_32 1
+#define K_CFG_AT_MIPS64 2
+
+#define S_CFG_AR 10 /* Architecture Revision */
+#define M_CFG_AR _MM_MAKEMASK(3,S_CFG_AR)
+#define V_CFG_AR(x) _MM_MAKEVALUE(x,S_CFG_AR)
+#define G_CFG_AR(x) _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR)
+#define K_CFG_AR_REV1 0
+
+#define S_CFG_MMU 7 /* MMU Type */
+#define M_CFG_MMU _MM_MAKEMASK(3,S_CFG_MMU)
+#define V_CFG_MMU(x) _MM_MAKEVALUE(x,S_CFG_MMU)
+#define G_CFG_MMU(x) _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU)
+#define K_CFG_MMU_NONE 0
+#define K_CFG_MMU_TLB 1
+#define K_CFG_MMU_BAT 2
+#define K_CFG_MMU_FIXED 3
+
+#define S_CFG_K0COH 0 /* K0seg coherency */
+#define M_CFG_K0COH _MM_MAKEMASK(3,S_CFG_K0COH)
+#define V_CFG_K0COH(x) _MM_MAKEVALUE(x,S_CFG_K0COH)
+#define G_CFG_K0COH(x) _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH)
+#define K_CFG_K0COH_UNCACHED 2
+#define K_CFG_K0COH_CACHEABLE 3
+#define K_CFG_K0COH_COHERENT 5
+
+/*
+ * MIPS64 Config Register (select 1)
+ */
+
+#define M_CFG_CFG2 _MM_MAKEMASK1(31) /* config2 select2 is impl */
+
+#define S_CFG_MMUSIZE 25
+#define M_CFG_MMUSIZE _MM_MAKEMASK(6,S_CFG_MMUSIZE)
+
+#define S_CFG_IS 22
+#define M_CFG_IS _MM_MAKEMASK(3,S_CFG_IS)
+#define V_CFG_IS(x) _MM_MAKEVALUE(x,S_CFG_IS)
+#define G_CFG_IS(x) _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS)
+
+#define S_CFG_IL 19
+#define M_CFG_IL _MM_MAKEMASK(S_CFG_IL,3)
+#define V_CFG_IL(x) _MM_MAKEVALUE(x,S_CFG_IL)
+#define G_CFG_IL(x) _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL)
+
+#define S_CFG_IA 16
+#define M_CFG_IA _MM_MAKEMASK(3,S_CFG_IA)
+#define V_CFG_IA(x) _MM_MAKEVALUE(x,S_CFG_IA)
+#define G_CFG_IA(x) _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA)
+
+#define S_CFG_DS 13
+#define M_CFG_DS _MM_MAKEMASK(3,S_CFG_DS)
+#define V_CFG_DS(x) _MM_MAKEVALUE(x,S_CFG_DS)
+#define G_CFG_DS(x) _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS)
+
+#define S_CFG_DL 10
+#define M_CFG_DL _MM_MAKEMASK(3,S_CFG_DL)
+#define V_CFG_DL(x) _MM_MAKEVALUE(x,S_CFG_DL)
+#define G_CFG_DL(x) _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL)
+
+#define S_CFG_DA 7
+#define M_CFG_DA _MM_MAKEMASK(3,S_CFG_DA)
+#define V_CFG_DA(x) _MM_MAKEVALUE(x,S_CFG_DA)
+#define G_CFG_DA(x) _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA)
+
+#define M_CFG_PC _MM_MAKEMASK1(4) /* perf ctrs present */
+#define M_CFG_WR _MM_MAKEMASK1(3) /* watch regs present */
+#define M_CFG_CA _MM_MAKEMASK1(2) /* MIPS16 present */
+#define M_CFG_EP _MM_MAKEMASK1(1) /* EJTAG present */
+#define M_CFG_FP _MM_MAKEMASK1(0) /* FPU present */
+
+
+
+/*
+ * Primary Cache TagLo
+ */
+
+#define S_TAGLO_PTAG 8
+#define M_TAGLO_PTAG _MM_MAKEMASK(56,S_TAGLO_PTAG)
+
+#define S_TAGLO_PSTATE 6
+#define M_TAGLO_PSTATE _MM_MAKEMASK(2,S_TAGLO_PSTATE)
+#define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE)
+#define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE)
+#define K_TAGLO_PSTATE_INVAL 0
+#define K_TAGLO_PSTATE_SHARED 1
+#define K_TAGLO_PSTATE_CLEAN_EXCL 2
+#define K_TAGLO_PSTATE_DIRTY_EXCL 3
+
+#define M_TAGLO_LOCK _MM_MAKEMASK1(5)
+#define M_TAGLO_PARITY _MM_MAKEMASK1(0)
+
+
+/*
+ * CP0 CacheErr register
+ */
+#define M_CERR_DATA _MM_MAKEMASK1(31) /* err in D space */
+#define M_CERR_SCACHE _MM_MAKEMASK1(30) /* err in l2, not l1 */
+#define M_CERR_DERR _MM_MAKEMASK1(29) /* data error */
+#define M_CERR_TERR _MM_MAKEMASK1(28) /* tag error */
+#define M_CERR_EXTRQ _MM_MAKEMASK1(27) /* external req caused err */
+#define M_CERR_BPAR _MM_MAKEMASK1(26) /* bus parity err */
+#define M_CERR_ADATA _MM_MAKEMASK1(25) /* additional data */
+#define M_CERR_IDX _MM_MAKEMASK(22,0)
+
+
+
+/*
+ * Primary Cache operations
+ */
+#define Index_Invalidate_I 0x0 /* 0 0 */
+#define Index_Writeback_Inv_D 0x1 /* 0 1 */
+#define Index_Invalidate_SI 0x2 /* 0 2 */
+#define Index_Writeback_Inv_SD 0x3 /* 0 3 */
+#define Index_Load_Tag_I 0x4 /* 1 0 */
+#define Index_Load_Tag_D 0x5 /* 1 1 */
+#define Index_Load_Tag_SI 0x6 /* 1 2 */
+#define Index_Load_Tag_SD 0x7 /* 1 3 */
+#define Index_Store_Tag_I 0x8 /* 2 0 */
+#define Index_Store_Tag_D 0x9 /* 2 1 */
+#define Index_Store_Tag_SI 0xA /* 2 2 */
+#define Index_Store_Tag_SD 0xB /* 2 3 */
+#define Create_Dirty_Exc_D 0xD /* 3 1 */
+#define Create_Dirty_Exc_SD 0xF /* 3 3 */
+#define Hit_Invalidate_I 0x10 /* 4 0 */
+#define Hit_Invalidate_D 0x11 /* 4 1 */
+#define Hit_Invalidate_SI 0x12 /* 4 2 */
+#define Hit_Invalidate_SD 0x13 /* 4 3 */
+#define Fill_I 0x14 /* 5 0 */
+#define Hit_Writeback_Inv_D 0x15 /* 5 1 */
+#define Hit_Writeback_Inv_SD 0x17 /* 5 3 */
+#define Hit_Writeback_I 0x18 /* 6 0 */
+#define Hit_Writeback_D 0x19 /* 6 1 */
+#define Hit_Writeback_SD 0x1B /* 6 3 */
+#define Hit_Set_Virtual_SI 0x1E /* 7 2 */
+#define Hit_Set_Virtual_SD 0x1F /* 7 3 */
+
+/* Watchpoint Register */
+#define M_WATCH_PA 0xfffffff8
+#define M_WATCH_R 0x00000002
+#define M_WATCH_W 0x00000001
+
+
+/* TLB entries */
+#define M_TLBHI_ASID _MM_MAKEMASK(0,8)
+#define M_TLBHI_VPN2 _MM_MAKEMASK(27,13)
+
+#define M_TLBLO_G _MM_MAKEMASK1(0)
+#define M_TLBLO_V _MM_MAKEMASK1(1)
+#define M_TLBLO_D _MM_MAKEMASK1(2)
+
+#define S_TLBLO_CALG 3
+#define M_TLBLO_CALG _MM_MAKEMASK(3,S_TLBLO_CALG)
+#define V_TLBLO_CALG(x) _MM_MAKEVALUE(x,S_TLBLO_CALG)
+#define G_TLBLO_CALG(x) _MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG)
+
+#define K_CALG_COH_EXCL1_NOL2 0
+#define K_CALG_COH_SHRL1_NOL2 1
+#define K_CALG_UNCACHED 2
+#define K_CALG_NONCOHERENT 3
+#define K_CALG_COH_EXCL 4
+#define K_CALG_COH_SHAREABLE 5
+#define K_CALG_NOTUSED 6
+#define K_CALG_UNCACHED_ACCEL 7
+
+#define S_TLBLO_PFNMASK 6
+#define M_TLBLO_PFNMASK _MM_MAKEMASK(24,S_TLBLO_PFNMASK)
+#define V_TLBLO_PFNMASK(x) _MM_MAKEVALUE(x,S_TLBLO_PFNMASK)
+#define G_TLBLO_PFNMASK(x) _MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK)
+
+
+
+#endif /* _SB_MIPS_H */
+
+
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/include/sbsdram.h b/cfe/cfe/arch/mips/cpu/bcmcore/include/sbsdram.h
new file mode 100644
index 0000000..80e93e3
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/include/sbsdram.h
@@ -0,0 +1,92 @@
+/*
+ Copyright 2001, Broadcom Corporation
+ All Rights Reserved.
+
+ This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom Corporation;
+ the contents of this file may not be disclosed to third parties, copied or
+ duplicated in any form, in whole or in part, without the prior written
+ permission of Broadcom Corporation.
+*/
+/*
+ * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
+ *
+ * $Id: sbsdram.h,v 1.1 2001/10/31 18:49:26 mpl Exp $
+ */
+
+#ifndef _SBSDRAM_H
+#define _SBSDRAM_H
+
+#ifndef _LANGUAGE_ASSEMBLY
+
+/* Sonics side: SDRAM core registers */
+typedef volatile struct sbsdramregs {
+ uint32 initcontrol; /* Generates external SDRAM initialization sequence */
+ uint32 config; /* Initializes external SDRAM mode register */
+ uint32 refresh; /* Controls external SDRAM refresh rate */
+ uint32 pad1;
+ uint32 pad2;
+} sbsdramregs_t;
+
+#endif
+
+/* SDRAM initialization control (initcontrol) register bits */
+#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
+#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
+#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
+#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
+#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
+#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
+#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
+#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
+#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
+#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
+#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
+#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
+#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
+
+/* SDRAM configuration (config) register bits */
+#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
+#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
+#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
+#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
+#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
+#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
+
+/* SDRAM refresh control (refresh) register bits */
+#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
+#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
+
+/* SDRAM Core Init values (OCP ID 0x803) */
+
+#define SDRAM_CONFIG SDRAM_BURSTFULL
+#define SDRAM_REFRESH SDRAM_REF(0x40)
+
+#if defined(MEM1MX16_KM)
+#define SDRAM_INIT 0x009
+#elif defined(MEM1MX16X2_KM)
+#define SDRAM_INIT 0x409
+#elif defined(MEM2MX8X2_KM)
+#define SDRAM_INIT 0x809
+#elif defined(MEM2MX8X4_KM)
+#define SDRAM_INIT 0xc09
+#elif defined(MEM2MX32_KM)
+#define SDRAM_INIT 0x439
+#elif defined(MEM4MX16_KM)
+#define SDRAM_INIT 0x019
+#elif defined(MEM4MX16X2_KM)
+#define SDRAM_INIT 0x419
+#elif defined(MEM8MX8X2_KM)
+#define SDRAM_INIT 0x819
+#elif defined(MEM8MX8X4_KM)
+#define SDRAM_INIT 0xc19
+#elif defined(MEM8MX16_KM)
+#define SDRAM_INIT 0x829
+#elif defined(MEM8MX16X2_KM)
+#define SDRAM_INIT 0xc29
+#elif defined(MEM4MX32_KM)
+#define SDRAM_INIT 0x429
+#else /* DEFAULT MEM */
+#define SDRAM_INIT 0x419
+#endif
+
+#endif /* _SBSDRAM_H */
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/src/Makefile b/cfe/cfe/arch/mips/cpu/bcmcore/src/Makefile
new file mode 100755
index 0000000..76662a0
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/src/Makefile
@@ -0,0 +1,8 @@
+
+ALLOBJS += bcmcore_cpuinit.o bcmcore_l1cache.o
+ifeq ($(strip ${CFG_RAMAPP}),1)
+ALLOBJS += bcmcore_arena.o
+endif
+CFLAGS += -mips32 -D_MIPSREGS32_ -mno-abicalls -fPIC
+# CFLAGS += -mips2 -D_MIPSREGS32_
+
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_arena.c b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_arena.c
new file mode 100755
index 0000000..b368158
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_arena.c
@@ -0,0 +1,170 @@
+/* *********************************************************************
+ * Broadcom Common Firmware Environment (CFE)
+ *
+ * Physical Memory (arena) manager File: bcmcore_arena.c
+ *
+ * This module describes the physical memory available to the
+ * firmware.
+ *
+ * Author: Mitch Lichtenberg (mpl@broadcom.com)
+ *
+ *********************************************************************
+ *
+ * Copyright 2000,2001,2002,2003
+ * Broadcom Corporation. All rights reserved.
+ *
+ * This software is furnished under license and may be used and
+ * copied only in accordance with the following terms and
+ * conditions. Subject to these conditions, you may download,
+ * copy, install, use, modify and distribute modified or unmodified
+ * copies of this software in source and/or binary form. No title
+ * or ownership is transferred hereby.
+ *
+ * 1) Any source code used, modified or distributed must reproduce
+ * and retain this copyright notice and list of conditions
+ * as they appear in the source file.
+ *
+ * 2) No right is granted to use any trade name, trademark, or
+ * logo of Broadcom Corporation. The "Broadcom Corporation"
+ * name may not be used to endorse or promote products derived
+ * from this software without the prior written permission of
+ * Broadcom Corporation.
+ *
+ * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
+ * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
+ * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
+ * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
+ * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+ * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
+ * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ ********************************************************************* */
+
+#include "sbmips.h"
+
+#include "lib_types.h"
+#include "lib_string.h"
+#include "lib_queue.h"
+#include "lib_malloc.h"
+#include "lib_printf.h"
+#include "lib_arena.h"
+
+#include "cfe_error.h"
+
+#include "cfe.h"
+#include "cfe_mem.h"
+
+#include "initdata.h"
+
+#define _NOPROTOS_
+#include "cfe_boot.h"
+#undef _NOPROTOS_
+
+
+/* *********************************************************************
+ * Macros
+ ********************************************************************* */
+
+#define ARENA_RANGE(bottom,top,type) arena_markrange(&cfe_arena,(uint64_t)(bottom), \
+ (uint64_t)(top)-(uint64_t)bottom+1,(type),NULL)
+
+#define MEG (1024*1024)
+#define KB 1024
+#define PAGESIZE 4096
+#define CFE_BOOTAREA_SIZE (256*KB)
+#define CFE_BOOTAREA_ADDR 0x20000000
+
+/* *********************************************************************
+ * Globals
+ ********************************************************************* */
+
+extern arena_t cfe_arena;
+
+unsigned int mem_bootarea_start;
+unsigned int mem_bootarea_size;
+
+void bcmcore_arena_init(void);
+void bcmcore_pagetable_init(uint64_t *ptaddr,unsigned int physaddr);
+
+
+/* *********************************************************************
+ * bcmcore_arena_init()
+ *
+ * Create the initial map of physical memory
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+void bcmcore_arena_init(void)
+{
+ int64_t memleft;
+
+#if 1 /* defined(CONFIG_MIPS_BRCM) */
+ arena_init(&cfe_arena,0x0,0x0); /* 2^32 physical bytes */
+#else
+ arena_init(&cfe_arena,0x0,0x100000000); /* 2^32 physical bytes */
+#endif
+
+ /*
+ * Mark the ranges from the SB1250's memory map
+ */
+
+ ARENA_RANGE(0x0000000000,0x000FFFFFFF,MEMTYPE_DRAM_NOTINSTALLED);
+
+ /*
+ * Now, fix up the map with what is known about *this* system.
+ *
+ * Do each 256MB chunk.
+ */
+
+ memleft = ((int64_t) mem_totalsize) << 20;
+
+ arena_markrange(&cfe_arena,0x00000000,memleft,MEMTYPE_DRAM_AVAILABLE,NULL);
+
+ /*
+ * Do the boot ROM
+ */
+
+ arena_markrange(&cfe_arena,0x1FC00000,2*1024*1024,MEMTYPE_BOOTROM,NULL);
+
+}
+
+
+/* *********************************************************************
+ * BCMCORE_PAGETABLE_INIT(ptaddr,physaddr)
+ *
+ * This routine constructs the page table. 256KB is mapped
+ * starting at physical address 'physaddr' - the resulting
+ * table entries are placed at 'ptaddr'
+ *
+ * Input parameters:
+ * ptaddr - base of page table
+ * physaddr - starting physical addr of area to map
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+void bcmcore_pagetable_init(uint64_t *ptaddr,unsigned int physaddr)
+{
+ int idx;
+
+ for (idx = 0; idx < (CFE_BOOTAREA_SIZE/PAGESIZE); idx++) {
+ ptaddr[idx] = (physaddr >> 6) |
+ V_TLBLO_CALG(K_CALG_NONCOHERENT) |
+ M_TLBLO_V |
+ M_TLBLO_D;
+ physaddr += PAGESIZE;
+ }
+
+}
+
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_cpuinit.S b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_cpuinit.S
new file mode 100755
index 0000000..7c04b51
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_cpuinit.S
@@ -0,0 +1,490 @@
+/* *********************************************************************
+ * SB1250 Board Support Package
+ *
+ * CPU initialization File: bcmcore_cpuinit.S
+ *
+ * This module contains code to initialize the CPU cores.
+ *
+ * Note: all the routines in this module rely on registers only,
+ * since DRAM may not be active yet.
+ *
+ * Author: Mitch Lichtenberg (mpl@broadcom.com)
+ *
+ *********************************************************************
+ *
+ * XX Copyright 2000,2001
+ * Broadcom Corporation. All rights reserved.
+ *
+ * BROADCOM PROPRIETARY AND CONFIDENTIAL
+ *
+ * This software is furnished under license and may be used and
+ * copied only in accordance with the license.
+ ********************************************************************* */
+
+#include "sbmips.h"
+#include "exception.h"
+#include "bsp_config.h"
+#include "mipsmacros.h"
+#include "cpu_config.h" /* for ERET and HAZARD */
+
+
+ .text
+
+
+/* *********************************************************************
+ * Macros
+ ********************************************************************* */
+
+#define LINESIZE 16
+
+#define CACHEOP(cachename,op) ((cachename) | ((op) << 2))
+
+#define CACHE_OP_IDXINVAL 0
+#define CACHE_OP_IDXLOADTAG 1
+#define CACHE_OP_IDXSTORETAG 2
+#define CACHE_OP_IMPLRSVD 3
+#define CACHE_OP_HITINVAL 4
+#define CACHE_OP_FILL 5
+#define CACHE_OP_HITWRITEBACK_INVAL 5
+#define CACHE_OP_HITWRITEBACK 6
+#define CACHE_OP_FETCHLOCK 7
+
+#define L2C 3
+#define L1C_I 0
+#define L1C_D 1
+
+
+/*
+ * Duplicates from cfe_iocb.h -- warning!
+ */
+
+#define CFE_CACHE_FLUSH_D 1
+#define CFE_CACHE_INVAL_I 2
+#define CFE_CACHE_INVAL_D 4
+#define CFE_CACHE_INVAL_L2 8
+#define CFE_CACHE_FLUSH_L2 16
+#define CFE_CACHE_INVAL_RANGE 32
+#define CFE_CACHE_FLUSH_RANGE 64
+
+#define BCMCORE_NTLBENTRIES 32
+
+
+
+#define SENDCHAR(c) \
+ li t0,0xBF800000 ; \
+ li t1,c ; \
+ sb t1,0(t0)
+
+
+#define R_CPU_CP0INIT _TBLIDX(0)
+#define R_CPU_L1CINIT _TBLIDX(1)
+#define R_CPU_SETLEDS _TBLIDX(2)
+#define R_CPU_L1CFLASHD _TBLIDX(3)
+#define R_CPU_L1CINVALI _TBLIDX(4)
+
+#define SETLEDS1(a,b,c,d) \
+ li a0,(((a)<<24)|((b)<<16)|((c)<<8)|(d)) ; \
+ CALLINIT_KSEG1(cpuinit_table,R_CPU_SETLEDS)
+#define SETLEDS(a,b,c,d) \
+ li a0,(((a)<<24)|((b)<<16)|((c)<<8)|(d)) ; \
+ CALLINIT_KSEG0(cpuinit_table,R_CPU_SETLEDS)
+
+cpuinit_table:
+ _LONG_ bcmcore_cp0_init # [ 0 ] R_CPU_CP0INIT
+ _LONG_ bcmcore_l1cache_init # [ 1 ] R_CPU_L1CINIT
+ _LONG_ board_setleds # [ 2 ] R_CPU_SETLEDS
+ _LONG_ bcmcore_l1cache_flush_d # [ 3 ] R_CPU_L1CFLASHD
+ _LONG_ bcmcore_l1cache_inval_i # [ 4 ] R_CPU_L1CINVALI
+
+
+/* *********************************************************************
+ * BCMCORE_CP0_INIT()
+ *
+ * Initialize an BCMCORE CPU's CP0 registers
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * all
+ ********************************************************************* */
+
+
+LEAF(bcmcore_cp0_init)
+
+ .set noreorder
+
+ mtc0 zero,C0_WATCHLO # Watch registers.
+ mtc0 zero,C0_WATCHHI
+ mtc0 zero,C0_CAUSE # must clear before writing SR
+
+ mfc0 v0,C0_SR # Get status register
+ and v0,M_SR_SR # preserve soft reset
+#ifdef DEBUG_ENV_ICE
+ and v0,~M_SR_BEV
+#else
+ or v0,M_SR_BEV # exceptions to boot vector
+#endif
+ mtc0 v0,C0_SR # set up the status register
+
+
+ mfc0 v0,C0_CONFIG # get current CONFIG register
+ srl v0,v0,3 # strip out K0 bits
+ sll v0,v0,3 # k0 bits now zero
+ or v0,v0,K_CFG_K0COH_CACHEABLE # K0 is cacheable.
+ mtc0 v0,C0_CONFIG
+ nop
+
+ mtc0 zero,C0_WATCHLO # Watch registers.
+ mtc0 zero,C0_WATCHHI
+
+ mtc0 zero,C0_TLBHI # TLB entry (high half)
+ nop
+
+
+ #
+ # This is probably not the right init value for C0_COMPARE,
+ # but it seems to be necessary for the sim model right now.
+ #
+
+ li v0,-1
+ mtc0 v0,C0_COMPARE
+ nop
+
+ #
+ # Initialize all the TLB entries to some invalid value
+ #
+
+ mtc0 zero,C0_TLBLO0 /* tlblo0 = invalid */
+ nop
+ mtc0 zero,C0_TLBLO1 /* tlblo1 = invalid */
+ nop
+ mtc0 zero,C0_PGMASK /* 4K pages */
+ nop
+
+ li t0,K1BASE /* tlbhi = impossible vpn */
+ li t1,(BCMCORE_NTLBENTRIES-1) /* index */
+
+
+ nop
+1: mtc0 t0,C0_TLBHI
+ nop
+ mtc0 t1,C0_INX
+ nop
+ addu t0,0x2000 /* inc vpn */
+ tlbwi
+ bnez t1,1b
+ subu t1,1 # BDSLOT
+ .set reorder
+
+
+/*
+ * XXX What other CP0 initialization do I need?
+ */
+
+ jr ra
+
+
+END(bcmcore_cp0_init)
+
+
+/* *********************************************************************
+ * BCMCORE_CPUINIT
+ *
+ * Do initialization of the Broadcom core
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+
+LEAF(bcmcore_cpuinit)
+
+ move fp,ra
+
+ SETLEDS1('C','P','U','I')
+ CALLINIT_KSEG1(cpuinit_table,R_CPU_CP0INIT)
+
+ SETLEDS1('L','1','C','I')
+ CALLINIT_KSEG1(cpuinit_table,R_CPU_L1CINIT)
+
+ move ra,fp
+ j ra
+
+END(bcmcore_cpuinit)
+
+
+/* *********************************************************************
+ * BCMCORE_KSEG0_SWITCH
+ *
+ * Return to the address of the routine that called us, except
+ * in K0seg instead of K1seg
+ *
+ * Input parameters:
+ * nothing - ra is return address
+ *
+ * Return value:
+ * ra = same return address in K0
+ ********************************************************************* */
+
+LEAF(bcmcore_kseg0_switch)
+
+ and ra,(K0SIZE-1)
+ or ra,K0BASE
+ jr ra
+
+END(bcmcore_kseg0_switch)
+
+/* *********************************************************************
+ * BCMCORE_NULL
+ *
+ * Dummy handler for routines we don't need to implement, like
+ * the multiprocessor stuff
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * none
+ ********************************************************************* */
+
+LEAF(bcmcore_null)
+
+ j ra
+
+END(bcmcore_null)
+
+
+/* *********************************************************************
+ * BCMCORE_CPURESTART
+ *
+ * This routine is called when someone soft-exits to CFE. We
+ * reinitialize any CP0 stuff here.
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+LEAF(bcmcore_cpurestart)
+
+ j ra
+
+END(bcmcore_cpurestart)
+
+
+/* *********************************************************************
+ * BCMCORE_CACHEOPS
+ *
+ * Perform various cache operations on a BCM Core
+ *
+ * Input parameters:
+ * a0 - flag bits (CFE_CACHE_xxx)
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * t0,t1,t2,t3,v1,s0
+ ********************************************************************* */
+
+LEAF(bcmcore_cacheops)
+
+ move s0,ra
+
+ move v1,a0
+
+ /*
+ * With no flags, we flush L1D and invalid L1I
+ */
+
+ bne v1,zero,1f
+ li v1,CFE_CACHE_FLUSH_D | CFE_CACHE_INVAL_I
+1:
+
+ /*
+ * Flush the D-Cache, since the program we loaded is "data".
+ */
+
+ and a0,v1,CFE_CACHE_FLUSH_D
+ beq a0,zero,1f
+ CALLINIT_KSEG1(cpuinit_table,R_CPU_L1CFLASHD)
+1:
+
+ /*
+ * Invalidate the I-Cache, so that addresses in the program
+ * region will miss and need to be filled from the data we
+ * just flushed above.
+ */
+
+ and a0,v1,CFE_CACHE_INVAL_I
+ beq a0,zero,1f
+ CALLINIT_KSEG1(cpuinit_table,R_CPU_L1CINVALI)
+1:
+
+
+ .set push
+ .set mips32
+
+ /*
+ * Invalidate cache range
+ */
+
+ and a0,v1,CFE_CACHE_INVAL_RANGE
+ beq a0,zero,2f
+
+ move t0,a1
+1: cache CACHEOP(L1C_D,CACHE_OP_HITINVAL),0(t0)
+ add t0,LINESIZE
+ blt t0,a2,1b
+
+ /*
+ * Flush cache range
+ */
+
+
+2:
+ and a0,v1,CFE_CACHE_FLUSH_RANGE
+ beq a0,zero,2f
+
+ move t0,a1
+1: cache CACHEOP(L1C_D,CACHE_OP_HITWRITEBACK_INVAL),0(t0)
+ add t0,LINESIZE
+ blt t0,a2,1b
+
+2:
+
+ .set pop
+
+
+ move ra,s0
+ j ra
+
+END(bcmcore_cacheops)
+
+
+
+/* *********************************************************************
+ * BCMCORE_TLBHANDLER
+ *
+ * This is the TLB exception handler for the bcmcore
+ *
+ * Note: only K0 and K1 are available to us at this time.
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ ********************************************************************* */
+
+
+LEAF(bcmcore_tlbhandler)
+ .set noreorder
+ .set noat
+
+/*
+ * XXX XXX XXX XXX XXX
+ *
+ * This won't work as-is on the BCMCORE. The CONTEXT register is not
+ * wide enough! In fact, it's broken on all pre-mips4 CPUs.
+ *
+ * XXX XXX XXX XXX XXX
+ */
+
+/*
+ * This requires a bit of explanation: We only support 256KB
+ * of mapped space for the boot program. This space will be
+ * mapped from 0x2000_0000 to 0x2004_0000 to some physical
+ * memory allocated by the firmware. This is 64 pages
+ * of 4KB each.
+ *
+ * We know our BadVPN2 will be in the range
+ * 0x100000 to 0x1001F0, since the memory is mapped from
+ * 0x2000_0000 to 0x2004_0000. BadVPN2 plus the four bits
+ * of zeroes at the end are bits 31..9
+ *
+ * We also want to place the PTEbase on something other than
+ * a 16MB boundary. Each entry is 16 bytes, and there
+ * are 64 entries, so we need only 10 bits to address
+ * the entire table (it can therefore be aligned on a
+ * 1KB boundary).
+ *
+ * To make this work, we'll shift PTEbase to the right, leaving
+ * the bottom ten bits for the page number, as:
+ *
+ * Bits 31..10: PTEbase
+ * Bits 9..4: BadVPN
+ * Bits 3..0: 16 bytes for table entry
+ *
+ * Therefore:
+ * PTEbase gets shifted right 13 bits.
+ * BadVPN gets masked at 6 bits (mask is 0x3F0)
+ * The bottom 4 bits are zero.
+ *
+ * To range check the address, we can shift the Bad VPN
+ * right by 9 bits, and check for values of 0x1000 and
+ * 0x1001.
+ */
+
+
+ /*
+ * This part range checks the VPN2 field in the
+ * context register. We only handle
+ * VPN2s in the range 0x100000 to 0x1001F0
+ */
+ mfc0 k0,C0_TLBHI
+
+ mfc0 k0,C0_CTEXT # Get context
+ sra k0,8 # keep hi part
+ and k0,0x1FFF # of VPN2
+ li k1,0x1000 # 0x1000 is ok
+ beq k0,k1,1f #
+ nop # BDSLOT
+ li k1,0x1001 # 0x1001 is ok
+ beq k0,k1,1f #
+ nop # BDSLOT
+
+ li k0,XTYPE_TLBFILL # all other bits are not
+ b _exc_entry
+ nop # BDSLOT
+
+1: mfc0 k0,C0_CTEXT # Get context
+ sra k0,13 # Shift PTEbase
+ li k1,0x3FF # Generate mask to kill
+ not k1 # BadVPN2 bits
+ and k0,k1 # keep only PTEBase part.
+
+ mfc0 k1,C0_CTEXT # Get Context
+ and k1,0x3F0 # Keep only BadVPN2 bits
+ or k1,k0 # Replace PTEBase
+
+ ld k0,0(k1) # Load entrylo0
+ ld k1,8(k1) # Load entrylo1
+ mtc0 k0,C0_TLBLO0 # and write to CP0
+ mtc0 k1,C0_TLBLO1
+ tlbwr # put it in the TLB
+ ERET
+ nop
+
+ .set reorder
+ .set at
+
+END(bcmcore_tlbhandler)
+
+
+/* *********************************************************************
+ * End
+ ********************************************************************* */
+
diff --git a/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_l1cache.S b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_l1cache.S
new file mode 100755
index 0000000..fa39bfd
--- /dev/null
+++ b/cfe/cfe/arch/mips/cpu/bcmcore/src/bcmcore_l1cache.S
@@ -0,0 +1,219 @@
+/* *********************************************************************
+ * SB1250 Board Support Package
+ *
+ * L1C initialization File: bcmcore_l1cache.S
+ *
+ * This module contains code to initialize the CPU's caches
+ *
+ * Note: all the routines in this module rely on registers only,
+ * since DRAM may not be active yet.
+ *
+ * Author: Mitch Lichtenberg (mpl@broadcom.com)
+ *
+ *********************************************************************
+ *
+ * XX Copyright 2000,2001
+ * Broadcom Corporation. All rights reserved.
+ *
+ * BROADCOM PROPRIETARY AND CONFIDENTIAL
+ *
+ * This software is furnished under license and may be used and
+ * copied only in accordance with the license.
+ ********************************************************************* */
+
+#include "sbmips.h"
+#include "bsp_config.h"
+
+ .text
+
+ .set push
+ .set mips32
+
+/* *********************************************************************
+ * Macros
+ ********************************************************************* */
+
+#define CP0_CFG_ISMSK (0x7 << 22)
+#define CP0_CFG_ISSHF 22
+#define CP0_CFG_ILMSK (0x7 << 19)
+#define CP0_CFG_ILSHF 19
+#define CP0_CFG_IAMSK (0x7 << 16)
+#define CP0_CFG_IASHF 16
+#define CP0_CFG_DSMSK (0x7 << 13)
+#define CP0_CFG_DSSHF 13
+#define CP0_CFG_DLMSK (0x7 << 10)
+#define CP0_CFG_DLSHF 10
+#define CP0_CFG_DAMSK (0x7 << 7)
+#define CP0_CFG_DASHF 7
+
+#define cacheop(kva, size, linesize, op) \
+ .set noreorder; \
+ addu t1, kva, size; \
+ subu t2, linesize, 1; \
+ not t2; \
+ and t0, kva, t2; \
+ addu t1, -1; \
+ and t1, t2; \
+10: cache op, 0(t0); \
+ bne t0, t1, 10b; \
+ addu t0, linesize; \
+11: \
+ .set reorder
+
+#define size_icache(size, linesize) \
+ mfc0 t7, C0_CONFIG, 1; \
+ and t0, t7, CP0_CFG_ILMSK; \
+ srl t0, t0, CP0_CFG_ILSHF; \
+ move linesize, zero; \
+ beq t0, zero,1f; \
+ add t0, 1; \
+ li linesize, 1; \
+ sll linesize, t0; \
+1: and t0, t7, CP0_CFG_ISMSK; \
+ srl t0, t0, CP0_CFG_ISSHF; \
+ li size, 64; \
+ sll size, t0; \
+ and t0, t7, CP0_CFG_IAMSK; \
+ srl t0, t0, CP0_CFG_IASHF; \
+ add t0, 1; \
+ mult size, t0; \
+ mflo size; \
+ mult size, linesize; \
+ mflo size
+
+#define size_dcache(size, linesize) \
+ mfc0 t7, C0_CONFIG, 1; \
+ and t0, t7, CP0_CFG_DLMSK; \
+ srl t0, t0, CP0_CFG_DLSHF; \
+ move linesize, zero; \
+ beq t0, zero,1f; \
+ add t0, 1; \
+ li linesize, 1; \
+ sll linesize, t0; \
+1: and t0, t7, CP0_CFG_DSMSK; \
+ srl t0, t0, CP0_CFG_DSSHF; \
+ li size, 64; \
+ sll size, t0; \
+ and t0, t7, CP0_CFG_DAMSK; \
+ srl t0, t0, CP0_CFG_DASHF; \
+ add t0, 1; \
+ mult size, t0; \
+ mflo size; \
+ mult size, linesize; \
+ mflo size
+
+
+/* *********************************************************************
+ * BCMCORE_L1CACHE_INIT()
+ *
+ * Initialize the L1 Cache
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * t0,t1,t2
+ ********************************************************************* */
+
+LEAF(bcmcore_l1cache_init)
+
+ mtc0 zero, C0_TAGLO # Initialize TAGLO register
+ mtc0 zero, C0_TAGLO,1 # Initialize DataLo register
+
+ li a0, K0BASE # Initialise primary instruction cache.
+ size_icache(a1, a2)
+ cacheop(a0, a1, a2, Index_Store_Tag_I)
+
+ li a0, K0BASE # Initialise primary data cache.
+ size_dcache(a1, a2)
+ cacheop(a0, a1, a2, Index_Store_Tag_D)
+
+ jr ra
+
+END(bcmcore_l1cache_init)
+
+/* *********************************************************************
+ * BCMCORE_L1CACHE_INVAL_I()
+ *
+ * Invalidate the entire ICache
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * t0,t1,t2
+ ********************************************************************* */
+LEAF(bcmcore_l1cache_inval_i)
+
+ li a0, K0BASE
+ size_icache(a1, a2)
+ cacheop(a0, a1, a2, Index_Invalidate_I)
+
+ j ra
+
+END(bcmcore_l1cache_inval_i)
+
+/* *********************************************************************
+ * BCMCORE_L1CACHE_FLUSH_D()
+ *
+ * Flush the entire DCache
+ *
+ * Input parameters:
+ * nothing
+ *
+ * Return value:
+ * nothing
+ *
+ * Registers used:
+ * t0,t1,t2
+ ********************************************************************* */
+LEAF(bcmcore_l1cache_flush_d)
+
+ li a0, K0BASE
+ size_dcache(a1, a2)
+
+# before flushing cache clear tags pointing to flash memory to avoid writes into flash
+ addu t1, a0, a1
+ subu t2, a2, 1
+ not t2
+ and t0, a0, t2
+ addu t1, -1
+ and t1, t2
+1:
+ cache Index_Load_Tag_D, 0(t0)
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ mfc0 t2, C0_TAGLO # Read TAGLO register
+ and t2, 0x1f000000 # check address
+ li t3, 0x1f000000
+ bne t2, t3, 2f
+ mtc0 zero, C0_TAGLO
+ cache Index_Store_Tag_D, 0(t0) # Reset tag for flash memory locations
+2:
+ .set noreorder;
+ bne t0, t1, 1b
+ addu t0, a2
+ .set reorder
+
+ cacheop(a0, a1, a2, Index_Writeback_Inv_D)
+
+ j ra
+
+END(bcmcore_l1cache_flush_d)
+
+ .set pop
+
+/* *********************************************************************
+ * End
+ ********************************************************************* */
+
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