CFE from danitool [without hostTools dir]: https://mega.nz/#!mwZyFK7a!CPT3BKC8dEw29kubtdYxhB91G9vIIismTkgzQ3iUy3k

25 files changed, 8331 insertions, 0 deletions

diff --git a/shared/opensource/include/bcm963xx/6328_cpu.h b/shared/opensource/include/bcm963xx/6328_cpu.h
new file mode 100755
index 0000000..8dfef4c
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6328_cpu.h
@@ -0,0 +1,150 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6328_CPU_H
+#define __BCM6328_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+#************************************************************************
+#* Coprocessor 0 Register Names
+#************************************************************************
+*/
+#define C0_BCM_CONFIG          $22
+
+/*
+# Select 1
+#  Bit  31:   unused
+#  Bits 30:25 MMU Size (Num TLB entries-1)
+#  Bits 24:22 ICache sets/way (2^n * 64)
+#  Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
+#  Bits 18:16 ICache Associativity (n+1) way                    
+#  Bits 15:13 DCache sets/way (2^n * 64)
+#  Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
+#  Bits 9:7   DCache Associativity (n+1) way                    
+#  Bits 6:4   unused
+#  Bit  3:    1=At least 1 watch register
+#  Bit  2:    1=MIPS16 code compression implemented
+#  Bit  1:    1=EJTAG implemented                   
+#  Bit  0:    1=FPU implemented                   
+*/
+#define CP0_CFG_ISMSK      (0x7 << 22)
+#define CP0_CFG_ISSHF      22
+#define CP0_CFG_ILMSK      (0x7 << 19)
+#define CP0_CFG_ILSHF      19
+#define CP0_CFG_IAMSK      (0x7 << 16)
+#define CP0_CFG_IASHF      16
+#define CP0_CFG_DSMSK      (0x7 << 13)
+#define CP0_CFG_DSSHF      13
+#define CP0_CFG_DLMSK      (0x7 << 10)
+#define CP0_CFG_DLSHF      10
+#define CP0_CFG_DAMSK      (0x7 << 7)
+#define CP0_CFG_DASHF      7
+
+/*
+#************************************************************************
+#* Coprocessor 0 Broadcom Config Register Bits
+#************************************************************************
+*/
+#define CP0_BCM_CFG_ICSHEN          (0x1 << 31)
+#define CP0_BCM_CFG_DCSHEN          (0x1 << 30)
+#define CP0_BCM_CFG_BTHD            (0x1 << 21)
+#define CP0_BCM_CFG_CLF             (0x1 << 20)
+#define CP0_BCM_CFG_NBK             (0x1 << 17)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Interrupt Register
+#************************************************************************
+*/
+#define CP0_CMT_XIR_4               (0x1 << 31)
+#define CP0_CMT_XIR_3               (0x1 << 30)
+#define CP0_CMT_XIR_2               (0x1 << 29)
+#define CP0_CMT_XIR_1               (0x1 << 28)
+#define CP0_CMT_XIR_0               (0x1 << 27)
+#define CP0_CMT_SIR_1               (0x1 << 16)
+#define CP0_CMT_SIR_0               (0x1 << 15)
+#define CP0_CMT_NMIR_TP1            (0x1 << 1)
+#define CP0_CMT_NMIR_TP0            (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Control Register
+#************************************************************************
+*/
+#define CP0_CMT_DSU_TP1             (0x1 << 30)
+#define CP0_CMT_TPS_SHFT            16
+#define CP0_CMT_TPS_MASK            (0xF << CP0_CMT_TPS_SHFT)
+#define CP0_CMT_PRIO_TP1            (0x1 << 5)
+#define CP0_CMT_PRIO_TP0            (0x1 << 4)
+#define CP0_CMT_RSTSE               (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Local Register
+#************************************************************************
+*/
+#define CP0_CMT_TPID                (0x1 << 31)
+
+/*
+#************************************************************************
+#* MIPS Registers
+#************************************************************************
+*/
+
+#define MIPS_BASE_BOOT  0xbfa00000
+#define MIPS_BASE       0xff400000
+
+#define MIPS_RAC_CR0    0x00        // RAC Configuration Register
+#define MIPS_RAC_CR1    0x08        // RAC Configuration Register 1
+#define RAC_FLH         (1 << 8)
+#define RAC_DPF         (1 << 6)
+#define RAC_NCH         (1 << 5)
+#define RAC_C_INV       (1 << 4)
+#define RAC_PF_D        (1 << 3)
+#define RAC_PF_I        (1 << 2)
+#define RAC_D           (1 << 1)
+#define RAC_I           (1 << 0)
+
+#define MIPS_RAC_ARR    0x04        // RAC Address Range Register
+#define RAC_UPB_SHFT    16
+#define RAC_LWB_SHFT    0
+
+#define MIPS_LMB_CR     0x1C        // LMB Control Register
+#define LMB_EN          (1 << 0)
+
+#define MIPS_SBR        0x20        // System Base Register
+
+#define MIPS_TP0_ALT_BV 0x30000
+#define MIPS_TP1_ALT_BV 0x38000
+#define ENABLE_ALT_BV   (1 << 19)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/opensource/include/bcm963xx/6328_intr.h b/shared/opensource/include/bcm963xx/6328_intr.h
new file mode 100755
index 0000000..e4197d1
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6328_intr.h
@@ -0,0 +1,120 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __6328_INTR_H
+#define __6328_INTR_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define INTERRUPT_ID_SOFTWARE_0           0
+#define INTERRUPT_ID_SOFTWARE_1           1
+
+/*=====================================================================*/
+/* BCM6328 Timer Interrupt Level Assignments                          */
+/*=====================================================================*/
+#define MIPS_TIMER_INT                  7
+
+/*=====================================================================*/
+/* Peripheral ISR Table Offset                                              */
+/*=====================================================================*/
+#define INTERNAL_ISR_TABLE_OFFSET       8
+#define INTERNAL_HIGH_ISR_TABLE_OFFSET  (INTERNAL_ISR_TABLE_OFFSET + 32)
+
+/*=====================================================================*/
+/* Logical Peripheral Interrupt IDs                                    */
+/*=====================================================================*/
+
+#define INTERRUPT_ID_NAND                (INTERNAL_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_PCM                 (INTERNAL_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_PCM_DMA_0           (INTERNAL_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_PCM_DMA_1           (INTERNAL_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_USBS                (INTERNAL_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_USB_CNTL_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_USB_CNTL_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_USB_BULK_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_USB_BULK_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_USB_ISO_RX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_USB_ISO_TX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_DG                  (INTERNAL_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_EPHY                (INTERNAL_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_EPHY_ENERGY_0_N     (INTERNAL_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_EPHY_ENERGY_1_N     (INTERNAL_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_EPHY_ENERGY_2_N     (INTERNAL_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_EPHY_ENERGY_3_N     (INTERNAL_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_EPHY_ENERGY_0       (INTERNAL_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_EPHY_ENERGY_1       (INTERNAL_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_EPHY_ENERGY_2       (INTERNAL_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_EPHY_ENERGY_3       (INTERNAL_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_XDSL                (INTERNAL_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_PCIE_EP             (INTERNAL_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_PCIE_RC             (INTERNAL_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_EXTERNAL_0          (INTERNAL_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_EXTERNAL_1          (INTERNAL_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_EXTERNAL_2          (INTERNAL_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_EXTERNAL_3          (INTERNAL_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_UART                (INTERNAL_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_HS_SPIM             (INTERNAL_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_WAKE_ON_IRQ         (INTERNAL_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_TIMER               (INTERNAL_ISR_TABLE_OFFSET + 31)
+#define INTERRUPT_ID_ENETSW_RX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_ENETSW_RX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_ENETSW_RX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_ENETSW_RX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_UART1               (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_ENETSW_SYS          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_USBH                (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_USBH20              (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_ATM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_ATM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_ATM_DMA_2           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_ATM_DMA_3           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_ATM_DMA_4           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_ATM_DMA_5           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_ATM_DMA_6           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_ATM_DMA_7           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_ATM_DMA_8           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_ATM_DMA_9           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_ATM_DMA_10          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_ATM_DMA_11          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_ATM_DMA_12          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_ATM_DMA_13          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_ATM_DMA_14          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_ATM_DMA_15          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_ATM_DMA_16          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_ATM_DMA_17          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_ATM_DMA_18          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_ATM_DMA_19          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_SAR                 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31)
+
+#define INTERRUPT_ID_LAST                INTERRUPT_ID_SAR
+
+#ifdef __cplusplus
+    }
+#endif                    
+
+#endif  /* __BCM6328_H */
+
+
diff --git a/shared/opensource/include/bcm963xx/6328_map_part.h b/shared/opensource/include/bcm963xx/6328_map_part.h
new file mode 100755
index 0000000..be199a5
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6328_map_part.h
@@ -0,0 +1,1325 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6328_MAP_H
+#define __BCM6328_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200  /* NAND registers */
+#define NAND_CACHE_BASE      0xb0000400
+#define LED_BASE             0xb0000800  /* LED control registers */
+#define HSSPIM_BASE          0xb0001000  /* High-Speed SPI registers */
+#define MISC_BASE            0xb0001800  /* Miscellaneous Registers */
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define SAR_DMA_BASE         0xb000b800  /* ATM SAR DMA control registers */
+#define PCIE_BASE            0xb0e40000
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64        IrqMask;
+    uint64        IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define ROBOSW_CLK_EN    (1 << 11)
+#define PCIE_CLK_EN      (1 << 10)
+#define HS_SPI_CLK_EN    (1 << 9)
+#define USBH_CLK_EN      (1 << 8)
+#define USBD_CLK_EN      (1 << 7)
+#define PCM_CLK_EN       (1 << 6)
+#define SAR_CLK_EN       (1 << 5)
+#define MIPS_CLK_EN      (1 << 4)
+#define ADSL_CLK_EN      (1 << 3)
+#define ADSL_AFE_EN      (1 << 2)
+#define ADSL_QPROC_EN    (1 << 1)
+#define PHYMIPS_CLK_EN   (1 << 0)
+
+    uint32        unused0;           /* (08) word 2 */
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_PCIE_HARD      (1 << 10)
+#define SOFT_RST_PCIE_EXT       (1 << 9)
+#define SOFT_RST_PCIE           (1 << 8)
+#define SOFT_RST_PCIE_CORE      (1 << 7)
+#define SOFT_RST_PCM            (1 << 6)
+#define SOFT_RST_USBH           (1 << 5)
+#define SOFT_RST_USBD           (1 << 4)
+#define SOFT_RST_SWITCH         (1 << 3)
+#define SOFT_RST_SAR            (1 << 2)
+#define SOFT_RST_EPHY           (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        unused1;            /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+
+    uint32        SoftRst;
+#define SOFT_RESET              0x00000001      // 0
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+#pragma pack(push, 4)
+typedef struct GpioControl {
+    uint32      GPIODirHi;                  /* 0 */
+    uint32      GPIODir;                    /* 4 */
+    uint32      GPIOioHi;                   /* 8 */
+    uint32      GPIOio;                     /* C */
+    uint32      unused0;                    /* 10 */
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+    uint64      PinMuxSel;                  /* 1C */
+#define SERIAL_LED_DATA     6
+#define SERIAL_LED_CLK      7
+#define INET_ACT_LED        11
+#define EPHY0_SPD_LED       17
+#define EPHY1_SPD_LED       18
+#define EPHY2_SPD_LED       19
+#define EPHY3_SPD_LED       20
+#define EPHY0_ACT_LED       25
+#define EPHY1_ACT_LED       26
+#define EPHY2_ACT_LED       27
+#define EPHY3_ACT_LED       28
+
+#define PINMUX_SERIAL_LED_DATA  ((uint64)2 << (SERIAL_LED_DATA << 1))
+#define PINMUX_SERIAL_LED_CLK   ((uint64)2 << (SERIAL_LED_CLK << 1))
+#define PINMUX_INET_ACT_LED     ((uint64)1 << (INET_ACT_LED << 1))
+#define PINMUX_EPHY0_ACT_LED    ((uint64)1 << (EPHY0_ACT_LED << 1))
+#define PINMUX_EPHY1_ACT_LED    ((uint64)1 << (EPHY1_ACT_LED << 1))
+#define PINMUX_EPHY2_ACT_LED    ((uint64)1 << (EPHY2_ACT_LED << 1))
+#define PINMUX_EPHY3_ACT_LED    ((uint64)1 << (EPHY3_ACT_LED << 1))
+
+    uint32      PinMuxSelOther;             /* 24 */
+#define SEL_USB                 12
+#define PINMUX_SEL_USB_MASK     (3 << SEL_USB)
+#define PINMUX_SEL_USB_HOST     (1 << SEL_USB)
+#define PINMUX_SEL_USB_DEV      (2 << SEL_USB)
+
+    uint32      TestControl;                /* 28 */
+    uint32      unused2;                    /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      unused3;                    /* 38 */
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define EPHY_AUTO_PWR_DOWN_EN   (1<<29)
+#define EPHY_IDDQ_FROM_PHY      (1<<28)
+#define EPHY_PLL_LOCK           (1<<27)
+#define EPHY_ATEST_25MHZ_EN     (1<<26)
+#define EPHY_PWR_DOWN_DLL       (1<<25)
+#define EPHY_PWR_DOWN_BIAS      (1<<24)
+#define EPHY_PWR_DOWN_TX_4      (1<<23)
+#define EPHY_PWR_DOWN_TX_3      (1<<22)
+#define EPHY_PWR_DOWN_TX_2      (1<<21)
+#define EPHY_PWR_DOWN_TX_1      (1<<20)
+#define EPHY_PWR_DOWN_RX_4      (1<<19)
+#define EPHY_PWR_DOWN_RX_3      (1<<18)
+#define EPHY_PWR_DOWN_RX_2      (1<<17)
+#define EPHY_PWR_DOWN_RX_1      (1<<16)
+#define EPHY_PWR_DOWN_SD_4      (1<<15)
+#define EPHY_PWR_DOWN_SD_3      (1<<14)
+#define EPHY_PWR_DOWN_SD_2      (1<<13)
+#define EPHY_PWR_DOWN_SD_1      (1<<12)
+#define EPHY_PWR_DOWN_RD_4      (1<<11)
+#define EPHY_PWR_DOWN_RD_3      (1<<10)
+#define EPHY_PWR_DOWN_RD_2      (1<<9)
+#define EPHY_PWR_DOWN_RD_1      (1<<8)
+#define EPHY_PWR_DOWN_4         (1<<7)
+#define EPHY_PWR_DOWN_3         (1<<6)
+#define EPHY_PWR_DOWN_2         (1<<5)
+#define EPHY_PWR_DOWN_1         (1<<4)
+#define EPHY_RST_4              (1<<3)
+#define EPHY_RST_3              (1<<2)
+#define EPHY_RST_2              (1<<1)
+#define EPHY_RST_1              (1<<0)
+    uint32      RoboswSwitchCtrl;           /* 40 */
+#define RSW_SPI_MODE            (1<<11)
+#define RSW_BC_SUPP_EN          (1<<10)
+#define RSW_CLK_FREQ_MASK       (3<<8)
+#define RSW_ENF_DFX_FLOW        (1<<7)
+#define RSW_ENH_DFX_FLOW        (1<<6)
+#define RSW_GRX_0_SETUP         (1<<5)
+#define RSW_GTX_0_SETUP         (1<<4)
+#define RSW_HW_FWDG_EN          (1<<3)
+#define RSW_QOS_EN              (1<<2)
+#define RSW_WD_CLR_EN           (1<<1)
+#define RSW_MII_DUMB_FWDG_EN    (1<<0)
+
+    uint32      RegFileTmCtl;               /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x0f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                4
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      unused4[6];                 /* 50 - 64 */
+    uint32      DieRevID;                   /* 68 */
+    uint32      unused5;                    /* 6c */
+    uint32      DiagSelControl;             /* 70 */
+    uint32      DiagReadBack;               /* 74 */
+    uint32      DiagReadBackHi;             /* 78 */
+    uint32      DiagMiscControl;            /* 7c */
+} GpioControl;
+#pragma pack(pop)
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    32
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? (1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define __mask(end, start)      (((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32    hs_spiGlobalCtrl;   // 0x0000
+#define HS_SPI_MOSI_IDLE        (1 << 18)
+#define HS_SPI_CLK_POLARITY      (1 << 17)
+#define HS_SPI_CLK_GATE_SSOFF       (1 << 16)
+#define HS_SPI_PLL_CLK_CTRL     (8)
+#define HS_SPI_PLL_CLK_CTRL_MASK    __mask(15, HS_SPI_PLL_CLK_CTRL)
+#define HS_SPI_SS_POLARITY      (0)
+#define HS_SPI_SS_POLARITY_MASK     __mask(7, HS_SPI_SS_POLARITY)
+
+  uint32    hs_spiExtTrigCtrl;  // 0x0004
+#define HS_SPI_TRIG_RAW_STATE   (24)
+#define HS_SPI_TRIG_RAW_STATE_MASK  __mask(31, HS_SPI_TRIG_RAW_STATE)
+#define HS_SPI_TRIG_LATCHED     (16)
+#define HS_SPI_TRIG_LATCHED_MASK    __mask(23, HS_SPI_TRIG_LATCHED)
+#define HS_SPI_TRIG_SENSE       (8)
+#define HS_SPI_TRIG_SENSE_MASK      __mask(15, HS_SPI_TRIG_SENSE)
+#define HS_SPI_TRIG_TYPE        (0)
+#define HS_SPI_TRIG_TYPE_MASK       __mask(7, HS_SPI_TRIG_TYPE)
+#define HS_SPI_TRIG_TYPE_EDGE       (0)
+#define HS_SPI_TRIG_TYPE_LEVEL      (1)
+
+  uint32    hs_spiIntStatus;    // 0x0008
+#define HS_SPI_IRQ_PING1_USER       (28)
+#define HS_SPI_IRQ_PING1_USER_MASK  __mask(31, HS_SPI_IRQ_PING1_USER)
+#define HS_SPI_IRQ_PING0_USER       (24)
+#define HS_SPI_IRQ_PING0_USER_MASK  __mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define HS_SPI_IRQ_PING1_CTRL_INV   (1 << 12)
+#define HS_SPI_IRQ_PING1_POLL_TOUT  (1 << 11)
+#define HS_SPI_IRQ_PING1_TX_UNDER   (1 << 10)
+#define HS_SPI_IRQ_PING1_RX_OVER    (1 << 9)
+#define HS_SPI_IRQ_PING1_CMD_DONE   (1 << 8)
+
+#define HS_SPI_IRQ_PING0_CTRL_INV   (1 << 4)
+#define HS_SPI_IRQ_PING0_POLL_TOUT  (1 << 3)
+#define HS_SPI_IRQ_PING0_TX_UNDER   (1 << 2)
+#define HS_SPI_IRQ_PING0_RX_OVER    (1 << 1)
+#define HS_SPI_IRQ_PING0_CMD_DONE   (1 << 0)
+
+  uint32    hs_spiIntStatusMasked;  // 0x000C
+#define HS_SPI_IRQSM__PING1_USER    (28)
+#define HS_SPI_IRQSM__PING1_USER_MASK   __mask(31, HS_SPI_IRQSM__PING1_USER)
+#define HS_SPI_IRQSM__PING0_USER    (24)
+#define HS_SPI_IRQSM__PING0_USER_MASK   __mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define HS_SPI_IRQSM__PING1_CTRL_INV    (1 << 12)
+#define HS_SPI_IRQSM__PING1_POLL_TOUT   (1 << 11)
+#define HS_SPI_IRQSM__PING1_TX_UNDER    (1 << 10)
+#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9)
+#define HS_SPI_IRQSM__PING1_CMD_DONE    (1 << 8)
+
+#define HS_SPI_IRQSM__PING0_CTRL_INV    (1 << 4)
+#define HS_SPI_IRQSM__PING0_POLL_TOUT   (1 << 3)
+#define HS_SPI_IRQSM__PING0_TX_UNDER    (1 << 2)
+#define HS_SPI_IRQSM__PING0_RX_OVER     (1 << 1)
+#define HS_SPI_IRQSM__PING0_CMD_DONE    (1 << 0)
+
+  uint32    hs_spiIntMask;      // 0x0010
+#define HS_SPI_IRQM_PING1_USER      (28)
+#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER)
+#define HS_SPI_IRQM_PING0_USER      (24)
+#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define HS_SPI_IRQM_PING1_CTRL_INV  (1 << 12)
+#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11)
+#define HS_SPI_IRQM_PING1_TX_UNDER  (1 << 10)
+#define HS_SPI_IRQM_PING1_RX_OVER   (1 << 9)
+#define HS_SPI_IRQM_PING1_CMD_DONE  (1 << 8)
+
+#define HS_SPI_IRQM_PING0_CTRL_INV  (1 << 4)
+#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3)
+#define HS_SPI_IRQM_PING0_TX_UNDER  (1 << 2)
+#define HS_SPI_IRQM_PING0_RX_OVER   (1 << 1)
+#define HS_SPI_IRQM_PING0_CMD_DONE  (1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32    hs_spiFlashCtrl;    // 0x0014
+#define HS_SPI_FCTRL_MB_ENABLE      (1 << 23)
+#define HS_SPI_FCTRL_SS_NUM         (20)
+#define HS_SPI_FCTRL_SS_NUM_MASK    __mask(22, HS_SPI_FCTRL_SS_NUM)
+#define HS_SPI_FCTRL_PROFILE_NUM    (16)
+#define HS_SPI_FCTRL_PROFILE_NUM_MASK   __mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define HS_SPI_FCTRL_DUMMY_BYTES    (10)
+#define HS_SPI_FCTRL_DUMMY_BYTES_MASK   __mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES     (8)
+#define HS_SPI_FCTRL_ADDR_BYTES_MASK    __mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES_2   (0)
+#define HS_SPI_FCTRL_ADDR_BYTES_3   (1)
+#define HS_SPI_FCTRL_ADDR_BYTES_4   (2)
+#define HS_SPI_FCTRL_READ_OPCODE    (0)
+#define HS_SPI_FCTRL_READ_OPCODE_MASK   __mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32    hs_spiFlashAddrBase;    // 0x0018
+
+  char      fill0[0x80 - 0x18];
+
+  uint32    hs_spiPP_0_Cmd;     // 0x0080
+#define HS_SPI_PP_SS_NUM        (12)
+#define HS_SPI_PP_SS_NUM_MASK       __mask(14, HS_SPI_PP_SS_NUM)
+#define HS_SPI_PP_PROFILE_NUM       (8)
+#define HS_SPI_PP_PROFILE_NUM_MASK  __mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+    uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+    uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+    uint32 fifo_status;
+    uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+    uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+    
+    uint32 signal_ctrl;
+#define	HS_SPI_ASYNC_INPUT_PATH (1 << 16)
+#define	HS_SPI_LAUNCH_RISING    (1 << 13)
+#define	HS_SPI_LATCH_RISING     (1 << 12)
+
+    uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+    uint32 polling_config;
+    uint32 polling_and_mask;
+    uint32 polling_compare;
+    uint32 polling_timeout;
+    uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+  uint32        miscSerdesCtrl;                 /* 0x0000 */
+#define SERDES_PCIE_ENABLE                      0x00000001
+#define SERDES_PCIE_EXD_ENABLE                  (1<<15)
+    
+  uint32        miscSerdesSts;                  /* 0x0004 */
+  uint32        miscIrqOutMask;                 /* 0x0008 */
+#define MISC_PCIE_EP_IRQ_MASK0                  (1<<0)
+#define MISC_PCIE_EP_IRQ_MASK1                  (1<<1)
+
+  uint32        miscMemcControl;                /* 0x000c */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE    (1<<3)
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE     (1<<2)
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE         (1<<1)
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE      (1<<0)
+
+  uint32        unused0[2];                     /* 0x0010 */
+
+  uint32        miscVregCtrl0;                  /* 0x0018 */
+#define VREG_VSEL1P2_SHIFT      0
+#define VREG_VSEL1P2_MASK       0x1f
+#define VREG_VSEL1P2_MIDDLE     0x0f
+
+  uint32        miscVregCtrl1;                  /* 0x001c */
+  uint32        miscVregCtrl2;                  /* 0x0020 */
+  uint32        miscLedXorReg;                  /* 0x0024 */
+  uint32        miscExtra2ChipIrqMask;          /* 0x0028 */
+  uint32        miscExtra2ChipIrqStatus;        /* 0x002c */
+  uint32        miscExtra2ChipIrqMask1;         /* 0x0030 */
+  uint32        miscExtra2ChipIrqStatus1;       /* 0x0034 */
+  uint32        miscDdrPllTestCtrl;             /* 0x0038 */
+  uint32        miscPadCtrlLow;                 /* 0x003c */
+  uint32        miscPadCtrlHigh;                /* 0x0040 */
+#define MISC_MII_SEL_SHIFT      30
+#define MISC_MII_SEL_3P3V       0
+#define MISC_MII_SEL_2P5V       1
+#define MISC_MII_SEL_1P5V       2
+  uint32        miscPeriphEcoReg;               /* 0x0044 */
+
+  uint32        miscIddqCtrl;                   /* 0x0048 */
+#define MISC_IDDQ_CONTROL_USBH    (1<<6)
+#define MISC_IDDQ_CONTROL_USBD    (1<<5)
+
+  uint32        miscAdslClkSample;              /* 0x004c */
+
+  uint32        unused3[(0x0100 - 0x0050) / 4]; /* 0x0050 */
+  uint32        miscAdslCtrl;                   /* 0x0100 */
+  uint32        unused4[(0x0180 - 0x0104) / 4]; /* 0x0104 */
+  uint32        miscMipsTestCtrl;               /* 0x0180 */
+  uint32        miscMipsTestStatus;             /* 0x0184 */
+  uint32        unused5[(0x0200 - 0x0188) / 4]; /* 0x0188 */
+  uint32        miscPllCtrlSysPll0;             /* 0x0200 */
+  uint32        miscPllCtrlSysPll1;             /* 0x0204 */
+  uint32        miscPllCtrlSysPll2;             /* 0x0208 */
+  uint32        miscPllCtrlSysPll3;             /* 0x020c */
+  uint32        miscPllCtrlDdrPll;              /* 0x0210 */
+  uint32        miscPllCtrlXtalEcoReg;          /* 0x0214 */
+  uint32        unused6[(0x0240 - 0x0218) / 4]; /* 0x0218 */
+  uint32        miscStrapBus;                   /* 0x0240 */
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           18
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SERIAL              0x01
+#define MISC_STRAP_BUS_BOOT_NAND                0x00
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      7
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK       (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT)
+
+  uint32        miscStrapOverride;              /* 0x0244 */
+  uint32        unused7[(0x0280 - 0x0248) / 4]; /* 0x0248 */
+  uint32        miscRtcSleepModeEn;             /* 0x0280 */
+  uint32        miscRtcSleepRtcEn;              /* 0x0284 */
+  uint32        miscRtcSleepRtcCountLow;        /* 0x0288 */
+  uint32        miscRtcSleepRtcCountHigh;       /* 0x028c */
+  uint32        miscRtcSleepRtcEvent;           /* 0x0290 */
+  uint32        miscRtcSleepWakeupMask;         /* 0x0294 */
+  uint32        miscRtcSleepWakeupStatus;       /* 0x0298 */
+  uint32        miscRtcSleepDebounceCtrl;       /* 0x029c */
+  uint32        miscRtcSleepCpuScratchPad;      /* 0x02a0 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+** LedControl Register Set Definitions.
+*/
+
+#pragma pack(push, 4)
+typedef struct LedControl {
+    uint32  ledInit;
+#define LED_LED_TEST                (1 << 31)
+#define LED_SHIFT_TEST              (1 << 30)
+#define LED_SERIAL_LED_SHIFT_DIR    (1 << 16)
+#define LED_SERIAL_LED_DATA_PPOL    (1 << 15)
+#define LEDSERIAL_LED_CLK_NPOL      (1 << 14)
+#define LED_SERIAL_LED_MUX_SEL      (1 << 13)
+#define LED_SERIAL_LED_EN           (1 << 12)
+#define LED_FAST_INTV_SHIFT         6
+#define LED_FAST_INTV_MASK          (0x3F<<LED_FAST_INTV_SHIFT)
+#define LED_SLOW_INTV_SHIFT         0
+#define LED_SLOW_INTV_MASK          (0x3F<<LED_SLOW_INTV_SHIFT)
+#define LED_INTERVAL_20MS           1
+
+    uint64  ledMode;
+#define LED_MODE_MASK               (uint64)0x3
+#define LED_MODE_OFF                (uint64)0x0
+#define LED_MODE_FLASH              (uint64)0x1
+#define LED_MODE_BLINK              (uint64)0x2
+#define LED_MODE_ON                 (uint64)0x3
+
+    uint32  ledHWDis;
+    uint32  ledStrobe;
+    uint32  ledLinkActSelHigh;
+#define LED_ENET0                   4
+#define LED_ENET1                   5
+#define LED_ENET2                   6
+#define LED_ENET3                   7
+#define LED_4_ACT_SHIFT             0
+#define LED_5_ACT_SHIFT             4
+#define LED_6_ACT_SHIFT             8
+#define LED_7_ACT_SHIFT             12
+#define LED_4_LINK_SHIFT            16
+#define LED_5_LINK_SHIFT            20
+#define LED_6_LINK_SHIFT            24
+#define LED_7_LINK_SHIFT            28
+    uint32  ledLinkActSelLow;
+#define LED_INET                    0
+#define LED_0_ACT_SHIFT             0
+#define LED_1_ACT_SHIFT             4
+#define LED_2_ACT_SHIFT             8
+#define LED_3_ACT_SHIFT             12
+#define LED_0_LINK_SHIFT            16
+#define LED_1_LINK_SHIFT            20
+#define LED_2_LINK_SHIFT            24
+#define LED_3_LINK_SHIFT            28
+
+    uint32  ledReadback;
+    uint32  ledSerialMuxSelect;
+} LedControl;
+#pragma pack(pop)
+
+#define LED ((volatile LedControl * const) LED_BASE)
+
+#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \
+    ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \
+    ((((X) & BP_GPIO_NUM_MASK) - 8) << 1))
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer 
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+#define USB_DEVICE_MODE_SEL     (1<<0)
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 GenericControl;
+#define PLL_SUSPEND_EN          (1<<1)
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16  
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+
+  uint32 ioBaseLimit;
+  uint32 secStatus;
+  uint32 rcMemBaseLimit;
+  uint32 rcPrefBaseLimit;
+  uint32 rcPrefBaseHi;
+  uint32 rcPrefLimitHi;
+  uint32 rcIoBaseLimit;
+  uint32 capPointer;
+  uint32 expRomBase;
+  uint32 brdigeCtrlIntPinIntLine;
+  uint32 bridgeCtrl;
+  uint32 unused1[27];
+
+  /* PcieExpressCtrlRegs */
+  uint16 pciExpressCap;
+  uint16 pcieCapabilitiy;
+  uint32 deviceCapability;
+  uint16 deviceControl;
+  uint16 deviceStatus;
+  uint32 linkCapability;
+  uint16 linkControl;
+  uint16 linkStatus;
+  uint32 slotCapability;
+  uint16 slotControl;
+  uint16 slotStatus;
+  uint16 rootControl;
+  uint16 rootCap;
+  uint32 rootStatus;
+  uint32 deviceCapability2;
+  uint16 deviceControl2;
+  uint16 deviceStatus2;
+  uint32 linkCapability2;
+  uint16 linkControl2;
+  uint16 linkStatus2;
+  uint32 slotCapability2;
+  uint16 slotControl2;
+  uint16 slotStatus2;
+  uint32 unused2[6];
+
+  /* PcieErrorRegs */
+  uint16 advErrCapId;
+  uint16 advErrCapOff;
+  uint32 ucErrStatus;
+  uint32 ucorrErrMask;
+  uint32 ucorrErrSevr;
+  uint32 corrErrStatus;
+  uint32 corrErrMask;
+  uint32 advErrCapControl;
+  uint32 headerLog1;
+  uint32 headerLog2;
+  uint32 headerLog3;
+  uint32 headerLog4;
+  uint32 rootErrorCommand;
+  uint32 rootErrorStatus;
+  uint32 rcCorrId;
+  uint32 rcFatalNonfatalId;
+  uint32 unused3[10];
+
+  /* PcieVcRegs */
+  uint16 vcCapId;
+  uint16 vcCapOffset;
+  uint32 prtVcCapability;
+  uint32 portVcCapability2;
+  uint16 portVcControl;
+  uint16 portVcCtatus;
+  uint32 portArbStatus;
+  uint32 vcRsrcControl;
+  uint32 vcRsrcStatus;
+  uint32 unused4[1];
+
+  /* PcieVendor */
+  uint32 vendorCapability;
+  uint32 vendorSpecificHdr;
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0  
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+  uint32 vpdIntf;        /* 0x428 */
+  uint16 unused_g;       /* 0x42c */
+  uint16 vpdAddrFlag;    /* 0x42e */
+  uint32 vpdData;        /* 0x430 */
+  uint32 idVal1;         /* 0x434 */
+  uint32 idVal2;         /* 0x438 */
+  uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+
+  uint32 idVal4;
+  uint32 idVal5;
+  uint32 unused_h;
+  uint32 idVal6;
+  uint32 msiData;
+  uint32 msiAddr_h;
+  uint32 msiAddr_l;
+  uint32 msiMask;
+  uint32 msiPend;
+  uint32 pmData_c;
+  uint32 msixControl;
+  uint32 msixTblOffBir;
+  uint32 msixPbaOffBit;
+  uint32 unused_k;
+  uint32 pcieCapability;
+  uint32 deviceCapability;
+  uint32 unused_l;
+  uint32 linkCapability;
+  uint32 bar2Config;
+  uint32 pcieDeviceCapability2;
+  uint32 pcieLinkCapability2;
+  uint32 pcieLinkControl;
+  uint32 pcieLinkCapabilityRc;
+  uint32 bar3Config;
+  uint32 rootCap;
+  uint32 devSerNumCapId;
+  uint32 lowerSerNum;
+  uint32 upperSerNum;
+  uint32 advErrCap;
+  uint32 pwrBdgtData0;
+  uint32 pwrBdgtData1;
+  uint32 pwrBdgtData2;
+  uint32 pwdBdgtData3;
+  uint32 pwrBdgtData4;
+  uint32 pwrBdgtData5;
+  uint32 pwrBdgtData6;
+  uint32 pwrBdgtData7;
+  uint32 pwrBdgtCapability;
+  uint32 vsecHdr;
+  uint32 rcUserMemLo1;
+  uint32 rcUserMemHi1;
+  uint32 rcUserMemLo2;
+  uint32 rcUserMemHi2;
+}PcieBlk428Regs;
+
+typedef struct PcieBlk800Regs{
+#define NUM_PCIE_BLK_800_CTRL_REGS  6
+  uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS];
+  uint32 tlCtlStat0;
+  uint32 pmStatus0;
+  uint32 pmStatus1;
+
+#define NUM_PCIE_BLK_800_TAGS       32
+  uint32 tlStatus[NUM_PCIE_BLK_800_TAGS];
+  uint32 tlHdrFcStatus;
+  uint32 tlDataFcStatus;
+  uint32 tlHdrFcconStatus;
+  uint32 tlDataFcconStatus;
+  uint32 tlTargetCreditStatus;
+  uint32 tlCreditAllocStatus;
+  uint32 tlSmlogicStatus;
+} PcieBlk800Regs;
+
+
+typedef struct PcieBlk1000Regs{
+#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS  16
+  uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS];
+  uint32 dlattnVec;
+  uint32 dlAttnMask;
+  uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13   
+  uint32 dlTxChecksum;
+  uint32 dlForcedUpdateGen1;
+  uint32 mdioAddr;
+  uint32 mdioWrData;
+  uint32 mdioRdData;
+  uint32 dlRxPFcCl;
+  uint32 dlRxCFcCl;
+  uint32 dlRxAckNack;
+  uint32 dlTxRxSeqnb;
+  uint32 dlTxPFcAl;
+  uint32 dlTxNpFcAl;
+  uint32 regDlSpare;
+  uint32 dlRegSpare;
+  uint32 dlTxRxSeq;
+  uint32 dlRxNpFcCl;
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         5
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+  uint32 phyReceivedMcpErrors;
+  uint32 phyTransmittedMcpErrors;
+  uint32 phyGenDebug;
+  uint32 phyRecoveryHist;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR1_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR1_REMAP_swap_enable                  1
+   
+   uint32 bar2Remap;       /* 0x081c*/
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR2_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR2_REMAP_swap_enable                  1
+   
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity  (1<<12)
+#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection   (1<<11)
+#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix              (1<<9)
+#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt                (1<<7)
+   
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+
+   uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR0_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR0_BASE_remap_enable                  1
+
+   uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */   
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR1_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR1_BASE_remap_enable                  1   
+   
+   uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 bridgeErrStatus;       /* 0x0838 */
+   uint32 bridgeErrMask;         /* 0x083c */   
+   uint32 coreErrStatus2;        /* 0x0840 */
+   uint32 coreErrMask2;          /* 0x0844 */
+   uint32 coreErrStatus1;        /* 0x0848 */
+   uint32 coreErrMask1;          /* 0x084c */
+   uint32 rcInterruptStatus;     /* 0x0850 */
+   uint32 rcInterruptMask;       /* 0x0854 */
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK   (1<<0)
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK   (1<<1)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK   (1<<2)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK   (1<<3)   
+      
+}PcieBridgeRegs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS                    ((volatile PcieRegs * const) PCIE_BASE)
+
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const) \
+                                        (PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const) \
+                                        (PCIE_BASE+0x428))
+#define PCIEH_BLK_800_REGS            ((volatile PcieBlk800Regs * const) \
+                                        (PCIE_BASE+0x800))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) \
+                                        (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) \
+                                        (PCIE_BASE+0x1800))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const)  \
+                                        (PCIE_BASE+0x2818))
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/opensource/include/bcm963xx/6362_cpu.h b/shared/opensource/include/bcm963xx/6362_cpu.h
new file mode 100755
index 0000000..f49a6ac
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6362_cpu.h
@@ -0,0 +1,150 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6362_CPU_H
+#define __BCM6362_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+#************************************************************************
+#* Coprocessor 0 Register Names
+#************************************************************************
+*/
+#define C0_BCM_CONFIG          $22
+
+/*
+# Select 1
+#  Bit  31:   unused
+#  Bits 30:25 MMU Size (Num TLB entries-1)
+#  Bits 24:22 ICache sets/way (2^n * 64)
+#  Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
+#  Bits 18:16 ICache Associativity (n+1) way                    
+#  Bits 15:13 DCache sets/way (2^n * 64)
+#  Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
+#  Bits 9:7   DCache Associativity (n+1) way                    
+#  Bits 6:4   unused
+#  Bit  3:    1=At least 1 watch register
+#  Bit  2:    1=MIPS16 code compression implemented
+#  Bit  1:    1=EJTAG implemented                   
+#  Bit  0:    1=FPU implemented                   
+*/
+#define CP0_CFG_ISMSK      (0x7 << 22)
+#define CP0_CFG_ISSHF      22
+#define CP0_CFG_ILMSK      (0x7 << 19)
+#define CP0_CFG_ILSHF      19
+#define CP0_CFG_IAMSK      (0x7 << 16)
+#define CP0_CFG_IASHF      16
+#define CP0_CFG_DSMSK      (0x7 << 13)
+#define CP0_CFG_DSSHF      13
+#define CP0_CFG_DLMSK      (0x7 << 10)
+#define CP0_CFG_DLSHF      10
+#define CP0_CFG_DAMSK      (0x7 << 7)
+#define CP0_CFG_DASHF      7
+
+/*
+#************************************************************************
+#* Coprocessor 0 Broadcom Config Register Bits
+#************************************************************************
+*/
+#define CP0_BCM_CFG_ICSHEN          (0x1 << 31)
+#define CP0_BCM_CFG_DCSHEN          (0x1 << 30)
+#define CP0_BCM_CFG_BTHD            (0x1 << 21)
+#define CP0_BCM_CFG_CLF             (0x1 << 20)
+#define CP0_BCM_CFG_NBK             (0x1 << 17)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Interrupt Register
+#************************************************************************
+*/
+#define CP0_CMT_XIR_4               (0x1 << 31)
+#define CP0_CMT_XIR_3               (0x1 << 30)
+#define CP0_CMT_XIR_2               (0x1 << 29)
+#define CP0_CMT_XIR_1               (0x1 << 28)
+#define CP0_CMT_XIR_0               (0x1 << 27)
+#define CP0_CMT_SIR_1               (0x1 << 16)
+#define CP0_CMT_SIR_0               (0x1 << 15)
+#define CP0_CMT_NMIR_TP1            (0x1 << 1)
+#define CP0_CMT_NMIR_TP0            (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Control Register
+#************************************************************************
+*/
+#define CP0_CMT_DSU_TP1             (0x1 << 30)
+#define CP0_CMT_TPS_SHFT            16
+#define CP0_CMT_TPS_MASK            (0xF << CP0_CMT_TPS_SHFT)
+#define CP0_CMT_PRIO_TP1            (0x1 << 5)
+#define CP0_CMT_PRIO_TP0            (0x1 << 4)
+#define CP0_CMT_RSTSE               (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Local Register
+#************************************************************************
+*/
+#define CP0_CMT_TPID                (0x1 << 31)
+
+/*
+#************************************************************************
+#* MIPS Registers
+#************************************************************************
+*/
+
+#define MIPS_BASE_BOOT  0xbfa00000
+#define MIPS_BASE       0xff400000
+
+#define MIPS_RAC_CR0    0x00        // RAC Configuration Register
+#define MIPS_RAC_CR1    0x08        // RAC Configuration Register 1
+#define RAC_FLH         (1 << 8)
+#define RAC_DPF         (1 << 6)
+#define RAC_NCH         (1 << 5)
+#define RAC_C_INV       (1 << 4)
+#define RAC_PF_D        (1 << 3)
+#define RAC_PF_I        (1 << 2)
+#define RAC_D           (1 << 1)
+#define RAC_I           (1 << 0)
+
+#define MIPS_RAC_ARR    0x04        // RAC Address Range Register
+#define RAC_UPB_SHFT    16
+#define RAC_LWB_SHFT    0
+
+#define MIPS_LMB_CR     0x1C        // LMB Control Register
+#define LMB_EN          (1 << 0)
+
+#define MIPS_SBR        0x20        // System Base Register
+
+#define MIPS_TP0_ALT_BV 0x30000
+#define MIPS_TP1_ALT_BV 0x38000
+#define ENABLE_ALT_BV   (1 << 19)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/opensource/include/bcm963xx/6362_intr.h b/shared/opensource/include/bcm963xx/6362_intr.h
new file mode 100755
index 0000000..b8e6a35
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6362_intr.h
@@ -0,0 +1,123 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __6362_INTR_H
+#define __6362_INTR_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define INTERRUPT_ID_SOFTWARE_0           0
+#define INTERRUPT_ID_SOFTWARE_1           1
+
+/*=====================================================================*/
+/* BCM6362 Timer Interrupt Level Assignments                          */
+/*=====================================================================*/
+#define MIPS_TIMER_INT                  7
+
+/*=====================================================================*/
+/* Peripheral ISR Table Offset                                              */
+/*=====================================================================*/
+#define INTERNAL_ISR_TABLE_OFFSET       8
+#define INTERNAL_HIGH_ISR_TABLE_OFFSET  (INTERNAL_ISR_TABLE_OFFSET + 32)
+
+/*=====================================================================*/
+/* Logical Peripheral Interrupt IDs                                    */
+/*=====================================================================*/
+
+#define INTERRUPT_ID_TIMER               (INTERNAL_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_RING_OSC            (INTERNAL_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_LS_SPIM             (INTERNAL_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_UART                (INTERNAL_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_UART1               (INTERNAL_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_HS_SPIM             (INTERNAL_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_WLAN_GPIO           (INTERNAL_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_WLAN                (INTERNAL_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_IPSEC               (INTERNAL_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_USBH                (INTERNAL_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_USBH20              (INTERNAL_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_USBS                (INTERNAL_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_NAND_FLASH          (INTERNAL_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_PCM                 (INTERNAL_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_EPHY                (INTERNAL_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_DG                  (INTERNAL_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_EPHY_ENERGY_0       (INTERNAL_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_EPHY_ENERGY_1       (INTERNAL_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_EPHY_ENERGY_2       (INTERNAL_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_EPHY_ENERGY_3       (INTERNAL_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_USB_CNTL_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_USB_CNTL_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_USB_BULK_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_USB_BULK_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_USB_ISO_RX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_USB_ISO_TX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_IPSEC_DMA_0         (INTERNAL_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_IPSEC_DMA_1         (INTERNAL_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_XDSL                (INTERNAL_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_FAP                 (INTERNAL_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_PCIE_RC             (INTERNAL_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_PCIE_EP             (INTERNAL_ISR_TABLE_OFFSET + 31)
+#define INTERRUPT_ID_ENETSW_RX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_ENETSW_RX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_ENETSW_RX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_ENETSW_RX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_PCM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_PCM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_DECT_0              (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_DECT_1              (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_EXTERNAL_0          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_EXTERNAL_1          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_EXTERNAL_2          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_EXTERNAL_3          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_ATM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_ATM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_ATM_DMA_2           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_ATM_DMA_3           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_ATM_DMA_4           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_ATM_DMA_5           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_ATM_DMA_6           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_ATM_DMA_7           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_ATM_DMA_8           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_ATM_DMA_9           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_ATM_DMA_10          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_ATM_DMA_11          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_ATM_DMA_12          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_ATM_DMA_13          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_ATM_DMA_14          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_ATM_DMA_15          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_ATM_DMA_16          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_ATM_DMA_17          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_ATM_DMA_18          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_ATM_DMA_19          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31)
+
+#define INTERRUPT_ID_LAST                INTERRUPT_ID_ATM_DMA_19
+
+#ifdef __cplusplus
+    }
+#endif                    
+
+#endif  /* __BCM6362_H */
+
+
diff --git a/shared/opensource/include/bcm963xx/6362_map_part.h b/shared/opensource/include/bcm963xx/6362_map_part.h
new file mode 100755
index 0000000..86d56e9
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6362_map_part.h
@@ -0,0 +1,1478 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6362_MAP_H
+#define __BCM6362_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#include "bcmtypes.h"
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200  /* NAND registers */
+#define NAND_CACHE_BASE      0xb0000600
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define HSSPIM_BASE          0xb0001000  /* High-Speed SPI registers */
+#define MISC_BASE            0xb0001800  /* Miscellaneous Registers */
+#define LED_BASE             0xb0001900  /* LED control registers */
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define IPSEC_BASE           0xb0002800
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define WLAN_CHIPC_BASE      0x10004000  /* WLAN ChipCommon registers, use 1xxx for ioremap */
+#define WLAN_MAC_BASE        0x10005000  /* WLAN d11mac registers */
+#define WLAN_SHIM_BASE       0xb0007000  /* shim interface to WLAN */
+#define SAR_DMA_BASE         0xb000b800  /* ATM SAR DMA control registers */
+#define PCIE_BASE            0xb0e40000
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64        IrqMask;
+    uint64        IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define NAND_CLK_EN      (1 << 20)
+#define PHYMIPS_CLK_EN   (1 << 19)
+#define FAP_CLK_EN       (1 << 18)
+#define PCIE_CLK_EN      (1 << 17)
+#define HS_SPI_CLK_EN    (1 << 16)
+#define SPI_CLK_EN       (1 << 15)
+#define IPSEC_CLK_EN     (1 << 14)
+#define USBH_CLK_EN      (1 << 13)
+#define USBD_CLK_EN      (1 << 12)
+#define PCM_CLK_EN       (1 << 11)
+#define ROBOSW_CLK_EN    (1 << 10)
+#define SAR_CLK_EN       (1 << 9)
+#define SWPKT_SAR_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define WLAN_OCP_CLK_EN  (1 << 5)
+#define MIPS_CLK_EN      (1 << 4)
+#define ADSL_CLK_EN      (1 << 3)
+#define ADSL_AFE_EN      (1 << 2)
+#define ADSL_QPROC_EN    (1 << 1)
+#define DISABLE_GLESS    (1 << 0)
+
+    uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_WLAN_SHIM_UBUS (1 << 14)
+#define SOFT_RST_FAP            (1 << 13)
+#define SOFT_RST_DDR_PHY        (1 << 12)
+#define SOFT_RST_WLAN_SHIM      (1 << 11)
+#define SOFT_RST_PCIE_EXT       (1 << 10)
+#define SOFT_RST_PCIE           (1 << 9)
+#define SOFT_RST_PCIE_CORE      (1 << 8)
+#define SOFT_RST_PCM            (1 << 7)
+#define SOFT_RST_USBH           (1 << 6)
+#define SOFT_RST_USBD           (1 << 5)
+#define SOFT_RST_SWITCH         (1 << 4)
+#define SOFT_RST_SAR            (1 << 3)
+#define SOFT_RST_EPHY           (1 << 2)
+#define SOFT_RST_IPSEC          (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        unused1;            /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+    uint32      LEDCtrl;                    /* 10 */
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_EXT_IRQ3          (1<<27)
+#define GPIO_MODE_EXT_IRQ2          (1<<26)
+#define GPIO_MODE_EXT_IRQ1          (1<<25)
+#define GPIO_MODE_EXT_IRQ0          (1<<24)
+#define GPIO_MODE_EPHY3_LED         (1<<23)
+#define GPIO_MODE_EPHY2_LED         (1<<22)
+#define GPIO_MODE_EPHY1_LED         (1<<21)
+#define GPIO_MODE_EPHY0_LED         (1<<20)
+#define GPIO_MODE_ADSL_SPI_SSB      (1<<19)
+#define GPIO_MODE_ADSL_SPI_CLK      (1<<18)
+#define GPIO_MODE_ADSL_SPI_MOSI     (1<<17)
+#define GPIO_MODE_ADSL_SPI_MISO     (1<<16)
+#define GPIO_MODE_UART2_SDOUT       (1<<15)
+#define GPIO_MODE_UART2_SDIN        (1<<14)
+#define GPIO_MODE_UART2_SRTS        (1<<13)
+#define GPIO_MODE_UART2_SCTS        (1<<12)
+#define GPIO_MODE_NTR_PULSE         (1<<11)
+#define GPIO_MODE_LS_SPIM_SSB3      (1<<10)
+#define GPIO_MODE_LS_SPIM_SSB2      (1<<9)
+#define GPIO_MODE_INET_LED          (1<<8)
+#define GPIO_MODE_ROBOSW_LED1       (1<<7)
+#define GPIO_MODE_ROBOSW_LED0       (1<<6)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<5)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<2)
+#define GPIO_MODE_SYS_IRQ           (1<<1)
+#define GPIO_MODE_USBD_LED          (1<<0)
+
+    uint32      GPIOCtrl;                   /* 1C */
+    uint32      unused3[2];                 /* 20 - 24*/
+    uint32      TestControl;                /* 28 */
+    uint32      OscControl;                 /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define NAND_GPIO_OVERRIDE      (1<<2)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define EPHY_PLL_LOCK           (1<<27)
+#define EPHY_ATEST_25MHZ_EN     (1<<26)
+#define EPHY_PWR_DOWN_DLL       (1<<25)
+#define EPHY_PWR_DOWN_BIAS      (1<<24)
+#define EPHY_PWR_DOWN_TX_4      (1<<23)
+#define EPHY_PWR_DOWN_TX_3      (1<<22)
+#define EPHY_PWR_DOWN_TX_2      (1<<21)
+#define EPHY_PWR_DOWN_TX_1      (1<<20)
+#define EPHY_PWR_DOWN_RX_4      (1<<19)
+#define EPHY_PWR_DOWN_RX_3      (1<<18)
+#define EPHY_PWR_DOWN_RX_2      (1<<17)
+#define EPHY_PWR_DOWN_RX_1      (1<<16)
+#define EPHY_PWR_DOWN_SD_4      (1<<15)
+#define EPHY_PWR_DOWN_SD_3      (1<<14)
+#define EPHY_PWR_DOWN_SD_2      (1<<13)
+#define EPHY_PWR_DOWN_SD_1      (1<<12)
+#define EPHY_PWR_DOWN_RD_4      (1<<11)
+#define EPHY_PWR_DOWN_RD_3      (1<<10)
+#define EPHY_PWR_DOWN_RD_2      (1<<9)
+#define EPHY_PWR_DOWN_RD_1      (1<<8)
+#define EPHY_PWR_DOWN_4         (1<<7)
+#define EPHY_PWR_DOWN_3         (1<<6)
+#define EPHY_PWR_DOWN_2         (1<<5)
+#define EPHY_PWR_DOWN_1         (1<<4)
+#define EPHY_RST_4              (1<<3)
+#define EPHY_RST_3              (1<<2)
+#define EPHY_RST_2              (1<<1)
+#define EPHY_RST_1              (1<<0)
+    uint32      RoboswSwitchCtrl;           /* 40 */
+#define RSW_MII_2_IFC_EN        (1<<23)
+#define RSW_MII_2_AMP_EN        (1<<22)
+#define RSW_MII_2_SEL_SHIFT     20
+#define RSW_MII_SEL_3P3V        0
+#define RSW_MII_SEL_2P5V        1
+#define RSW_MII_SEL_1P5V        2
+#define RSW_MII_AMP_EN          (1<<18)
+#define RSW_MII_SEL_SHIFT       16
+#define RSW_SPI_MODE            (1<<11)
+#define RSW_BC_SUPP_EN          (1<<10)
+#define RSW_CLK_FREQ_MASK       (3<<8)
+#define RSW_ENF_DFX_FLOW        (1<<7)
+#define RSW_ENH_DFX_FLOW        (1<<6)
+#define RSW_GRX_0_SETUP         (1<<5)
+#define RSW_GTX_0_SETUP         (1<<4)
+#define RSW_HW_FWDG_EN          (1<<3)
+#define RSW_QOS_EN              (1<<2)
+#define RSW_WD_CLR_EN           (1<<1)
+#define RSW_MII_DUMB_FWDG_EN    (1<<0)
+
+    uint32      RegFileTmCtl;               /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x0f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                4
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      unused4[6];                 /* 50 - 64 */
+    uint32      DieRevID;                   /* 68 */
+    uint32      unused5;                    /* 6c */
+    uint32      DiagSelControl;             /* 70 */
+    uint32      DiagReadBack;               /* 74 */
+    uint32      DiagReadBackHi;             /* 78 */
+    uint32      DiagMiscControl;            /* 7c */
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    48
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2;
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3;
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define __mask(end, start)      (((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32    hs_spiGlobalCtrl;   // 0x0000
+#define HS_SPI_MOSI_IDLE        (1 << 18)
+#define HS_SPI_CLK_POLARITY      (1 << 17)
+#define HS_SPI_CLK_GATE_SSOFF       (1 << 16)
+#define HS_SPI_PLL_CLK_CTRL     (8)
+#define HS_SPI_PLL_CLK_CTRL_MASK    __mask(15, HS_SPI_PLL_CLK_CTRL)
+#define HS_SPI_SS_POLARITY      (0)
+#define HS_SPI_SS_POLARITY_MASK     __mask(7, HS_SPI_SS_POLARITY)
+
+  uint32    hs_spiExtTrigCtrl;  // 0x0004
+#define HS_SPI_TRIG_RAW_STATE   (24)
+#define HS_SPI_TRIG_RAW_STATE_MASK  __mask(31, HS_SPI_TRIG_RAW_STATE)
+#define HS_SPI_TRIG_LATCHED     (16)
+#define HS_SPI_TRIG_LATCHED_MASK    __mask(23, HS_SPI_TRIG_LATCHED)
+#define HS_SPI_TRIG_SENSE       (8)
+#define HS_SPI_TRIG_SENSE_MASK      __mask(15, HS_SPI_TRIG_SENSE)
+#define HS_SPI_TRIG_TYPE        (0)
+#define HS_SPI_TRIG_TYPE_MASK       __mask(7, HS_SPI_TRIG_TYPE)
+#define HS_SPI_TRIG_TYPE_EDGE       (0)
+#define HS_SPI_TRIG_TYPE_LEVEL      (1)
+
+  uint32    hs_spiIntStatus;    // 0x0008
+#define HS_SPI_IRQ_PING1_USER       (28)
+#define HS_SPI_IRQ_PING1_USER_MASK  __mask(31, HS_SPI_IRQ_PING1_USER)
+#define HS_SPI_IRQ_PING0_USER       (24)
+#define HS_SPI_IRQ_PING0_USER_MASK  __mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define HS_SPI_IRQ_PING1_CTRL_INV   (1 << 12)
+#define HS_SPI_IRQ_PING1_POLL_TOUT  (1 << 11)
+#define HS_SPI_IRQ_PING1_TX_UNDER   (1 << 10)
+#define HS_SPI_IRQ_PING1_RX_OVER    (1 << 9)
+#define HS_SPI_IRQ_PING1_CMD_DONE   (1 << 8)
+
+#define HS_SPI_IRQ_PING0_CTRL_INV   (1 << 4)
+#define HS_SPI_IRQ_PING0_POLL_TOUT  (1 << 3)
+#define HS_SPI_IRQ_PING0_TX_UNDER   (1 << 2)
+#define HS_SPI_IRQ_PING0_RX_OVER    (1 << 1)
+#define HS_SPI_IRQ_PING0_CMD_DONE   (1 << 0)
+
+  uint32    hs_spiIntStatusMasked;  // 0x000C
+#define HS_SPI_IRQSM__PING1_USER    (28)
+#define HS_SPI_IRQSM__PING1_USER_MASK   __mask(31, HS_SPI_IRQSM__PING1_USER)
+#define HS_SPI_IRQSM__PING0_USER    (24)
+#define HS_SPI_IRQSM__PING0_USER_MASK   __mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define HS_SPI_IRQSM__PING1_CTRL_INV    (1 << 12)
+#define HS_SPI_IRQSM__PING1_POLL_TOUT   (1 << 11)
+#define HS_SPI_IRQSM__PING1_TX_UNDER    (1 << 10)
+#define HS_SPI_IRQSM__PING1_RX_OVER (1 << 9)
+#define HS_SPI_IRQSM__PING1_CMD_DONE    (1 << 8)
+
+#define HS_SPI_IRQSM__PING0_CTRL_INV    (1 << 4)
+#define HS_SPI_IRQSM__PING0_POLL_TOUT   (1 << 3)
+#define HS_SPI_IRQSM__PING0_TX_UNDER    (1 << 2)
+#define HS_SPI_IRQSM__PING0_RX_OVER     (1 << 1)
+#define HS_SPI_IRQSM__PING0_CMD_DONE    (1 << 0)
+
+  uint32    hs_spiIntMask;      // 0x0010
+#define HS_SPI_IRQM_PING1_USER      (28)
+#define HS_SPI_IRQM_PING1_USER_MASK __mask(31, HS_SPI_IRQM_PING1_USER)
+#define HS_SPI_IRQM_PING0_USER      (24)
+#define HS_SPI_IRQM_PING0_USER_MASK __mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define HS_SPI_IRQM_PING1_CTRL_INV  (1 << 12)
+#define HS_SPI_IRQM_PING1_POLL_TOUT (1 << 11)
+#define HS_SPI_IRQM_PING1_TX_UNDER  (1 << 10)
+#define HS_SPI_IRQM_PING1_RX_OVER   (1 << 9)
+#define HS_SPI_IRQM_PING1_CMD_DONE  (1 << 8)
+
+#define HS_SPI_IRQM_PING0_CTRL_INV  (1 << 4)
+#define HS_SPI_IRQM_PING0_POLL_TOUT (1 << 3)
+#define HS_SPI_IRQM_PING0_TX_UNDER  (1 << 2)
+#define HS_SPI_IRQM_PING0_RX_OVER   (1 << 1)
+#define HS_SPI_IRQM_PING0_CMD_DONE  (1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32    hs_spiFlashCtrl;    // 0x0014
+#define HS_SPI_FCTRL_MB_ENABLE      (1 << 23)
+#define HS_SPI_FCTRL_SS_NUM         (20)
+#define HS_SPI_FCTRL_SS_NUM_MASK    __mask(22, HS_SPI_FCTRL_SS_NUM)
+#define HS_SPI_FCTRL_PROFILE_NUM    (16)
+#define HS_SPI_FCTRL_PROFILE_NUM_MASK   __mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define HS_SPI_FCTRL_DUMMY_BYTES    (10)
+#define HS_SPI_FCTRL_DUMMY_BYTES_MASK   __mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES     (8)
+#define HS_SPI_FCTRL_ADDR_BYTES_MASK    __mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define HS_SPI_FCTRL_ADDR_BYTES_2   (0)
+#define HS_SPI_FCTRL_ADDR_BYTES_3   (1)
+#define HS_SPI_FCTRL_ADDR_BYTES_4   (2)
+#define HS_SPI_FCTRL_READ_OPCODE    (0)
+#define HS_SPI_FCTRL_READ_OPCODE_MASK   __mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32    hs_spiFlashAddrBase;    // 0x0018
+
+  char      fill0[0x80 - 0x18];
+
+  uint32    hs_spiPP_0_Cmd;     // 0x0080
+#define HS_SPI_PP_SS_NUM        (12)
+#define HS_SPI_PP_SS_NUM_MASK       __mask(14, HS_SPI_PP_SS_NUM)
+#define HS_SPI_PP_PROFILE_NUM       (8)
+#define HS_SPI_PP_PROFILE_NUM_MASK  __mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+    uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+    uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+    uint32 fifo_status;
+    uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+    uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+    
+    uint32 signal_ctrl;
+#define	HS_SPI_ASYNC_INPUT_PATH (1 << 16)
+#define	HS_SPI_LAUNCH_RISING    (1 << 13)
+#define	HS_SPI_LATCH_RISING     (1 << 12)
+
+    uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+    uint32 polling_config;
+    uint32 polling_and_mask;
+    uint32 polling_compare;
+    uint32 polling_timeout;
+    uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+    uint32  unused1;                            /* 0x00 */
+    uint32  miscSerdesCtrl;                     /* 0x04 */
+#define SERDES_PCIE_ENABLE                      0x00000001
+#define SERDES_PCIE_EXD_ENABLE                  (1<<15)
+    
+    uint32  miscSerdesSts;                      /* 0x08 */
+    uint32  miscIrqOutMask;                     /* 0x0C */
+#define MISC_PCIE_EP_IRQ_MASK0                  (1<<0)
+#define MISC_PCIE_EP_IRQ_MASK1                  (1<<1)
+
+    uint32  miscMemcControl;                    /* 0x10 */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE    (1<<3)
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE     (1<<2)
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE         (1<<1)
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE      (1<<0)
+
+    uint32  miscStrapBus;                       /* 0x14 */
+#define MISC_STRAP_BUS_RESET_CFG_DELAY          (1<<18)
+#define MISC_STRAP_BUS_RESET_OUT_SHIFT          16
+#define MISC_STRAP_BUS_RESET_OUT_MASK           (3<<MISC_STRAP_BUS_RESET_OUT_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT           15
+#define MISC_STRAP_BUS_BOOT_SEL_MASK            (0x1<<MISC_STRAP_BUS_BOOT_SEL_SHIFT)
+#define MISC_STRAP_BUS_BOOT_SERIAL              0x01
+#define MISC_STRAP_BUS_BOOT_NAND                0x00
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1<<14)
+#define MISC_STRAP_BUS_HS_SPIM_24B_N_32B_ADDR   (1<<14)
+#define MISC_STRAP_BUS_HS_SPIM_CLK_SLOW_N_FAST  (1<<13)
+#define MISC_STRAP_BUS_LS_SPIM_CLK_FAST_N_SLOW  (1<<12)
+#define MISC_STRAP_BUS_LS_SPI_MASTER_N_SLAVE    (1<<11)
+#define MISC_STRAP_BUS_PLL_USE_LOCK             (1<<10)
+#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N     (1<<9)
+#define MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT     7
+#define MISC_STRAP_BUS_ROBOSW_P4_MODE_MASK      (3<<MISC_STRAP_BUS_ROBOSW_P4_MODE_SHIFT)
+#define MISC_STRAP_BUS_HARD_RESET_DELAY         (1<<6)
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT      1
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK       (0x1F<<MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT)
+#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX        (1<<0)
+
+    uint32  miscStrapOverride;              /* 0x18 */
+    uint32  miscVregCtrl0;                  /* 0x1C */
+
+    uint32  miscVregCtrl1;                  /* 0x20 */
+#define VREG_VSEL1P2_SHIFT        0
+#define VREG_VSEL1P2_MASK         0x1f
+#define VREG_VSEL1P2_MIDDLE       0x0f
+
+    uint32  miscVregCtrl2;                  /* 0x24 */
+    uint32  miscExtra2ChipsIrqMask;         /* 0x28 */
+    uint32  miscExtra2ChipsIrqSts;          /* 0x2C */
+    uint32  miscExtra2ChipsIrqMask1;        /* 0x30 */
+    uint32  miscExtra2ChipsIrqSts1;         /* 0x34 */
+    uint32  miscFapIrqMask;                 /* 0x38 */
+    uint32  miscExtraFapIrqMask;            /* 0x3C */
+    uint32  miscExtra2FapIrqMask;           /* 0x40 */
+    uint32  miscAdsl_clock_sample;          /* 0x44 */
+
+    uint32  miscIddqCtrl;                   /* 0x48 */
+#define MISC_IDDQ_CONTROL_USBD    (1<<5)
+#define MISC_IDDQ_CONTROL_USBH    (1<<4)
+
+    uint32  miscSleep;                      /* 0x4C */
+    uint32  miscRtc_enable;                 /* 0x50 */
+    uint32  miscRtc_count_L;                /* 0x54 */
+    uint32  miscRtc_count_H;                /* 0x58 */
+    uint32  miscRtc_event;                  /* 0x5C */
+    uint32  miscWakeup_mask;                /* 0x60 */
+    uint32  miscWakeup_status;              /* 0x64 */
+} Misc;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+/*
+** LedControl Register Set Definitions.
+*/
+
+#pragma pack(push, 4)
+typedef struct LedControl {
+    uint32  ledInit;
+#define LED_LED_TEST                (1 << 31)
+#define LED_SHIFT_TEST              (1 << 30)
+#define LED_SERIAL_LED_SHIFT_DIR    (1 << 16)
+#define LED_SERIAL_LED_DATA_PPOL    (1 << 15)
+#define LEDSERIAL_LED_CLK_NPOL      (1 << 14)
+#define LED_SERIAL_LED_MUX_SEL      (1 << 13)
+#define LED_SERIAL_LED_EN           (1 << 12)
+#define LED_FAST_INTV_SHIFT         6
+#define LED_FAST_INTV_MASK          (0x3F<<LED_FAST_INTV_SHIFT)
+#define LED_SLOW_INTV_SHIFT         0
+#define LED_SLOW_INTV_MASK          (0x3F<<LED_SLOW_INTV_SHIFT)
+#define LED_INTERVAL_20MS           1
+
+    uint64  ledMode;
+#define LED_MODE_MASK               (uint64)0x3
+#define LED_MODE_OFF                (uint64)0x0
+#define LED_MODE_FLASH              (uint64)0x1
+#define LED_MODE_BLINK              (uint64)0x2
+#define LED_MODE_ON                 (uint64)0x3
+
+    uint32  ledHWDis;
+    uint32  ledStrobe;
+    uint32  ledLinkActSelHigh;
+#define LED_ENET0                   4
+#define LED_ENET1                   5
+#define LED_ENET2                   6
+#define LED_ENET3                   7
+#define LED_4_ACT_SHIFT             0
+#define LED_5_ACT_SHIFT             4
+#define LED_6_ACT_SHIFT             8
+#define LED_7_ACT_SHIFT             12
+#define LED_4_LINK_SHIFT            16
+#define LED_5_LINK_SHIFT            20
+#define LED_6_LINK_SHIFT            24
+#define LED_7_LINK_SHIFT            28
+    uint32  ledLinkActSelLow;
+#define LED_USB                     0
+#define LED_INET                    1
+#define LED_0_ACT_SHIFT             0
+#define LED_1_ACT_SHIFT             4
+#define LED_2_ACT_SHIFT             8
+#define LED_3_ACT_SHIFT             12
+#define LED_0_LINK_SHIFT            16
+#define LED_1_LINK_SHIFT            20
+#define LED_2_LINK_SHIFT            24
+#define LED_3_LINK_SHIFT            28
+
+    uint32  ledReadback;
+    uint32  ledSerialMuxSelect;
+} LedControl;
+#pragma pack(pop)
+
+#define LED ((volatile LedControl * const) LED_BASE)
+
+#define GPIO_NUM_TO_LED_MODE_SHIFT(X) \
+    ((((X) & BP_GPIO_NUM_MASK) < 8) ? (32 + (((X) & BP_GPIO_NUM_MASK) << 1)) : \
+    (((X) & BP_GPIO_SERIAL) ? ((((X) & BP_GPIO_NUM_MASK) - 8) << 1) : \
+    (((X) & BP_GPIO_NUM_MASK) < 16) ? (32 + ((((X) & BP_GPIO_NUM_MASK) - 8) << 1)) : \
+    ((((X) & BP_GPIO_NUM_MASK) - 16) << 1)))
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer 
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16  
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+
+  uint32 ioBaseLimit;
+  uint32 secStatus;
+  uint32 rcMemBaseLimit;
+  uint32 rcPrefBaseLimit;
+  uint32 rcPrefBaseHi;
+  uint32 rcPrefLimitHi;
+  uint32 rcIoBaseLimit;
+  uint32 capPointer;
+  uint32 expRomBase;
+  uint32 brdigeCtrlIntPinIntLine;
+  uint32 bridgeCtrl;
+  uint32 unused1[27];
+
+  /* PcieExpressCtrlRegs */
+  uint16 pciExpressCap;
+  uint16 pcieCapabilitiy;
+  uint32 deviceCapability;
+  uint16 deviceControl;
+  uint16 deviceStatus;
+  uint32 linkCapability;
+  uint16 linkControl;
+  uint16 linkStatus;
+  uint32 slotCapability;
+  uint16 slotControl;
+  uint16 slotStatus;
+  uint16 rootControl;
+  uint16 rootCap;
+  uint32 rootStatus;
+  uint32 deviceCapability2;
+  uint16 deviceControl2;
+  uint16 deviceStatus2;
+  uint32 linkCapability2;
+  uint16 linkControl2;
+  uint16 linkStatus2;
+  uint32 slotCapability2;
+  uint16 slotControl2;
+  uint16 slotStatus2;
+  uint32 unused2[6];
+
+  /* PcieErrorRegs */
+  uint16 advErrCapId;
+  uint16 advErrCapOff;
+  uint32 ucErrStatus;
+  uint32 ucorrErrMask;
+  uint32 ucorrErrSevr;
+  uint32 corrErrStatus;
+  uint32 corrErrMask;
+  uint32 advErrCapControl;
+  uint32 headerLog1;
+  uint32 headerLog2;
+  uint32 headerLog3;
+  uint32 headerLog4;
+  uint32 rootErrorCommand;
+  uint32 rootErrorStatus;
+  uint32 rcCorrId;
+  uint32 rcFatalNonfatalId;
+  uint32 unused3[10];
+
+  /* PcieVcRegs */
+  uint16 vcCapId;
+  uint16 vcCapOffset;
+  uint32 prtVcCapability;
+  uint32 portVcCapability2;
+  uint16 portVcControl;
+  uint16 portVcCtatus;
+  uint32 portArbStatus;
+  uint32 vcRsrcControl;
+  uint32 vcRsrcStatus;
+  uint32 unused4[1];
+
+  /* PcieVendor */
+  uint32 vendorCapability;
+  uint32 vendorSpecificHdr;
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0  
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+  uint32 vpdIntf;        /* 0x428 */
+  uint16 unused_g;       /* 0x42c */
+  uint16 vpdAddrFlag;    /* 0x42e */
+  uint32 vpdData;        /* 0x430 */
+  uint32 idVal1;         /* 0x434 */
+  uint32 idVal2;         /* 0x438 */
+  uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+
+  uint32 idVal4;
+  uint32 idVal5;
+  uint32 unused_h;
+  uint32 idVal6;
+  uint32 msiData;
+  uint32 msiAddr_h;
+  uint32 msiAddr_l;
+  uint32 msiMask;
+  uint32 msiPend;
+  uint32 pmData_c;
+  uint32 msixControl;
+  uint32 msixTblOffBir;
+  uint32 msixPbaOffBit;
+  uint32 unused_k;
+  uint32 pcieCapability;
+  uint32 deviceCapability;
+  uint32 unused_l;
+  uint32 linkCapability;
+  uint32 bar2Config;
+  uint32 pcieDeviceCapability2;
+  uint32 pcieLinkCapability2;
+  uint32 pcieLinkControl;
+  uint32 pcieLinkCapabilityRc;
+  uint32 bar3Config;
+  uint32 rootCap;
+  uint32 devSerNumCapId;
+  uint32 lowerSerNum;
+  uint32 upperSerNum;
+  uint32 advErrCap;
+  uint32 pwrBdgtData0;
+  uint32 pwrBdgtData1;
+  uint32 pwrBdgtData2;
+  uint32 pwdBdgtData3;
+  uint32 pwrBdgtData4;
+  uint32 pwrBdgtData5;
+  uint32 pwrBdgtData6;
+  uint32 pwrBdgtData7;
+  uint32 pwrBdgtCapability;
+  uint32 vsecHdr;
+  uint32 rcUserMemLo1;
+  uint32 rcUserMemHi1;
+  uint32 rcUserMemLo2;
+  uint32 rcUserMemHi2;
+}PcieBlk428Regs;
+
+typedef struct PcieBlk800Regs{
+#define NUM_PCIE_BLK_800_CTRL_REGS  6
+  uint32 tlControl[NUM_PCIE_BLK_800_CTRL_REGS];
+  uint32 tlCtlStat0;
+  uint32 pmStatus0;
+  uint32 pmStatus1;
+
+#define NUM_PCIE_BLK_800_TAGS       32
+  uint32 tlStatus[NUM_PCIE_BLK_800_TAGS];
+  uint32 tlHdrFcStatus;
+  uint32 tlDataFcStatus;
+  uint32 tlHdrFcconStatus;
+  uint32 tlDataFcconStatus;
+  uint32 tlTargetCreditStatus;
+  uint32 tlCreditAllocStatus;
+  uint32 tlSmlogicStatus;
+} PcieBlk800Regs;
+
+
+typedef struct PcieBlk1000Regs{
+#define NUM_PCIE_BLK_1000_PDL_CTRL_REGS  16
+  uint32 pdlControl[NUM_PCIE_BLK_1000_PDL_CTRL_REGS];
+  uint32 dlattnVec;
+  uint32 dlAttnMask;
+  uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13   
+  uint32 dlTxChecksum;
+  uint32 dlForcedUpdateGen1;
+  uint32 mdioAddr;
+  uint32 mdioWrData;
+  uint32 mdioRdData;
+  uint32 dlRxPFcCl;
+  uint32 dlRxCFcCl;
+  uint32 dlRxAckNack;
+  uint32 dlTxRxSeqnb;
+  uint32 dlTxPFcAl;
+  uint32 dlTxNpFcAl;
+  uint32 regDlSpare;
+  uint32 dlRegSpare;
+  uint32 dlTxRxSeq;
+  uint32 dlRxNpFcCl;
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         5
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+  uint32 phyReceivedMcpErrors;
+  uint32 phyTransmittedMcpErrors;
+  uint32 phyGenDebug;
+  uint32 phyRecoveryHist;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR1_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR1_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR1_REMAP_swap_enable                  1
+   
+   uint32 bar2Remap;       /* 0x081c*/
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK                    0xffff0000
+#define PCIE_BRIDGE_BAR2_REMAP_addr_MASK_SHIFT              16
+#define PCIE_BRIDGE_BAR2_REMAP_remap_enable                 (1<<1)
+#define PCIE_BRIDGE_BAR2_REMAP_swap_enable                  1
+   
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_en_l1_int_status_mask_polarity  (1<<12)
+#define PCIE_BRIDGE_OPT_REG1_en_pcie_bridge_hole_detection   (1<<11)
+#define PCIE_BRIDGE_OPT_REG1_en_rd_reply_be_fix              (1<<9)
+#define PCIE_BRIDGE_OPT_REG1_enable_rd_be_opt                (1<<7)
+   
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+
+   uint32 Ubus2PcieBar0BaseMask; /* 0x0828 */
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR0_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR0_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR0_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR0_BASE_remap_enable                  1
+
+   uint32 Ubus2PcieBar0RemapAdd; /* 0x082c */   
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR0_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 Ubus2PcieBar1BaseMask; /* 0x0830 */
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK                     0xfff00000
+#define PCIE_BRIDGE_BAR1_BASE_base_MASK_SHIFT               20
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK                     0x0000fff0
+#define PCIE_BRIDGE_BAR1_BASE_mask_MASK_SHIFT               4
+#define PCIE_BRIDGE_BAR1_BASE_swap_enable                   (1<<1)
+#define PCIE_BRIDGE_BAR1_BASE_remap_enable                  1   
+   
+   uint32 Ubus2PcieBar1RemapAdd; /* 0x0834 */
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_MASK               0xfff00000
+#define PCIE_BRIDGE_BAR1_REMAP_ADDR_addr_SHIFT              20
+   
+   uint32 bridgeErrStatus;       /* 0x0838 */
+   uint32 bridgeErrMask;         /* 0x083c */   
+   uint32 coreErrStatus2;        /* 0x0840 */
+   uint32 coreErrMask2;          /* 0x0844 */
+   uint32 coreErrStatus1;        /* 0x0848 */
+   uint32 coreErrMask1;          /* 0x084c */
+   uint32 rcInterruptStatus;     /* 0x0850 */
+   uint32 rcInterruptMask;       /* 0x0854 */
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_a_MASK   (1<<0)
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_b_MASK   (1<<1)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_c_MASK   (1<<2)   
+#define PCIE_BRIDGE_INTERRUPT_MASK_int_d_MASK   (1<<3)   
+      
+}PcieBridgeRegs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS                    ((volatile PcieRegs * const) PCIE_BASE)
+
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const) \
+                                        (PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const) \
+                                        (PCIE_BASE+0x428))
+#define PCIEH_BLK_800_REGS            ((volatile PcieBlk800Regs * const) \
+                                        (PCIE_BASE+0x800))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) \
+                                        (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) \
+                                        (PCIE_BASE+0x1800))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const)  \
+                                        (PCIE_BASE+0x2818))
+
+typedef struct WlanShimRegs_a0 {
+    uint32 CcIdA;                               /* CC desc A */
+    uint32 CcIdB;                               /* CC desc B */
+    uint32 CcAddr;                              /* CC base addr */
+    uint32 MacIdA;                              /* MAC desc A */
+    uint32 MacIdB;                              /* MAC desc B */
+    uint32 MacAddr;                             /* MAC base addr */
+    uint32 ShimIdA;                             /* SHIM desc A */
+    uint32 ShimIdB;                             /* SHIM desc B */
+    uint32 ShimAddr;                            /* SHIM addr */
+    uint32 ShimEot;                             /* EOT */
+    uint32 CcControl;                           /* CC control */                                                
+    uint32 CcStatus;                            /* CC status */                                                
+    uint32 MacControl;                          /* MAC control */                                                
+    uint32 MacStatus;                           /* MAC status */    
+    uint32 ShimMisc;                            /* SHIM control registers */
+    uint32 ShimStatus;                          /* SHIM status */       
+}WlanShimRegs_a0;
+
+typedef struct WlanShimRegs_b0 {
+    uint32 ShimMisc;                            /* SHIM control registers */
+#define WLAN_SHIM_FORCE_CLOCKS_ON   (1 << 2)
+#define WLAN_SHIM_MACRO_DISABLE     (1 << 1)
+#define WLAN_SHIM_MACRO_SOFT_RESET  (1 << 0)
+
+    uint32 ShimStatus;                          /* SHIM status */       
+
+    uint32 CcControl;                           /* CC control */
+#define SICF_WOC_CORE_RESET         0x10000    
+#define SICF_BIST_EN                0x8000
+#define SICF_PME_EN                 0x4000      
+#define SICF_CORE_BITS              0x3ffc      
+#define SICF_FGC                    0x0002      
+#define SICF_CLOCK_EN               0x0001      
+
+    uint32 CcStatus;                            /* CC status */
+#define SISF_BIST_DONE              0x8000      
+#define SISF_BIST_ERROR             0x4000      
+#define SISF_GATED_CLK              0x2000      
+#define SISF_DMA64                  0x1000      
+#define SISF_CORE_BITS              0x0fff      
+
+    uint32 MacControl;                          /* MAC control */
+    uint32 MacStatus;                           /* MAC status */
+
+    uint32 CcIdA;                               /* CC desc A */
+    uint32 CcIdB;                               /* CC desc B */
+    uint32 CcAddr;                              /* CC base addr */
+    uint32 MacIdA;                              /* MAC desc A */
+    uint32 MacIdB;                              /* MAC desc B */
+    uint32 MacAddr;                             /* MAC base addr */
+    uint32 ShimIdA;                             /* SHIM desc A */
+    uint32 ShimIdB;                             /* SHIM desc B */
+    uint32 ShimAddr;                            /* SHIM addr */
+    uint32 ShimEot;                             /* EOT */                                                                                                                                            
+}WlanShimRegs_b0;
+
+typedef union WlanShimRegs {
+    WlanShimRegs_a0 a0;
+    WlanShimRegs_b0 b0;                            /* SHIM control registers */
+}WlanShimRegs;
+
+#define WLAN_SHIM                   ((volatile WlanShimRegs * const)WLAN_SHIM_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/opensource/include/bcm963xx/6368_cpu.h b/shared/opensource/include/bcm963xx/6368_cpu.h
new file mode 100755
index 0000000..75cdde2
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6368_cpu.h
@@ -0,0 +1,150 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6368_CPU_H
+#define __BCM6368_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+#************************************************************************
+#* Coprocessor 0 Register Names
+#************************************************************************
+*/
+#define C0_BCM_CONFIG          $22
+
+/*
+# Select 1
+#  Bit  31:   unused
+#  Bits 30:25 MMU Size (Num TLB entries-1)
+#  Bits 24:22 ICache sets/way (2^n * 64)
+#  Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
+#  Bits 18:16 ICache Associativity (n+1) way                    
+#  Bits 15:13 DCache sets/way (2^n * 64)
+#  Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
+#  Bits 9:7   DCache Associativity (n+1) way                    
+#  Bits 6:4   unused
+#  Bit  3:    1=At least 1 watch register
+#  Bit  2:    1=MIPS16 code compression implemented
+#  Bit  1:    1=EJTAG implemented                   
+#  Bit  0:    1=FPU implemented                   
+*/
+#define CP0_CFG_ISMSK      (0x7 << 22)
+#define CP0_CFG_ISSHF      22
+#define CP0_CFG_ILMSK      (0x7 << 19)
+#define CP0_CFG_ILSHF      19
+#define CP0_CFG_IAMSK      (0x7 << 16)
+#define CP0_CFG_IASHF      16
+#define CP0_CFG_DSMSK      (0x7 << 13)
+#define CP0_CFG_DSSHF      13
+#define CP0_CFG_DLMSK      (0x7 << 10)
+#define CP0_CFG_DLSHF      10
+#define CP0_CFG_DAMSK      (0x7 << 7)
+#define CP0_CFG_DASHF      7
+
+/*
+#************************************************************************
+#* Coprocessor 0 Broadcom Config Register Bits
+#************************************************************************
+*/
+#define CP0_BCM_CFG_ICSHEN          (0x1 << 31)
+#define CP0_BCM_CFG_DCSHEN          (0x1 << 30)
+#define CP0_BCM_CFG_BTHD            (0x1 << 21)
+#define CP0_BCM_CFG_CLF             (0x1 << 20)
+#define CP0_BCM_CFG_NBK             (0x1 << 17)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Interrupt Register
+#************************************************************************
+*/
+#define CP0_CMT_XIR_4               (0x1 << 31)
+#define CP0_CMT_XIR_3               (0x1 << 30)
+#define CP0_CMT_XIR_2               (0x1 << 29)
+#define CP0_CMT_XIR_1               (0x1 << 28)
+#define CP0_CMT_XIR_0               (0x1 << 27)
+#define CP0_CMT_SIR_1               (0x1 << 16)
+#define CP0_CMT_SIR_0               (0x1 << 15)
+#define CP0_CMT_NMIR_TP1            (0x1 << 1)
+#define CP0_CMT_NMIR_TP0            (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Control Register
+#************************************************************************
+*/
+#define CP0_CMT_DSU_TP1             (0x1 << 30)
+#define CP0_CMT_TPS_SHFT            16
+#define CP0_CMT_TPS_MASK            (0xF << CP0_CMT_TPS_SHFT)
+#define CP0_CMT_PRIO_TP1            (0x1 << 5)
+#define CP0_CMT_PRIO_TP0            (0x1 << 4)
+#define CP0_CMT_RSTSE               (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Local Register
+#************************************************************************
+*/
+#define CP0_CMT_TPID                (0x1 << 31)
+
+/*
+#************************************************************************
+#* MIPS Registers
+#************************************************************************
+*/
+
+#define MIPS_BASE_BOOT  0xbfa00000
+#define MIPS_BASE       0xff400000
+
+#define MIPS_RAC_CR0    0x00        // RAC Configuration Register
+#define MIPS_RAC_CR1    0x08        // RAC Configuration Register 1
+#define RAC_FLH         (1 << 8)
+#define RAC_DPF         (1 << 6)
+#define RAC_NCH         (1 << 5)
+#define RAC_C_INV       (1 << 4)
+#define RAC_PF_D        (1 << 3)
+#define RAC_PF_I        (1 << 2)
+#define RAC_D           (1 << 1)
+#define RAC_I           (1 << 0)
+
+#define MIPS_RAC_ARR    0x04        // RAC Address Range Register
+#define RAC_UPB_SHFT    16
+#define RAC_LWB_SHFT    0
+
+#define MIPS_LMB_CR     0x1C        // LMB Control Register
+#define LMB_EN          (1 << 0)
+
+#define MIPS_SBR        0x20        // System Base Register
+
+#define MIPS_TP0_ALT_BV 0x30000
+#define MIPS_TP1_ALT_BV 0x38000
+#define ENABLE_ALT_BV   (1 << 19)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/opensource/include/bcm963xx/6368_intr.h b/shared/opensource/include/bcm963xx/6368_intr.h
new file mode 100755
index 0000000..afbca5f
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6368_intr.h
@@ -0,0 +1,123 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __6368_INTR_H
+#define __6368_INTR_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define INTERRUPT_ID_SOFTWARE_0           0
+#define INTERRUPT_ID_SOFTWARE_1           1
+
+/*=====================================================================*/
+/* BCM6368 Timer Interrupt Level Assignments                          */
+/*=====================================================================*/
+#define MIPS_TIMER_INT                  7
+
+/*=====================================================================*/
+/* Peripheral ISR Table Offset                                              */
+/*=====================================================================*/
+#define INTERNAL_ISR_TABLE_OFFSET       8
+#define INTERNAL_HIGH_ISR_TABLE_OFFSET  (INTERNAL_ISR_TABLE_OFFSET + 32)
+
+/*=====================================================================*/
+/* Logical Peripheral Interrupt IDs                                    */
+/*=====================================================================*/
+
+#define INTERRUPT_ID_TIMER               (INTERNAL_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_SPI                 (INTERNAL_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_UART                (INTERNAL_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_UART1               (INTERNAL_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_XDSL                (INTERNAL_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_USBH                (INTERNAL_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_IPSEC               (INTERNAL_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_USBH20              (INTERNAL_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_USBS                (INTERNAL_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_RING_OSC            (INTERNAL_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_NAND_FLASH          (INTERNAL_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_ATM                 (INTERNAL_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_PCM                 (INTERNAL_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_MPI                 (INTERNAL_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_DG                  (INTERNAL_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_EPHY                (INTERNAL_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_EPHY_ENERGY_0       (INTERNAL_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_EPHY_ENERGY_1       (INTERNAL_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_EPHY_ENERGY_2       (INTERNAL_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_EPHY_ENERGY_3       (INTERNAL_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_EXTERNAL_0          (INTERNAL_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_EXTERNAL_1          (INTERNAL_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_EXTERNAL_2          (INTERNAL_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_EXTERNAL_3          (INTERNAL_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_EXTERNAL_4          (INTERNAL_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_EXTERNAL_5          (INTERNAL_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_USB_CNTL_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_USB_CNTL_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_USB_BULK_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_USB_BULK_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_USB_ISO_RX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_USB_ISO_TX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 31)
+#define INTERRUPT_ID_ENETSW_RX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_ENETSW_RX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_ENETSW_RX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_ENETSW_RX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_ENETSW_TX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_ENETSW_TX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_ENETSW_TX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_ENETSW_TX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_ATM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_ATM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_ATM_DMA_2           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_ATM_DMA_3           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_ATM_DMA_4           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_ATM_DMA_5           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_ATM_DMA_6           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_ATM_DMA_7           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_ATM_DMA_8           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_ATM_DMA_9           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_ATM_DMA_10          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_ATM_DMA_11          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_ATM_DMA_12          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_ATM_DMA_13          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_ATM_DMA_14          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_ATM_DMA_15          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_ATM_DMA_16          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_ATM_DMA_17          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_ATM_DMA_18          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_ATM_DMA_19          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_IPSEC_DMA_0         (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_IPSEC_DMA_1         (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_PCM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_PCM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31)
+
+#define INTERRUPT_ID_LAST                INTERRUPT_ID_PCM_DMA_1
+
+#ifdef __cplusplus
+    }
+#endif                    
+
+#endif  /* __BCM6368_H */
+
+
diff --git a/shared/opensource/include/bcm963xx/6368_map_part.h b/shared/opensource/include/bcm963xx/6368_map_part.h
new file mode 100755
index 0000000..165adc2
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6368_map_part.h
@@ -0,0 +1,1035 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6368_MAP_H
+#define __BCM6368_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define NAND_REG_BASE        0xb0000200  /* NAND registers */
+#define NAND_CACHE_BASE      0xb0000600
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define MPI_BASE             0xb0001000  /* MPI control registers */
+#define MEMC_BASE            0xb0001200  /* Memory control registers */
+#define DDR_BASE             0xb0001280  /* DDR IO Buf Control registers */
+#define USB_EHCI_BASE        0x10001500  /* USB host registers */
+#define USB_OHCI_BASE        0x10001600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0001700
+#define SAR_DMA_BASE         0xb0005000  /* ATM SAR DMA control registers */
+
+
+typedef struct MemoryControl
+{
+    uint32 Control;             /* (00) */
+#define MEMC_SELF_REFRESH    (1<<6) // enable self refresh mode
+#define MEMC_MRS             (1<<4) // generate a mode register select cycle
+#define MEMC_PRECHARGE       (1<<3) // generate a precharge cycle
+#define MEMC_REFRESH         (1<<2) // generate an auto refresh cycle
+#define MEMC_SEQUENCE_ENABLE (1<<1) // enable memory controller sequencer
+#define MEMC_MASTER_ENABLE   (1<<0) // enable accesses to external sdram
+
+    uint32  Config;             /* (04) */
+#define MEMC_EARLY_HDR_CNT_SHFT 25
+#define MEMC_EARLY_HDR_CNT_MASK (0x7<<MEMC_EARLYHDRCNT_SHFT)
+#define MEMC_USE_HDR_CNT        (1<<24)
+#define MEMC_EN_FAST_REPLY      (1<<23)
+#define MEMC_RR_ARB             (1<<22)
+#define MEMC_SFX_NO_MRS2        (1<<21)
+#define MEMC_SFX_NO_DLL_RST     (1<<20)
+#define MEMC_LLMB_ONE_REQ       (1<<19)
+#define MEMC_SYS_PORT_CMD_MODE  (1<<18)
+#define MEMC_PAD_OP_MODE        (1<<17)
+#define MEMC_DQS_GATE_EN        (1<<16)
+#define MEMC_PRED_RD_STROBE_EN  (1<<15)
+#define MEMC_PRED_RD_LATENCY_SEL (1<<14)
+#define MEMC_UBUS_CLF_EN        (1<<8)
+
+#define MEMC_ROW_SHFT           6
+#define MEMC_ROW_MASK           (0x3<<MEMC_ROW_SHFT)
+#define MEMC_11BIT_ROW          0
+#define MEMC_12BIT_ROW          1
+#define MEMC_13BIT_ROW          2
+#define MEMC_14BIT_ROW          3
+
+#define MEMC_COL_SHFT           3
+#define MEMC_COL_MASK           (0x7<<MEMC_COL_SHFT)
+#define MEMC_8BIT_COL           0
+#define MEMC_9BIT_COL           1
+#define MEMC_10BIT_COL          2
+#define MEMC_11BIT_COL          3
+
+#define MEMC_SEL_PRIORITY       (1<<2)
+
+#define MEMC_WIDTH_SHFT         1
+#define MEMC_WIDTH_MASK         (0x1<<MEMC_WIDTH_SHFT)
+#define MEMC_32BIT_BUS          0
+#define MEMC_16BIT_BUS          1
+
+#define MEMC_MEMTYPE_SDR        (0<<0)
+#define MEMC_MEMTYPE_DDR        (1<<0)
+
+    uint32  RefreshPdControl;   /* (08) */ 
+#define MEMC_REFRESH_ENABLE     (1<<15)
+
+    uint32  BistStatus;         /* (0C) */
+    uint32  ExtendedModeBuffer; /* (10) */
+    uint32  BankClosingTimer;   /* (14) */
+    uint32  PriorityInversionTimer; /* (18) */
+
+    uint32  DramTiming;         /* (1c) */
+#define MEMC_WR_NOP_RD        (1<<23)
+#define MEMC_WR_NOP_WR        (1<<22)
+#define MEMC_RD_NOP_WR        (1<<21)
+#define MEMC_RD_NOP_RD        (1<<20)
+#define MEMC_CAS_LATENCY_2    (0)
+#define MEMC_CAS_LATENCY_2_5  (1)
+#define MEMC_CAS_LATENCY_3    (2)
+
+    uint32  IntStatus;          /* (20) */
+    uint32  IntMask;            /* (24) */
+#define MEMC_INT3             (1<<3)
+#define MEMC_INT2             (2<<3)
+#define MEMC_INT1             (1<<3)
+#define MEMC_INT0             (0<<3)
+
+    uint32  IntInfo;            /* (28) */
+    uint8   unused5[0x50-0x2c]; /* (2c) */
+    uint32  Barrier;            /* (50) */
+    uint32  CoreId;             /* (54) */
+} MemoryControl;
+
+#define MEMC ((volatile MemoryControl * const) MEMC_BASE)
+
+typedef struct DDRControl {
+    uint32    RevID;            /* 00 */
+    uint32    PadSSTLMode;      /* 04 */
+    uint32    CmdPadCntl;       /* 08 */
+    uint32    DQPadCntl;        /* 0c */
+    uint32    DQSPadCntl;       /* 10 */
+    uint32    ClkPadCntl0;      /* 14 */
+    uint32    MIPSDDRPLLCntl0;  /* 18 */
+    uint32    MIPSDDRPLLCntl1;  /* 1c */
+    uint32    MIPSDDRPLLConfig; /* 20 */
+#define MIPSDDR_NDIV_SHFT       16
+#define MIPSDDR_NDIV_MASK       (0x1ff<<MIPSDDR_NDIV_SHFT)
+#define REF_MDIV_SHFT           8
+#define REF_MDIV_MASK           (0xff<<REF_MDIV_SHFT)
+#define MIPSDDR_P2_SHFT         4
+#define MIPSDDR_P2_MASK         (0xf<<MIPSDDR_P2_SHFT)
+#define MIPSDDR_P1_SHFT         0
+#define MIPSDDR_P1_MASK         (0xf<<MIPSDDR_P1_SHFT)
+    uint32    MIPSDDRPLLMDiv;   /* 24 */
+#define DDR_MDIV_SHFT           8
+#define DDR_MDIV_MASK           (0xff<<DDR_MDIV_SHFT)
+#define MIPS_MDIV_SHFT          0
+#define MIPS_MDIV_MASK          (0xff<<MIPS_MDIV_SHFT)
+    uint32    DSLCorePhaseCntl; /* 28 */
+    uint32    DSLCpuPhaseCntr;  /* 2c */
+#define DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT    28
+#define DSL_PHY_AFE_PI_CNTR_CYCLES_MASK     (0xF << DSL_PHY_AFE_PI_CNTR_CYCLES_SHIFT)
+#define DSL_PHY_PI_CNTR_CYCLES_SHIFT        24
+#define DSL_PHY_PI_CNTR_CYCLES_MASK         (0xF << DSL_PHY_PI_CNTR_CYCLES_SHIFT)
+#define DSL_PHY_AFE_PI_CNTR_EN              (1 << 22)
+#define DSL_PHY_PI_CNTR_EN                  (1 << 21)
+#define DSL_CPU_PI_CNTR_EN                  (1 << 20)
+#define DSL_CPU_PI_CNTR_CYCLES_SHIFT    16
+#define DSL_CPU_PI_CNTR_CYCLES_MASK (0xF << DSL_CPU_PI_CNTR_CYCLES_SHIFT)
+    uint32    MIPSPhaseCntl;    /* 30 */
+#define PH_CNTR_EN              (1 << 20)
+    uint32    DDR1_2PhaseCntl0; /* 34 */
+    uint32    DDR3_4PhaseCntl0; /* 38 */
+    uint32    VCDLPhaseCntl0;   /* 3c */
+    uint32    VCDLPhaseCntl1;   /* 40 */
+    uint32    WSliceCntl;       /* 44 */
+    uint32    DeskewDLLCntl;    /* 48 */
+    uint32    DeskewDLLReset;   /* 4c */
+    uint32    DeskewDLLPhase;   /* 50 */
+    uint32    AnalogTestCntl;   /* 54 */
+    uint32    RdDQSGateCntl;    /* 58 */
+    uint32    PLLTestReg;       /* 5c */
+    uint32    Spare0;           /* 60 */
+    uint32    Spare1;           /* 64 */
+    uint32    Spare2;           /* 68 */
+    uint32    CLBist;           /* 6c */
+    uint32    LBistCRC;         /* 70 */
+    uint32    UBUSPhaseCntl;    /* 74 */
+    uint32    UBUSPIDeskewLLMB0; /* 78 */
+    uint32    UBUSPIDeskewLLMB1; /* 7C */
+
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64		  IrqMask;
+    uint64		  IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+     uint32        RevID;             /* (00) word 0 */
+     uint32        blkEnables;        /* (04) word 1 */
+#define USBH_IDDQ_EN     (1 << 19)
+#define IPSEC_CLK_EN     (1 << 18)
+#define NAND_CLK_EN      (1 << 17)
+#define DISABLE_GLESS    (1 << 16)
+#define USBH_CLK_EN      (1 << 15)
+#define PCM_CLK_EN       (1 << 14)
+#define UTOPIA_CLK_EN    (1 << 13)
+#define ROBOSW_CLK_EN    (1 << 12)
+#define SAR_CLK_EN       (1 << 11)
+#define USBD_CLK_EN      (1 << 10)
+#define SPI_CLK_EN       (1 << 9)
+#define SWPKT_SAR_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define PHYMIPS_CLK_EN   (1 << 6)
+#define VDSL_CLK_EN      (1 << 5)
+#define VDSL_BONDING_EN  (1 << 4)
+#define VDSL_AFE_EN      (1 << 3)
+#define VDSL_QPROC_EN    (1 << 2)
+   
+     uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+     uint32        deviceTimeoutEn;   /* (0c) word 3 */
+     uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_PCM     (1 << 13)
+#define SOFT_RST_USBH    (1 << 12)
+#define SOFT_RST_USBD    (1 << 11)
+#define SOFT_RST_SWITCH  (1 << 10)
+#define SOFT_RST_SAR     (1 << 7)
+#define SOFT_RST_EPHY    (1 << 6)
+#define SOFT_RST_IPSEC   (1 << 4)
+#define SOFT_RST_MPI     (1 << 3)
+#define SOFT_RST_SPI     (1 << 0)
+
+    uint32        unused1;            /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        ExtIrqCfg1;         /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000      
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters 
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to 
+                                           * detect irq on rising AND falling 
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+    uint32      LEDCtrl;
+#define LED_ALL_STROBE          0x0f000000
+#define LED3_STROBE             0x08000000
+#define LED2_STROBE             0x04000000
+#define LED1_STROBE             0x02000000
+#define LED0_STROBE             0x01000000
+#define LED_TEST                0x00010000
+#define DISABLE_LINK_ACT_ALL    0x0000f000
+#define DISABLE_LINK_ACT_3      0x00008000
+#define DISABLE_LINK_ACT_2      0x00004000
+#define DISABLE_LINK_ACT_1      0x00002000
+#define DISABLE_LINK_ACT_0      0x00001000
+#define LED_INTERVAL_SET_MASK   0x00000f00
+#define LED_INTERVAL_SET_1280MS 0x00000700
+#define LED_INTERVAL_SET_640MS  0x00000600
+#define LED_INTERVAL_SET_320MS  0x00000500
+#define LED_INTERVAL_SET_160MS  0x00000400
+#define LED_INTERVAL_SET_80MS   0x00000300
+#define LED_INTERVAL_SET_40MS   0x00000200
+#define LED_INTERVAL_SET_20MS   0x00000100
+#define LED_ON_ALL              0x000000f0
+#define LED_ON_3                0x00000080
+#define LED_ON_2                0x00000040
+#define LED_ON_1                0x00000020
+#define LED_ON_0                0x00000010
+#define LED_ENABLE_ALL          0x0000000f
+#define LED_ENABLE_3            0x00000008
+#define LED_ENABLE_2            0x00000004
+#define LED_ENABLE_1            0x00000002
+#define LED_ENABLE_0            0x00000001
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_SPI_SSN5          (1<<31)
+#define GPIO_MODE_SPI_SSN4          (1<<30)
+#define GPIO_MODE_SPI_SSN3          (1<<29)
+#define GPIO_MODE_SPI_SSN2          (1<<28)
+#define GPIO_MODE_EBI_CS3           (1<<27)
+#define GPIO_MODE_EBI_CS2           (1<<26)
+#define GPIO_MODE_PCMCIA_VS2        (1<<25)
+#define GPIO_MODE_PCMCIA_VS1        (1<<24)
+#define GPIO_MODE_PCMCIA_CD2        (1<<23)
+#define GPIO_MODE_PCMCIA_CD1        (1<<22)
+#define GPIO_MODE_PCI_GNT0          (1<<20)
+#define GPIO_MODE_PCI_REQ0          (1<<19)
+#define GPIO_MODE_PCI_INTB          (1<<18)
+#define GPIO_MODE_PCI_GNT1          (1<<17)
+#define GPIO_MODE_PCI_REQ1          (1<<16)
+#define GPIO_MODE_USBD_LED          (1<<14)
+#define GPIO_MODE_ROBOSW_LED1       (1<<13)
+#define GPIO_MODE_ROBOSW_LED0       (1<<12)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<11)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<10)
+#define GPIO_MODE_EPHY3_LED         (1<<9)
+#define GPIO_MODE_EPHY2_LED         (1<<8)
+#define GPIO_MODE_EPHY1_LED         (1<<7)
+#define GPIO_MODE_EPHY0_LED         (1<<6)
+#define GPIO_MODE_INET_LED          (1<<5)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SYS_IRQ           (1<<2)
+#define GPIO_MODE_ANALOG_AFE_1      (1<<1)
+#define GPIO_MODE_ANALOG_AFE_0      (1<<0)
+
+    uint32      VregConfig;                 /* 1C */
+#define VREG_VSEL1P2_SHIFT      8
+#define VREG_VSEL1P2_MASK       (0x0f<<8)
+#define VREG_VSEL1P2_MIDDLE     9
+
+    uint32      AuxLedInterval;             /* 20 */
+#define AUX_LED_IN_7            0x80000000
+#define AUX_LED_IN_6            0x40000000
+#define AUX_LED_IN_5            0x20000000
+#define AUX_LED_IN_4            0x10000000
+#define AUX_LED_IN_MASK         0xf0000000
+#define LED_IN_3                0x08000000
+#define LED_IN_2                0x04000000
+#define LED_IN_1                0x02000000
+#define LED_IN_0                0x01000000
+#define AUX_LED_TEST            0x00400000
+#define USE_NEW_INTV            0x00200000
+#define LED7_LNK_ORAND          0x00100000
+#define LED7_LNK_MASK           0x000f0000
+#define LED7_LNK_MASK_SHFT      16
+#define LED7_ACT_MASK           0x0000f000
+#define LED7_ACT_MASK_SHFT      12
+#define AUX_FLASH_INTV          0x00000fc0
+#define AUX_FLASH_INTV_SHFT     6
+#define AUX_BLINK_INTV          0x0000003f
+    uint32      AuxLedCtrl;                 /* 24 */
+#define AUX_HW_DISAB_7          0x80000000
+#define AUX_STROBE_7            0x40000000
+#define AUX_MODE_7              0x30000000
+#define AUX_MODE_SHFT_7         28
+#define AUX_HW_DISAB_6          0x08000000
+#define AUX_STROBE_6            0x04000000
+#define AUX_MODE_6              0x03000000
+#define AUX_MODE_SHFT_6         24
+#define AUX_HW_DISAB_5          0x00800000
+#define AUX_STROBE_5            0x00400000
+#define AUX_MODE_5              0x00300000
+#define AUX_MODE_SHFT_5         20
+#define AUX_HW_DISAB_4          0x00080000
+#define AUX_STROBE_4            0x00040000
+#define AUX_MODE_4              0x00030000
+#define AUX_MODE_SHFT_4         16
+#define AUX_HW_DISAB_3          0x00008000
+#define AUX_STROBE_3            0x00004000
+#define AUX_MODE_3              0x00003000
+#define AUX_MODE_SHFT_3         12
+#define AUX_HW_DISAB_2          0x00000800
+#define AUX_STROBE_2            0x00000400
+#define AUX_MODE_2              0x00000300
+#define AUX_MODE_SHFT_2         8
+#define AUX_HW_DISAB_1          0x00000080
+#define AUX_STROBE_1            0x00000040
+#define AUX_MODE_1              0x00000030
+#define AUX_MODE_SHFT_1         4
+#define AUX_HW_DISAB_0          0x00000008
+#define AUX_STROBE_0            0x00000004
+#define AUX_MODE_0              0x00000003
+#define AUX_MODE_SHFT_0         0
+
+#define LED_STEADY_OFF          0x0
+#define LED_FLASH               0x1
+#define LED_BLINK               0x2
+#define LED_STEADY_ON           0x3
+
+    uint32      TestControl;                /* 28 */
+
+    uint32      VDSLControl;                /* 2C */
+#define VDSL_CORE_RESET         (1<<2)
+#define VDSL_MIPS_RESET         (1<<1)
+#define VDSL_MIPS_POR_RESET     (1<<0)
+#define VDSL_CLK_RATIO_SHIFT    8
+#define VDSL_CLK_RATIO_MSK      (0x1F << VDSL_CLK_RATIO_SHIFT)
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define EN_PCI_CLK_66           (1<<20)
+#define EN_UTO_CLK_FAST         (1<<19)
+#define EN_UTO                  (1<<18)
+#define EN_GMII2                (1<<17)
+#define EN_GMII1                (1<<16)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define RSW_HW_FWDG_EN          (1<<19)
+#define RSW_MII_DUMB_FWDG_EN    (1<<16)
+#define EPHY_RST_4              (1<<9)
+#define EPHY_RST_3              (1<<8)
+#define EPHY_RST_2              (1<<7)
+#define EPHY_RST_1              (1<<6)
+#define EPHY_PWR_DOWN_4         (1<<5)
+#define EPHY_PWR_DOWN_3         (1<<4)
+#define EPHY_PWR_DOWN_2         (1<<3)
+#define EPHY_PWR_DOWN_1         (1<<2)
+#define EPHY_PWR_DOWN_DLL       (1<<1)
+#define EPHY_PWR_DOWN_BIAS      (1<<0)
+    uint32      StrapBus;                   /* 40 */
+#define UTOPIA_MASTER_ON        (1<<14)
+#define MISC_STRAP_BUS_BOOT_SEL_MASK     0x3
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT    0
+#define MISC_STRAP_BUS_BOOT_PARALLEL     0x03
+#define MISC_STRAP_BUS_BOOT_SERIAL       0x01
+#define MISC_STRAP_BUS_BOOT_NAND         0x00
+    uint32      StrapOverride;              /* 44 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES         8
+#define RING_OSC_512_CYCLES         9
+#define RING_OSC_1024_CYCLES        10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK        (0x7f<<24)
+#define RING_OSC_ENABLE_SHIFT       24
+#define RING_OSC_MAX                7
+#define RING_OSC_COUNT_RESET        (0x1<<23)
+#define RING_OSC_SELECT_MASK        (0x7<<20)
+#define RING_OSC_SELECT_SHIFT       20
+#define RING_OSC_IRQ                (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW   (0x1<<17)
+#define RING_OSC_COUNTER_BUSY       (0x1<<16)
+#define RING_OSC_COUNT_MASK         0x0000ffff
+
+    uint32      SerialLed;                  /* 50 */
+    uint32      SerialLedCtrl;              /* 54 */
+#define SER_LED_BUSY            (1<<3)
+#define SER_LED_POLARITY        (1<<2)
+#define SER_LED_DIV_1           0
+#define SER_LED_DIV_2           1
+#define SER_LED_DIV_4           2
+#define SER_LED_DIV_8           3
+#define SER_LED_DIV_MASK        0x3
+#define SER_LED_DIV_SHIFT       0
+    uint32    unused2[4];                   /* 58 */
+    uint32    DieRevID;                     /* 68 */
+    uint32    DiagMemStatus;                /* 6c */
+    uint32    DiagSelControl;               /* 70 */
+    uint32    DiagReadBack;                 /* 74 */
+    uint32    DiagReadBackHi;               /* 78 */
+    uint32    DiagMiscControl;              /* 7c */
+#define EPHY_SA_RESET_N           0x00000300
+#define EPHY_SA_TESTEN            0x00000500
+#define EPHY_SA_CLOCK_RESET       0x0000d900
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    40
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2; 
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3; 
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+/*
+** DMA Buffer 
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** External Bus Interface
+*/
+typedef struct EbiChipSelect {
+    uint32    base;                         /* base address in upper 24 bits */
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+    uint32    config;
+#define EBI_ENABLE          0x00000001      /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
+#define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
+#define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
+#define EBI_WREN            0x00000020      /* enable posted writes */
+#define EBI_POLARITY        0x00000040      /* .. set to invert something, 
+                                        **    don't know what yet */
+#define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200      /* .. use fifo */
+#define EBI_RE              0x00000400      /* .. Reverse Endian */
+#define EBI_SETUP_SHIFT     16
+#define EBI_HOLD_SHIFT      20
+#define EBI_SETUP_STATES    0x0f0000
+#define EBI_HOLD_STATES     0xf00000
+} EbiChipSelect;
+
+typedef struct MpiRegisters {
+  EbiChipSelect cs[7];                  /* size chip select configuration */
+#define EBI_CS0_BASE            0
+#define EBI_CS1_BASE            1
+#define EBI_CS2_BASE            2
+#define EBI_CS3_BASE            3
+#define PCMCIA_COMMON_BASE      4
+#define PCMCIA_ATTRIBUTE_BASE   5
+#define PCMCIA_IO_BASE          6
+  uint32        unused0[2];             /* reserved */
+  uint32        ebi_control;            /* ebi control */
+  uint32        unused1[4];             /* reserved */
+#define EBI_ACCESS_TIMEOUT      0x000007FF
+  uint32        pcmcia_cntl1;           /* pcmcia control 1 */
+#define PCCARD_CARD_RESET       0x00040000
+#define CARDBUS_ENABLE          0x00008000
+#define PCMCIA_ENABLE           0x00004000
+#define PCMCIA_GPIO_ENABLE      0x00002000
+#define CARDBUS_IDSEL           0x00001F00
+#define VS2_OEN                 0x00000080
+#define VS1_OEN                 0x00000040
+#define VS2_OUT                 0x00000020
+#define VS1_OUT                 0x00000010
+#define VS2_IN                  0x00000008
+#define VS1_IN                  0x00000004
+#define CD2_IN                  0x00000002
+#define CD1_IN                  0x00000001
+#define VS_MASK                 0x0000000C
+#define CD_MASK                 0x00000003
+  uint32        unused2;                /* reserved */
+  uint32        pcmcia_cntl2;           /* pcmcia control 2 */
+#define PCMCIA_BYTESWAP_DIS     0x00000002
+#define PCMCIA_HALFWORD_EN      0x00000001
+#define RW_ACTIVE_CNT_BIT       2
+#define INACTIVE_CNT_BIT        8
+#define CE_SETUP_CNT_BIT        16
+#define CE_HOLD_CNT_BIT         24
+  uint32        unused3[40];            /* reserved */
+
+  uint32        sp0range;               /* PCI to internal system bus address space */
+#define ADDR_SPACE_MASK         0xFFFF0000
+  uint32        sp0remap;
+  uint32        sp0cfg;
+  uint32        sp1range;
+  uint32        sp1remap;
+  uint32        sp1cfg;
+
+  uint32        EndianCfg;
+
+  uint32        l2pcfgctl;              /* internal system bus to PCI IO/Cfg control */
+#define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
+#define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
+#define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
+#define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
+#define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
+#define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
+
+  uint32        l2pmrange1;             /* internal system bus to PCI memory space */
+#define PCI_SIZE_64K            0xFFFF0000
+#define PCI_SIZE_128K           0xFFFE0000
+#define PCI_SIZE_256K           0xFFFC0000
+#define PCI_SIZE_512K           0xFFF80000
+#define PCI_SIZE_1M             0xFFF00000
+#define PCI_SIZE_2M             0xFFE00000
+#define PCI_SIZE_4M             0xFFC00000
+#define PCI_SIZE_8M             0xFF800000
+#define PCI_SIZE_16M            0xFF000000
+#define PCI_SIZE_32M            0xFE000000
+  uint32        l2pmbase1;              /* kseg0 or kseg1 address & 0x1FFFFFFF */
+  uint32        l2pmremap1;
+#define CARDBUS_MEM             0x00000004
+#define MEM_WINDOW_EN           0x00000001
+  uint32        l2pmrange2;
+  uint32        l2pmbase2;
+  uint32        l2pmremap2;
+  uint32        l2piorange;             /* internal system bus to PCI I/O space */
+  uint32        l2piobase;
+  uint32        l2pioremap;
+
+  uint32        pcimodesel;
+#define PCI_INT_BUS_RD_PREFETCH 0x000001F0
+#define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
+#define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
+
+  uint32        pciintstat;             /* PCI interrupt mask/status */
+#define MAILBOX1_SENT           0x08
+#define MAILBOX0_SENT           0x04
+#define MAILBOX1_MSG_RCV        0x02
+#define MAILBOX0_MSG_RCV        0x01
+  uint32        locbuscntrl;            /* internal system bus control */
+#define DIR_U2P_NOSWAP          0x00000002
+#define EN_PCI_GPIO             0x00000001
+  uint32        locintstat;             /* internal system bus interrupt mask/status */
+#define CSERR                   0x0200
+#define SERR                    0x0100
+#define EXT_PCI_INT             0x0080
+#define DIR_FAILED              0x0040
+#define DIR_COMPLETE            0x0020
+#define PCI_CFG                 0x0010
+  uint32        unused4[7];
+
+  uint32        mailbox0;
+  uint32        mailbox1;
+
+  uint32        pcicfgcntrl;            /* internal system bus PCI configuration control */
+#define PCI_CFG_REG_WRITE_EN    0x00000080
+#define PCI_CFG_ADDR            0x0000003C
+  uint32        pcicfgdata;             /* internal system bus PCI configuration data */
+
+  uint32        locch2ctl;              /* PCI to interrnal system bus DMA (downstream) local control */
+#define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
+#define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
+#define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
+#define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
+  uint32        locch2intStat;
+#define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
+#define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
+#define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
+  uint32        locch2intMask;
+  uint32        unused5;
+  uint32        locch2descaddr;
+  uint32        locch2status1;
+#define LOCAL_DESC_STATE        0xE0000000
+#define PCI_DESC_STATE          0x1C000000
+#define BYTE_DONE               0x03FFC000
+#define RING_ADDR               0x00003FFF
+  uint32        locch2status2;
+#define BUFPTR_OFFSET           0x1FFF0000
+#define PCI_MASTER_STATE        0x000000C0
+#define LOC_MASTER_STATE        0x00000038
+#define CONTROL_STATE           0x00000007
+  uint32        unused6;
+
+  uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
+#define DMA_U2P_LE              0x00000200  /* local bus is little endian */
+#define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
+  uint32        locch1intstat;
+  uint32        locch1intmask;
+  uint32        unused7;
+  uint32        locch1descaddr;
+  uint32        locch1status1;
+  uint32        locch1status2;
+  uint32        unused8;
+
+  uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
+  uint32        pcich1intstat;
+  uint32        pcich1intmask;
+  uint32        pcich1descaddr;
+  uint32        pcich1status1;
+  uint32        pcich1status2;
+
+  uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
+  uint32        pcich2intstat;
+  uint32        pcich2intmask;
+  uint32        pcich2descaddr;
+  uint32        pcich2status1;
+  uint32        pcich2status2;
+
+  uint32        perm_id;                /* permanent device and vendor id */
+  uint32        perm_rev;               /* permanent revision id */
+} MpiRegisters;
+
+#define MPI ((volatile MpiRegisters * const) MPI_BASE)
+
+/* PCI configuration address space start offset 0x40 */
+#define BRCM_PCI_CONFIG_TIMER               0x40
+#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK    0x0000FF00
+#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK     0x000000FF
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/opensource/include/bcm963xx/6816_cpu.h b/shared/opensource/include/bcm963xx/6816_cpu.h
new file mode 100755
index 0000000..56afce7
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6816_cpu.h
@@ -0,0 +1,150 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6816_CPU_H
+#define __BCM6816_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+#************************************************************************
+#* Coprocessor 0 Register Names
+#************************************************************************
+*/
+#define C0_BCM_CONFIG          $22
+
+/*
+# Select 1
+#  Bit  31:   unused
+#  Bits 30:25 MMU Size (Num TLB entries-1)
+#  Bits 24:22 ICache sets/way (2^n * 64)
+#  Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
+#  Bits 18:16 ICache Associativity (n+1) way                    
+#  Bits 15:13 DCache sets/way (2^n * 64)
+#  Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
+#  Bits 9:7   DCache Associativity (n+1) way                    
+#  Bits 6:4   unused
+#  Bit  3:    1=At least 1 watch register
+#  Bit  2:    1=MIPS16 code compression implemented
+#  Bit  1:    1=EJTAG implemented                   
+#  Bit  0:    1=FPU implemented                   
+*/
+#define CP0_CFG_ISMSK      (0x7 << 22)
+#define CP0_CFG_ISSHF      22
+#define CP0_CFG_ILMSK      (0x7 << 19)
+#define CP0_CFG_ILSHF      19
+#define CP0_CFG_IAMSK      (0x7 << 16)
+#define CP0_CFG_IASHF      16
+#define CP0_CFG_DSMSK      (0x7 << 13)
+#define CP0_CFG_DSSHF      13
+#define CP0_CFG_DLMSK      (0x7 << 10)
+#define CP0_CFG_DLSHF      10
+#define CP0_CFG_DAMSK      (0x7 << 7)
+#define CP0_CFG_DASHF      7
+
+/*
+#************************************************************************
+#* Coprocessor 0 Broadcom Config Register Bits
+#************************************************************************
+*/
+#define CP0_BCM_CFG_ICSHEN          (0x1 << 31)
+#define CP0_BCM_CFG_DCSHEN          (0x1 << 30)
+#define CP0_BCM_CFG_BTHD            (0x1 << 21)
+#define CP0_BCM_CFG_CLF             (0x1 << 20)
+#define CP0_BCM_CFG_NBK             (0x1 << 17)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Interrupt Register
+#************************************************************************
+*/
+#define CP0_CMT_XIR_4               (0x1 << 31)
+#define CP0_CMT_XIR_3               (0x1 << 30)
+#define CP0_CMT_XIR_2               (0x1 << 29)
+#define CP0_CMT_XIR_1               (0x1 << 28)
+#define CP0_CMT_XIR_0               (0x1 << 27)
+#define CP0_CMT_SIR_1               (0x1 << 16)
+#define CP0_CMT_SIR_0               (0x1 << 15)
+#define CP0_CMT_NMIR_TP1            (0x1 << 1)
+#define CP0_CMT_NMIR_TP0            (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Control Register
+#************************************************************************
+*/
+#define CP0_CMT_DSU_TP1             (0x1 << 30)
+#define CP0_CMT_TPS_SHFT            16
+#define CP0_CMT_TPS_MASK            (0xF << CP0_CMT_TPS_SHFT)
+#define CP0_CMT_PRIO_TP1            (0x1 << 5)
+#define CP0_CMT_PRIO_TP0            (0x1 << 4)
+#define CP0_CMT_RSTSE               (0x1 << 0)
+
+/*
+#************************************************************************
+#* Coprocessor 0 CMT Local Register
+#************************************************************************
+*/
+#define CP0_CMT_TPID                (0x1 << 31)
+
+/*
+#************************************************************************
+#* MIPS Registers
+#************************************************************************
+*/
+
+#define MIPS_BASE_BOOT  0xbfa00000
+#define MIPS_BASE       0xff400000
+
+#define MIPS_RAC_CR0    0x00        // RAC Configuration Register
+#define MIPS_RAC_CR1    0x08        // RAC Configuration Register 1
+#define RAC_FLH         (1 << 8)
+#define RAC_DPF         (1 << 6)
+#define RAC_NCH         (1 << 5)
+#define RAC_C_INV       (1 << 4)
+#define RAC_PF_D        (1 << 3)
+#define RAC_PF_I        (1 << 2)
+#define RAC_D           (1 << 1)
+#define RAC_I           (1 << 0)
+
+#define MIPS_RAC_ARR    0x04        // RAC Address Range Register
+#define RAC_UPB_SHFT    16
+#define RAC_LWB_SHFT    0
+
+#define MIPS_LMB_CR     0x1C        // LMB Control Register
+#define LMB_EN          (1 << 0)
+
+#define MIPS_SBR        0x20        // System Base Register
+
+#define MIPS_TP0_ALT_BV 0x30000
+#define MIPS_TP1_ALT_BV 0x38000
+#define ENABLE_ALT_BV   (1 << 19)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/shared/opensource/include/bcm963xx/6816_intr.h b/shared/opensource/include/bcm963xx/6816_intr.h
new file mode 100755
index 0000000..6a8d9e8
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6816_intr.h
@@ -0,0 +1,116 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __6816_INTR_H
+#define __6816_INTR_H
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+
+#define INTERRUPT_ID_SOFTWARE_0           0
+#define INTERRUPT_ID_SOFTWARE_1           1
+
+/*=====================================================================*/
+/* BCM6816 Timer Interrupt Level Assignments                          */
+/*=====================================================================*/
+#define MIPS_TIMER_INT                  7
+
+/*=====================================================================*/
+/* Peripheral ISR Table Offset                                              */
+/*=====================================================================*/
+#define INTERNAL_ISR_TABLE_OFFSET       8
+#define INTERNAL_HIGH_ISR_TABLE_OFFSET  (INTERNAL_ISR_TABLE_OFFSET + 32)
+
+/*=====================================================================*/
+/* Logical Peripheral Interrupt IDs                                    */
+/*=====================================================================*/
+
+#define INTERRUPT_ID_TIMER               (INTERNAL_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_SPI                 (INTERNAL_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_UART                (INTERNAL_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_UART1               (INTERNAL_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_DG                  (INTERNAL_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_USBH                (INTERNAL_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_IPSEC               (INTERNAL_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_USBH20              (INTERNAL_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_USBS                (INTERNAL_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_RING_OSC            (INTERNAL_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_NAND_FLASH          (INTERNAL_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_GPON                (INTERNAL_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_APM                 (INTERNAL_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_MPI                 (INTERNAL_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_EPHY                (INTERNAL_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_PCIE_NMI            (INTERNAL_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_PCIE_A              (INTERNAL_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_PCIE_B              (INTERNAL_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_PCIE_C              (INTERNAL_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_PCIE_D              (INTERNAL_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_EXTERNAL_0          (INTERNAL_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_EXTERNAL_1          (INTERNAL_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_EXTERNAL_2          (INTERNAL_ISR_TABLE_OFFSET + 22)
+#define INTERRUPT_ID_EXTERNAL_3          (INTERNAL_ISR_TABLE_OFFSET + 23)
+#define INTERRUPT_ID_EXTERNAL_4          (INTERNAL_ISR_TABLE_OFFSET + 24)
+#define INTERRUPT_ID_EXTERNAL_5          (INTERNAL_ISR_TABLE_OFFSET + 25)
+#define INTERRUPT_ID_USB_CNTL_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 26)
+#define INTERRUPT_ID_USB_CNTL_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 27)
+#define INTERRUPT_ID_USB_BULK_RX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_USB_BULK_TX_DMA     (INTERNAL_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_USB_ISO_RX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 30)
+#define INTERRUPT_ID_USB_ISO_TX_DMA      (INTERNAL_ISR_TABLE_OFFSET + 31)
+#define INTERRUPT_ID_ENETSW_RX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 0)
+#define INTERRUPT_ID_ENETSW_RX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 1)
+#define INTERRUPT_ID_ENETSW_RX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 2)
+#define INTERRUPT_ID_ENETSW_RX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 3)
+#define INTERRUPT_ID_ENETSW_TX_DMA_0     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 4)
+#define INTERRUPT_ID_ENETSW_TX_DMA_1     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 5)
+#define INTERRUPT_ID_ENETSW_TX_DMA_2     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 6)
+#define INTERRUPT_ID_ENETSW_TX_DMA_3     (INTERNAL_HIGH_ISR_TABLE_OFFSET + 7)
+#define INTERRUPT_ID_MOCA_STOP           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 8)
+#define INTERRUPT_ID_MOCA_START          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 9)
+#define INTERRUPT_ID_MOCA_GEN            (INTERNAL_HIGH_ISR_TABLE_OFFSET + 10)
+#define INTERRUPT_ID_MOCA_WDG            (INTERNAL_HIGH_ISR_TABLE_OFFSET + 11)
+#define INTERRUPT_ID_EPHY_ENERGY_0       (INTERNAL_HIGH_ISR_TABLE_OFFSET + 12)
+#define INTERRUPT_ID_EPHY_ENERGY_1       (INTERNAL_HIGH_ISR_TABLE_OFFSET + 13)
+#define INTERRUPT_ID_GPON_DMA_0          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 14)
+#define INTERRUPT_ID_GPON_DMA_1          (INTERNAL_HIGH_ISR_TABLE_OFFSET + 15)
+#define INTERRUPT_ID_APM_DMA_0           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 16)
+#define INTERRUPT_ID_APM_DMA_1           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 17)
+#define INTERRUPT_ID_APM_DMA_2           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 18)
+#define INTERRUPT_ID_APM_DMA_3           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 19)
+#define INTERRUPT_ID_APM_DMA_4           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 20)
+#define INTERRUPT_ID_APM_DMA_5           (INTERNAL_HIGH_ISR_TABLE_OFFSET + 21)
+#define INTERRUPT_ID_IPSEC_DMA_0         (INTERNAL_HIGH_ISR_TABLE_OFFSET + 28)
+#define INTERRUPT_ID_IPSEC_DMA_1         (INTERNAL_HIGH_ISR_TABLE_OFFSET + 29)
+#define INTERRUPT_ID_I2C                 (INTERNAL_HIGH_ISR_TABLE_OFFSET + 31)
+
+#define INTERRUPT_ID_LAST                INTERRUPT_ID_I2C
+
+#ifdef __cplusplus
+    }
+#endif                    
+
+#endif  /* __BCM6816_H */
+
+
diff --git a/shared/opensource/include/bcm963xx/6816_map_part.h b/shared/opensource/include/bcm963xx/6816_map_part.h
new file mode 100755
index 0000000..f7aa541
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/6816_map_part.h
@@ -0,0 +1,1487 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM6816_MAP_H
+#define __BCM6816_MAP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "bcmtypes.h"
+
+#define PERF_BASE            0xb0000000  /* chip control registers */
+#define TIMR_BASE            0xb0000040  /* timer registers */
+#define GPIO_BASE            0xb0000080  /* gpio registers */
+#define UART_BASE            0xb0000100  /* uart registers */
+#define UART1_BASE           0xb0000120  /* uart registers */
+#define SPI_BASE             0xb0000800  /* SPI master controller registers */
+#define HSSPIM_BASE          0xb0001000  /* High-Speed SPI registers */
+#define MISC_BASE            0xb0001800  /* Miscellaneous Registers */
+#define NAND_REG_BASE        0xb0002000  /* NAND registers */
+#define MPI_BASE             0xb00020A0  /* MPI control registers */
+#define NAND_CACHE_BASE      0xb0002200
+#define USB_CTL_BASE         0xb0002400  /* USB 2.0 device control registers */
+#define USB_EHCI_BASE        0x10002500  /* USB host registers */
+#define USB_OHCI_BASE        0x10002600  /* USB host registers */
+#define USBH_CFG_BASE        0xb0002700
+#define DDR_BASE             0xb0003000  /* Memory control registers */
+#define GPON_SERDES_BASE     0xb0004800  /* GPON SERDES Interface Registers */
+#define APM_HVG_BASE         0xb0008300  /* High-Voltage Generation */
+#define APM_HVG_BASE_REG_15  0xb0008408  /* High-Voltage Generation Register 15 */
+#define APM_HVG_BASE_REG_19  0xb0008488  /* High-Voltage Generation Register 19 */
+#define PCIE_BASE            0xb0e40000  /* PCIE registers */
+
+typedef struct DDRPhyControl {
+    uint32 REVISION;               /* 0x00 */
+    uint32 CLK_PM_CTRL;            /* 0x04 */
+    uint32 unused0[2];             /* 0x08-0x10 */
+    uint32 PLL_STATUS;             /* 0x10 */
+    uint32 PLL_CONFIG;             /* 0x14 */
+    uint32 PLL_PRE_DIVIDER;        /* 0x18 */
+    uint32 PLL_DIVIDER;            /* 0x1c */
+    uint32 PLL_CONTROL1;           /* 0x20 */
+    uint32 PLL_CONTROL2;           /* 0x24 */
+    uint32 PLL_SS_EN;              /* 0x28 */
+    uint32 PLL_SS_CFG;             /* 0x2c */
+    uint32 STATIC_VDL_OVERRIDE;    /* 0x30 */
+    uint32 DYNAMIC_VDL_OVERRIDE;   /* 0x34 */
+    uint32 IDLE_PAD_CONTROL;       /* 0x38 */
+    uint32 ZQ_PVT_COMP_CTL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;          /* 0x40 */
+    uint32 CLOCK_REG_CONTROL;      /* 0x44 */
+    uint32 unused1[46];
+} DDRPhyControl;
+
+typedef struct DDRPhyByteLaneControl {
+    uint32 REVISION;                /* 0x00 */
+    uint32 VDL_CALIBRATE;           /* 0x04 */
+    uint32 VDL_STATUS;              /* 0x08 */
+    uint32 unused;                  /* 0x0c */
+    uint32 VDL_OVERRIDE_0;          /* 0x10 */
+    uint32 VDL_OVERRIDE_1;          /* 0x14 */
+    uint32 VDL_OVERRIDE_2;          /* 0x18 */
+    uint32 VDL_OVERRIDE_3;          /* 0x1c */
+    uint32 VDL_OVERRIDE_4;          /* 0x20 */
+    uint32 VDL_OVERRIDE_5;          /* 0x24 */
+    uint32 VDL_OVERRIDE_6;          /* 0x28 */
+    uint32 VDL_OVERRIDE_7;          /* 0x2c */
+    uint32 READ_CONTROL;            /* 0x30 */
+    uint32 READ_FIFO_STATUS;        /* 0x34 */
+    uint32 READ_FIFO_CLEAR;         /* 0x38 */
+    uint32 IDLE_PAD_CONTROL;        /* 0x3c */
+    uint32 DRIVE_PAD_CTL;           /* 0x40 */
+    uint32 CLOCK_PAD_DISABLE;       /* 0x44 */
+    uint32 WR_PREAMBLE_MODE;        /* 0x48 */
+    uint32 CLOCK_REG_CONTROL;       /* 0x4C */
+    uint32 unused0[44];
+} DDRPhyByteLaneControl;
+
+typedef struct DDRControl {
+    uint32 CNFG;                            /* 0x000 */
+    uint32 CSST;                            /* 0x004 */
+    uint32 CSEND;                           /* 0x008 */
+    uint32 unused;                          /* 0x00c */
+    uint32 ROW00_0;                         /* 0x010 */
+    uint32 ROW00_1;                         /* 0x014 */
+    uint32 ROW01_0;                         /* 0x018 */
+    uint32 ROW01_1;                         /* 0x01c */
+    uint32 unused0[4];
+    uint32 ROW20_0;                         /* 0x030 */
+    uint32 ROW20_1;                         /* 0x034 */
+    uint32 ROW21_0;                         /* 0x038 */
+    uint32 ROW21_1;                         /* 0x03c */
+    uint32 unused1[4];
+    uint32 COL00_0;                         /* 0x050 */
+    uint32 COL00_1;                         /* 0x054 */
+    uint32 COL01_0;                         /* 0x058 */
+    uint32 COL01_1;                         /* 0x05c */
+    uint32 unused2[4];
+    uint32 COL20_0;                         /* 0x070 */
+    uint32 COL20_1;                         /* 0x074 */
+    uint32 COL21_0;                         /* 0x078 */
+    uint32 COL21_1;                         /* 0x07c */
+    uint32 unused3[4];
+    uint32 BNK10;                           /* 0x090 */
+    uint32 BNK32;                           /* 0x094 */
+    uint32 unused4[26];
+    uint32 DCMD;                            /* 0x100 */
+#define DCMD_CS1          (1 << 5)
+#define DCMD_CS0          (1 << 4)
+#define DCMD_SET_SREF     4
+    uint32 DMODE_0;                         /* 0x104 */
+    uint32 DMODE_1;                         /* 0x108 */
+#define DMODE_1_DRAMSLEEP (1 << 11)
+    uint32 CLKS;                            /* 0x10c */
+    uint32 ODT;                             /* 0x110 */
+    uint32 TIM1_0;                          /* 0x114 */
+    uint32 TIM1_1;                          /* 0x118 */
+    uint32 TIM2;                            /* 0x11c */
+    uint32 CTL_CRC;                         /* 0x120 */
+    uint32 DOUT_CRC;                        /* 0x124 */
+    uint32 DIN_CRC;                         /* 0x128 */
+    uint32 unused5[53];
+
+    DDRPhyControl           PhyControl;             /* 0x200 */
+    DDRPhyByteLaneControl   PhyByteLane0Control;    /* 0x300 */
+    DDRPhyByteLaneControl   PhyByteLane1Control;    /* 0x400 */
+    DDRPhyByteLaneControl   PhyByteLane2Control;    /* 0x500 */
+    DDRPhyByteLaneControl   PhyByteLane3Control;    /* 0x600 */
+    uint32 unused6[64];
+
+    uint32 GCFG;                            /* 0x800 */
+    uint32 LBIST_CFG;                       /* 0x804 */
+    uint32 LBIST_SEED;                      /* 0x808 */
+    uint32 ARB;                             /* 0x80c */
+    uint32 PI_GCF;                          /* 0x810 */
+    uint32 PI_UBUS_CTL;                     /* 0x814 */
+    uint32 PI_MIPS_CTL;                     /* 0x818 */
+    uint32 PI_DSL_MIPS_CTL;                 /* 0x81c */
+    uint32 PI_DSL_PHY_CTL;                  /* 0x820 */
+    uint32 PI_UBUS_ST;                      /* 0x824 */
+    uint32 PI_MIPS_ST;                      /* 0x828 */
+    uint32 PI_DSL_MIPS_ST;                  /* 0x82c */
+    uint32 PI_DSL_PHY_ST;                   /* 0x830 */
+    uint32 PI_UBUS_SMPL;                    /* 0x834 */
+    uint32 TESTMODE;                        /* 0x838 */
+    uint32 TEST_CFG1;                       /* 0x83c */
+    uint32 TEST_PAT;                        /* 0x840 */
+    uint32 TEST_COUNT;                      /* 0x844 */
+    uint32 TEST_CURR_COUNT;                 /* 0x848 */
+    uint32 TEST_ADDR_UPDT;                  /* 0x84c */
+    uint32 TEST_ADDR;                       /* 0x850 */
+    uint32 TEST_DATA0;                      /* 0x854 */
+    uint32 TEST_DATA1;                      /* 0x858 */
+    uint32 TEST_DATA2;                      /* 0x85c */
+    uint32 TEST_DATA3;                      /* 0x860 */
+} DDRControl;
+
+#define DDR ((volatile DDRControl * const) DDR_BASE)
+
+/*
+** Peripheral Controller
+*/
+
+#define IRQ_BITS 64
+typedef struct  {
+    uint64		  IrqMask;
+    uint64		  IrqStatus;
+} IrqControl_t;
+
+typedef struct PerfControl {
+    uint32        RevID;             /* (00) word 0 */
+    uint32        blkEnables;        /* (04) word 1 */
+#define ACP_A_CLK_EN     (1 << 25)
+#define ACP_B_CLK_EN     (1 << 24)
+#define NTP_CLK_EN       (1 << 23)
+#define PCM_CLK_EN       (1 << 22)
+#define BMU_CLK_EN       (1 << 21)
+#define PCIE_CLK_EN      (1 << 20)
+#define GPON_SER_CLK_EN  (1 << 19)
+#define IPSEC_CLK_EN     (1 << 18)
+#define NAND_CLK_EN      (1 << 17)
+#define DISABLE_GLESS    (1 << 16)
+#define USBH_CLK_EN      (1 << 15)
+#define APM_CLK_EN       (1 << 14)
+#define ROBOSW_CLK_EN    (1 << 12)
+#define USBD_CLK_EN      (1 << 10)
+#define SPI_CLK_EN       (1 << 9)
+#define SWPKT_GPON_CLK_EN (1 << 8)
+#define SWPKT_USB_CLK_EN (1 << 7)
+#define GPON_CLK_EN      (1 << 6)
+
+    uint32        pll_control;       /* (08) word 2 */
+#define SOFT_RESET              0x00000001      // 0
+
+    uint32        deviceTimeoutEn;   /* (0c) word 3 */
+    uint32        softResetB;        /* (10) word 4 */
+#define SOFT_RST_SERDES_DIG     (1 << 23)
+#define SOFT_RST_SERDES         (1 << 22)
+#define SOFT_RST_SERDES_MDIO    (1 << 21)
+#define SOFT_RST_SERDES_PLL     (1 << 20)
+#define SOFT_RST_SERDES_HW      (1 << 19)
+#define SOFT_RST_GPON           (1 << 18)
+#define SOFT_RST_BMU            (1 << 17)
+#define SOFT_RST_HVG            (1 << 16)
+#define SOFT_RST_APM            (1 << 15)
+#define SOFT_RST_ACP            (1 << 14)
+#define SOFT_RST_PCM            (1 << 13)
+#define SOFT_RST_USBH           (1 << 12)
+#define SOFT_RST_USBD           (1 << 11)
+#define SOFT_RST_SWITCH         (1 << 10)
+#define SOFT_RST_MOCA_CPU       (1 << 9)
+#define SOFT_RST_MOCA_SYS       (1 << 8)
+#define SOFT_RST_MOCA           (1 << 7)
+#define SOFT_RST_EPHY           (1 << 6)
+#define SOFT_RST_PCIE           (1 << 5)
+#define SOFT_RST_IPSEC          (1 << 4)
+#define SOFT_RST_MPI            (1 << 3)
+#define SOFT_RST_PCIE_EXT       (1 << 2)
+#define SOFT_RST_PCIE_CORE      (1 << 1)
+#define SOFT_RST_SPI            (1 << 0)
+
+    uint32        diagControl;        /* (14) word 5 */
+    uint32        ExtIrqCfg;          /* (18) word 6*/
+    uint32        ExtIrqCfg1;         /* (1c) word 7 */
+#define EI_SENSE_SHFT   0
+#define EI_STATUS_SHFT  4
+#define EI_CLEAR_SHFT   8
+#define EI_MASK_SHFT    12
+#define EI_INSENS_SHFT  16
+#define EI_LEVEL_SHFT   20
+
+     IrqControl_t IrqControl[2];
+} PerfControl;
+
+#define PERF ((volatile PerfControl * const) PERF_BASE)
+
+/*
+** Timer
+*/
+typedef struct Timer {
+    uint16        unused0;
+    byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+    byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+    uint32        TimerCtl0;
+    uint32        TimerCtl1;
+    uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000
+    uint32        TimerCnt0;
+    uint32        TimerCnt1;
+    uint32        TimerCnt2;
+    uint32        WatchDogDefCount;
+
+    /* Write 0xff00 0x00ff to Start timer
+     * Write 0xee00 0x00ee to Stop and re-load default count
+     * Read from this register returns current watch dog count
+     */
+    uint32        WatchDogCtl;
+
+    /* Number of 50-MHz ticks for WD Reset pulse to last */
+    uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
+
+/*
+** UART
+*/
+typedef struct UartChannel {
+    byte          unused0;
+    byte          control;
+#define BRGEN           0x80    /* Control register bit defs */
+#define TXEN            0x40
+#define RXEN            0x20
+#define LOOPBK          0x10
+#define TXPARITYEN      0x08
+#define TXPARITYEVEN    0x04
+#define RXPARITYEN      0x02
+#define RXPARITYEVEN    0x01
+
+    byte          config;
+#define XMITBREAK       0x40
+#define BITS5SYM        0x00
+#define BITS6SYM        0x10
+#define BITS7SYM        0x20
+#define BITS8SYM        0x30
+#define ONESTOP         0x07
+#define TWOSTOP         0x0f
+    /* 4-LSBS represent STOP bits/char
+     * in 1/8 bit-time intervals.  Zero
+     * represents 1/8 stop bit interval.
+     * Fifteen represents 2 stop bits.
+     */
+    byte          fifoctl;
+#define RSTTXFIFOS      0x80
+#define RSTRXFIFOS      0x40
+    /* 5-bit TimeoutCnt is in low bits of this register.
+     *  This count represents the number of characters
+     *  idle times before setting receive Irq when below threshold
+     */
+    uint32        baudword;
+    /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
+     */
+
+    byte          txf_levl;       /* Read-only fifo depth */
+    byte          rxf_levl;       /* Read-only fifo depth */
+    byte          fifocfg;        /* Upper 4-bits are TxThresh, Lower are
+                                   *      RxThreshold.  Irq can be asserted
+                                   *      when rx fifo> thresh, txfifo<thresh
+                                   */
+    byte          prog_out;       /* Set value of DTR (Bit0), RTS (Bit1)
+                                   *  if these bits are also enabled to GPIO_o
+                                   */
+#define DTREN   0x01
+#define RTSEN   0x02
+
+    byte          unused1;
+    byte          DeltaIPEdgeNoSense;     /* Low 4-bits, set corr bit to 1 to
+                                           * detect irq on rising AND falling
+                                           * edges for corresponding GPIO_i
+                                           * if enabled (edge insensitive)
+                                           */
+    byte          DeltaIPConfig_Mask;     /* Upper 4 bits: 1 for posedge sense
+                                           *      0 for negedge sense if
+                                           *      not configured for edge
+                                           *      insensitive (see above)
+                                           * Lower 4 bits: Mask to enable change
+                                           *  detection IRQ for corresponding
+                                           *  GPIO_i
+                                           */
+    byte          DeltaIP_SyncIP;         /* Upper 4 bits show which bits
+                                           *  have changed (may set IRQ).
+                                           *  read automatically clears bit
+                                           * Lower 4 bits are actual status
+                                           */
+
+    uint16        intMask;                /* Same Bit defs for Mask and status */
+    uint16        intStatus;
+#define DELTAIP         0x0001
+#define TXUNDERR        0x0002
+#define TXOVFERR        0x0004
+#define TXFIFOTHOLD     0x0008
+#define TXREADLATCH     0x0010
+#define TXFIFOEMT       0x0020
+#define RXUNDERR        0x0040
+#define RXOVFERR        0x0080
+#define RXTIMEOUT       0x0100
+#define RXFIFOFULL      0x0200
+#define RXFIFOTHOLD     0x0400
+#define RXFIFONE        0x0800
+#define RXFRAMERR       0x1000
+#define RXPARERR        0x2000
+#define RXBRK           0x4000
+
+    uint16        unused2;
+    uint16        Data;                   /* Write to TX, Read from RX */
+                                          /* bits 11:8 are BRK,PAR,FRM errors */
+
+    uint32        unused3;
+    uint32        unused4;
+} Uart;
+
+#define UART ((volatile Uart * const) UART_BASE)
+
+/*
+** Gpio Controller
+*/
+
+typedef struct GpioControl {
+    uint64      GPIODir;                    /* 0 */
+    uint64      GPIOio;                     /* 8 */
+#define GPIO_MoCA_OVERLAY_UART_WRITE  39
+#define GPIO_MoCA_OVERLAY_UART_READ   38
+    uint32      LEDCtrl;
+#define LED_ALL_STROBE          0x0f000000
+#define LED3_STROBE             0x08000000
+#define LED2_STROBE             0x04000000
+#define LED1_STROBE             0x02000000
+#define LED0_STROBE             0x01000000
+#define LED_TEST                0x00010000
+#define DISABLE_LINK_ACT_ALL    0x0000f000
+#define DISABLE_LINK_ACT_3      0x00008000
+#define DISABLE_LINK_ACT_2      0x00004000
+#define DISABLE_LINK_ACT_1      0x00002000
+#define DISABLE_LINK_ACT_0      0x00001000
+#define LED_INTERVAL_SET_MASK   0x00000f00
+#define LED_INTERVAL_SET_1280MS 0x00000700
+#define LED_INTERVAL_SET_640MS  0x00000600
+#define LED_INTERVAL_SET_320MS  0x00000500
+#define LED_INTERVAL_SET_160MS  0x00000400
+#define LED_INTERVAL_SET_80MS   0x00000300
+#define LED_INTERVAL_SET_40MS   0x00000200
+#define LED_INTERVAL_SET_20MS   0x00000100
+#define LED_ON_ALL              0x000000f0
+#define LED_ON_3                0x00000080
+#define LED_ON_2                0x00000040
+#define LED_ON_1                0x00000020
+#define LED_ON_0                0x00000010
+#define LED_ENABLE_ALL          0x0000000f
+#define LED_ENABLE_3            0x00000008
+#define LED_ENABLE_2            0x00000004
+#define LED_ENABLE_1            0x00000002
+#define LED_ENABLE_0            0x00000001
+    uint32      SpiSlaveCfg;                /* 14 */
+    uint32      GPIOMode;                   /* 18 */
+#define GPIO_MODE_SPI_SSN5          (1<<31)
+#define GPIO_MODE_SPI_SSN4          (1<<30)
+#define GPIO_MODE_SPI_SSN3          (1<<29)
+#define GPIO_MODE_SPI_SSN2          (1<<28)
+#define GPIO_MODE_EBI_CS3           (1<<27)
+#define GPIO_MODE_EBI_CS2           (1<<26)
+#define GPIO_MODE_APM_CLK           (1<<25)
+#define GPIO_MODE_APM_SDIN          (1<<24)
+#define GPIO_MODE_APM_SDOUT         (1<<23)
+#define GPIO_MODE_APM_FRAME_SYNC    (1<<22)
+#define GPIO_MODE_PCI_GNT0          (1<<20)
+#define GPIO_MODE_PCI_REQ0          (1<<19)
+#define GPIO_MODE_PCI_INTB          (1<<18)
+#define GPIO_MODE_PCI_GNT1          (1<<17)
+#define GPIO_MODE_PCI_REQ1          (1<<16)
+#define GPIO_MODE_NTR_PULSE         (1<<15)
+#define GPIO_MODE_USBD_LED          (1<<14)
+#define GPIO_MODE_ROBOSW_LED1       (1<<13)
+#define GPIO_MODE_ROBOSW_LED0       (1<<12)
+#define GPIO_MODE_ROBOSW_LED_CLK    (1<<11)
+#define GPIO_MODE_ROBOSW_LED_DATA   (1<<10)
+#define GPIO_MODE_GPON_LED          (1<<8)
+#define GPIO_MODE_GPHY1_LED         (1<<7)
+#define GPIO_MODE_GPHY0_LED         (1<<6)
+#define GPIO_MODE_MOCA_LED          (1<<5)
+#define GPIO_MODE_SERIAL_LED_CLK    (1<<4)
+#define GPIO_MODE_SERIAL_LED_DATA   (1<<3)
+#define GPIO_MODE_SYS_IRQ           (1<<2)
+#define GPIO_MODE_GPON_TX_APC_FAIL  (1<<1) /*Anticipating B0*/
+#define GPIO_MODE_GPON_TX_EN_L      (1<<0)
+
+    uint32      VregConfig;                 /* 1C */
+#define VREG_VSEL1P2_SHIFT      8
+#define VREG_VSEL1P2_MASK       (0x0f<<8)
+#define VREG_VSEL1P2_MIDDLE     9
+
+    uint32      AuxLedInterval;             /* 20 */
+#define AUX_LED_IN_7            0x80000000
+#define AUX_LED_IN_6            0x40000000
+#define AUX_LED_IN_5            0x20000000
+#define AUX_LED_IN_4            0x10000000
+#define AUX_LED_IN_MASK         0xf0000000
+#define LED_IN_3                0x08000000
+#define LED_IN_2                0x04000000
+#define LED_IN_1                0x02000000
+#define LED_IN_0                0x01000000
+#define AUX_LED_TEST            0x00400000
+#define USE_NEW_INTV            0x00200000
+#define LED7_LNK_ORAND          0x00100000
+#define LED7_LNK_MASK           0x000f0000
+#define LED7_LNK_MASK_SHFT      16
+#define LED7_ACT_MASK           0x0000f000
+#define LED7_ACT_MASK_SHFT      12
+#define AUX_FLASH_INTV          0x00000fc0
+#define AUX_FLASH_INTV_100MS    0x00000140
+#define AUX_FLASH_INTV_SHFT     6
+#define AUX_BLINK_INTV          0x0000003f
+#define AUX_BLINK_INTV_60MS     0x00000003
+    uint32      AuxLedCtrl;                 /* 24 */
+#define AUX_HW_DISAB_7          0x80000000
+#define AUX_STROBE_7            0x40000000
+#define AUX_MODE_7              0x30000000
+#define AUX_MODE_SHFT_7         28
+#define AUX_HW_DISAB_6          0x08000000
+#define AUX_STROBE_6            0x04000000
+#define AUX_MODE_6              0x03000000
+#define AUX_MODE_SHFT_6         24
+#define AUX_HW_DISAB_5          0x00800000
+#define AUX_STROBE_5            0x00400000
+#define AUX_MODE_5              0x00300000
+#define AUX_MODE_SHFT_5         20
+#define AUX_HW_DISAB_4          0x00080000
+#define AUX_STROBE_4            0x00040000
+#define AUX_MODE_4              0x00030000
+#define AUX_MODE_SHFT_4         16
+#define AUX_HW_DISAB_3          0x00008000
+#define AUX_STROBE_3            0x00004000
+#define AUX_MODE_3              0x00003000
+#define AUX_MODE_SHFT_3         12
+#define AUX_HW_DISAB_2          0x00000800
+#define AUX_STROBE_2            0x00000400
+#define AUX_MODE_2              0x00000300
+#define AUX_MODE_SHFT_2         8
+#define AUX_HW_DISAB_1          0x00000080
+#define AUX_STROBE_1            0x00000040
+#define AUX_MODE_1              0x00000030
+#define AUX_MODE_SHFT_1         4
+#define AUX_HW_DISAB_0          0x00000008
+#define AUX_STROBE_0            0x00000004
+#define AUX_MODE_0              0x00000003
+#define AUX_MODE_SHFT_0         0
+
+#define LED_STEADY_OFF          0x0
+#define LED_FLASH               0x1
+#define LED_BLINK               0x2
+#define LED_STEADY_ON           0x3
+
+    uint32      TestControl;                /* 28 */
+
+    uint32      OscControl;                 /* 2C */
+    uint32      RoboSWLEDControl;           /* 30 */
+    uint32      RoboSWLEDLSR;               /* 34 */
+    uint32      GPIOBaseMode;               /* 38 */
+#define EN_GMII2                (1<<17)
+#define EN_GMII1                (1<<16)
+    uint32      RoboswEphyCtrl;             /* 3C */
+#define RSW_HW_FWDG_EN          (1<<19)
+#define RSW_MII_DUMB_FWDG_EN    (1<<16)
+#define EPHY_RST_4              (1<<9)
+#define EPHY_RST_3              (1<<8)
+#define EPHY_RST_2              (1<<7)
+#define EPHY_RST_1              (1<<6)
+#define EPHY_PWR_DOWN_4         (1<<5)
+#define EPHY_PWR_DOWN_3         (1<<4)
+#define EPHY_PWR_DOWN_2         (1<<3)
+#define EPHY_PWR_DOWN_1         (1<<2)
+    uint32      unused1[2];                 /* 40 */
+
+    uint32      RingOscCtrl0;               /* 48 */
+#define RING_OSC_256_CYCLES        8
+#define RING_OSC_512_CYCLES        9
+#define RING_OSC_1024_CYCLES       10
+
+    uint32      RingOscCtrl1;               /* 4C */
+#define RING_OSC_ENABLE_MASK       (0x57<<24)
+#define RING_OSC_ENABLE_SHIFT      24
+#define RING_OSC_MAX               7
+#define RING_OSC_COUNT_RESET       (0x1<<23)
+#define RING_OSC_SELECT_MASK       (0x7<<20)
+#define RING_OSC_SELECT_SHIFT      20
+#define RING_OSC_IRQ               (0x1<<18)
+#define RING_OSC_COUNTER_OVERFLOW  (0x1<<17)
+#define RING_OSC_COUNTER_BUSY      (0x1<<16)
+#define RING_OSC_COUNT_MASK        0x0000ffff
+
+    uint32      SerialLed;                  /* 50 */
+    uint32      SerialLedCtrl;              /* 54 */
+#define SER_LED_BUSY            (1<<3)
+#define SER_LED_POLARITY        (1<<2)
+#define SER_LED_DIV_1           0
+#define SER_LED_DIV_2           1
+#define SER_LED_DIV_4           2
+#define SER_LED_DIV_8           3
+#define SER_LED_DIV_MASK        0x3
+#define SER_LED_DIV_SHIFT       0
+    uint32    SerialLedBlink;               /* 58 */
+    uint32    SerdesCtl;                    /* 5c */
+#define SERDES_PCIE_ENABLE  0x00000001
+#define SERDES_PCIE_EXD_ENABLE  (1<<15)
+    uint32    SerdesStatus;                 /* 60 */
+    uint32    unused2;                      /* 64 */
+    uint32    DieRevID;                     /* 68 */
+    uint32    DiagMemStatus;                /* 6c */
+    uint32    DiagSelControl;               /* 70 */
+    uint32    DiagReadBack;                 /* 74 */
+    uint32    DiagReadBackHi;               /* 78 */
+    uint32    DiagMiscControl;              /* 7c */
+#define EPHY_SA_RESET_N           0x00000300
+#define EPHY_SA_TESTEN            0x00000500
+#define EPHY_SA_CLOCK_RESET       0x0000d900
+} GpioControl;
+
+#define GPIO ((volatile GpioControl * const) GPIO_BASE)
+
+/* Number to mask conversion macro used for GPIODir and GPIOio */
+#define GPIO_NUM_MAX                    40
+#define GPIO_NUM_TO_MASK(X)             ( (((X) & BP_GPIO_NUM_MASK) < GPIO_NUM_MAX) ? ((uint64)1 << ((X) & BP_GPIO_NUM_MASK)) : (0) )
+
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiMsgCtl;              /* (0x0) control byte */
+#define FULL_DUPLEX_RW                  0
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              14
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[0x21e];      /* (0x02 - 0x21f) msg data */
+  byte          unused0[0x1e0];
+  byte          spiRxDataFifo[0x220];   /* (0x400 - 0x61f) rx data */
+  byte          unused1[0xe0];
+
+  uint16        spiCmd;                 /* (0x700): SPI command */
+#define SPI_CMD_NOOP                    0
+#define SPI_CMD_SOFT_RESET              1
+#define SPI_CMD_HARD_RESET              2
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_COMMAND_MASK            0x000f
+
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+#define SPI_CMD_ONE_BYTE_SHIFT          11
+#define SPI_CMD_ONE_WIRE_SHIFT          12
+#define SPI_DEV_ID_0                    0
+#define SPI_DEV_ID_1                    1
+#define SPI_DEV_ID_2                    2
+#define SPI_DEV_ID_3                    3
+
+  byte          spiIntStatus;           /* (0x702): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x703): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x704): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_RX_OVERFLOW            0x02
+#define SPI_INTR_INTR_TX_UNDERFLOW      0x04
+#define SPI_INTR_TX_OVERFLOW            0x08
+#define SPI_INTR_RX_UNDERFLOW           0x10
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x705): SPI status */
+#define SPI_RX_EMPTY                    0x02
+#define SPI_CMD_BUSY                    0x04
+#define SPI_SERIAL_BUSY                 0x08
+
+  byte          spiClkCfg;              /* (0x706): SPI clock configuration */
+#define SPI_CLK_0_391MHZ                1
+#define SPI_CLK_0_781MHZ                2 /* default */
+#define SPI_CLK_1_563MHZ                3
+#define SPI_CLK_3_125MHZ                4
+#define SPI_CLK_6_250MHZ                5
+#define SPI_CLK_12_50MHZ                6
+#define SPI_CLK_MASK                    0x07
+#define SPI_SSOFFTIME_MASK              0x38
+#define SPI_SSOFFTIME_SHIFT             3
+#define SPI_BYTE_SWAP                   0x80
+
+  byte          spiFillByte;            /* (0x707): SPI fill byte */
+  byte          unused2;
+  byte          spiMsgTail;             /* (0x709): msgtail */
+  byte          unused3;
+  byte          spiRxTail;              /* (0x70B): rxtail */
+} SpiControl;
+
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
+
+/*
+** High-Speed SPI Controller
+*/
+
+#define	__mask(end, start)		(((1 << ((end - start) + 1)) - 1) << start)
+typedef struct HsSpiControl {
+
+  uint32	hs_spiGlobalCtrl;	// 0x0000
+#define	HS_SPI_MOSI_IDLE		(1 << 18)
+#define	HS_SPI_CLK_STATE_GATED		(1 << 17)
+#define	HS_SPI_CLK_GATE_SSOFF		(1 << 16)
+#define	HS_SPI_PLL_CLK_CTRL		(8)
+#define	HS_SPI_PLL_CLK_CTRL_MASK	__mask(15, HS_SPI_PLL_CLK_CTRL)
+#define	HS_SPI_SS_POLARITY		(0)
+#define	HS_SPI_SS_POLARITY_MASK		__mask(7, HS_SPI_SS_POLARITY)
+
+  uint32	hs_spiExtTrigCtrl;	// 0x0004
+#define	HS_SPI_TRIG_RAW_STATE		(24)
+#define	HS_SPI_TRIG_RAW_STATE_MASK	__mask(31, HS_SPI_TRIG_RAW_STATE)
+#define	HS_SPI_TRIG_LATCHED		(16)
+#define	HS_SPI_TRIG_LATCHED_MASK	__mask(23, HS_SPI_TRIG_LATCHED)
+#define	HS_SPI_TRIG_SENSE		(8)
+#define	HS_SPI_TRIG_SENSE_MASK		__mask(15, HS_SPI_TRIG_SENSE)
+#define	HS_SPI_TRIG_TYPE		(0)
+#define	HS_SPI_TRIG_TYPE_MASK		__mask(7, HS_SPI_TRIG_TYPE)
+#define	HS_SPI_TRIG_TYPE_EDGE		(0)
+#define	HS_SPI_TRIG_TYPE_LEVEL		(1)
+
+  uint32	hs_spiIntStatus;	// 0x0008
+#define	HS_SPI_IRQ_PING1_USER		(28)
+#define	HS_SPI_IRQ_PING1_USER_MASK	__mask(31, HS_SPI_IRQ_PING1_USER)
+#define	HS_SPI_IRQ_PING0_USER		(24)
+#define	HS_SPI_IRQ_PING0_USER_MASK	__mask(27, HS_SPI_IRQ_PING0_USER)
+
+#define	HS_SPI_IRQ_PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQ_PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQ_PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQ_PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQ_PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQ_PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQ_PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQ_PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQ_PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQ_PING0_CMD_DONE	(1 << 0)
+
+  uint32	hs_spiIntStatusMasked;	// 0x000C
+#define	HS_SPI_IRQSM__PING1_USER	(28)
+#define	HS_SPI_IRQSM__PING1_USER_MASK	__mask(31, HS_SPI_IRQSM__PING1_USER)
+#define	HS_SPI_IRQSM__PING0_USER	(24)
+#define	HS_SPI_IRQSM__PING0_USER_MASK	__mask(27, HS_SPI_IRQSM__PING0_USER)
+
+#define	HS_SPI_IRQSM__PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQSM__PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQSM__PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQSM__PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQSM__PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQSM__PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQSM__PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQSM__PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQSM__PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQSM__PING0_CMD_DONE	(1 << 0)
+
+  uint32	hs_spiIntMask;		// 0x0010
+#define	HS_SPI_IRQM_PING1_USER		(28)
+#define	HS_SPI_IRQM_PING1_USER_MASK	__mask(31, HS_SPI_IRQM_PING1_USER)
+#define	HS_SPI_IRQM_PING0_USER		(24)
+#define	HS_SPI_IRQM_PING0_USER_MASK	__mask(27, HS_SPI_IRQM_PING0_USER)
+
+#define	HS_SPI_IRQM_PING1_CTRL_INV	(1 << 12)
+#define	HS_SPI_IRQM_PING1_POLL_TOUT	(1 << 11)
+#define	HS_SPI_IRQM_PING1_TX_UNDER	(1 << 10)
+#define	HS_SPI_IRQM_PING1_RX_OVER	(1 << 9)
+#define	HS_SPI_IRQM_PING1_CMD_DONE	(1 << 8)
+
+#define	HS_SPI_IRQM_PING0_CTRL_INV	(1 << 4)
+#define	HS_SPI_IRQM_PING0_POLL_TOUT	(1 << 3)
+#define	HS_SPI_IRQM_PING0_TX_UNDER	(1 << 2)
+#define	HS_SPI_IRQM_PING0_RX_OVER	(1 << 1)
+#define	HS_SPI_IRQM_PING0_CMD_DONE	(1 << 0)
+
+#define HS_SPI_INTR_CLEAR_ALL       (0xFF001F1F)
+
+  uint32	hs_spiFlashCtrl;	// 0x0014
+#define	HS_SPI_FCTRL_MB_ENABLE		(1 << 23)
+#define	HS_SPI_FCTRL_SS_NUM		(20)
+#define	HS_SPI_FCTRL_SS_NUM_MASK	__mask(22, HS_SPI_FCTRL_SS_NUM)
+#define	HS_SPI_FCTRL_PROFILE_NUM	(16)
+#define	HS_SPI_FCTRL_PROFILE_NUM_MASK	__mask(18, HS_SPI_FCTRL_PROFILE_NUM)
+#define	HS_SPI_FCTRL_DUMMY_BYTES	(10)
+#define	HS_SPI_FCTRL_DUMMY_BYTES_MASK	__mask(11, HS_SPI_FCTRL_DUMMY_BYTES)
+#define	HS_SPI_FCTRL_ADDR_BYTES		(8)
+#define	HS_SPI_FCTRL_ADDR_BYTES_MASK	__mask(9, HS_SPI_FCTRL_ADDR_BYTES)
+#define	HS_SPI_FCTRL_ADDR_BYTES_2	(0)
+#define	HS_SPI_FCTRL_ADDR_BYTES_3	(1)
+#define	HS_SPI_FCTRL_ADDR_BYTES_4	(2)
+#define	HS_SPI_FCTRL_READ_OPCODE	(0)
+#define	HS_SPI_FCTRL_READ_OPCODE_MASK	__mask(7, HS_SPI_FCTRL_READ_OPCODE)
+
+  uint32	hs_spiFlashAddrBase;	// 0x0018
+
+  char		fill0[0x80 - 0x18];
+
+  uint32	hs_spiPP_0_Cmd;		// 0x0080
+#define	HS_SPI_PP_SS_NUM		(12)
+#define	HS_SPI_PP_SS_NUM_MASK		__mask(14, HS_SPI_PP_SS_NUM)
+#define	HS_SPI_PP_PROFILE_NUM		(8)
+#define	HS_SPI_PP_PROFILE_NUM_MASK	__mask(10, HS_SPI_PP_PROFILE_NUM)
+
+} HsSpiControl;
+
+typedef struct HsSpiPingPong {
+
+	uint32 command;
+#define HS_SPI_SS_NUM (12)
+#define HS_SPI_PROFILE_NUM (8)
+#define HS_SPI_TRIGGER_NUM (4)
+#define HS_SPI_COMMAND_VALUE (0)
+    #define HS_SPI_COMMAND_NOOP (0)
+    #define HS_SPI_COMMAND_START_NOW (1)
+    #define HS_SPI_COMMAND_START_TRIGGER (2)
+    #define HS_SPI_COMMAND_HALT (3)
+    #define HS_SPI_COMMAND_FLUSH (4)
+
+	uint32 status;
+#define HS_SPI_ERROR_BYTE_OFFSET (16)
+#define HS_SPI_WAIT_FOR_TRIGGER (2)
+#define HS_SPI_SOURCE_BUSY (1)
+#define HS_SPI_SOURCE_GNT (0)
+
+	uint32 fifo_status;
+	uint32 control;
+
+} HsSpiPingPong;
+
+typedef struct HsSpiProfile {
+
+	uint32 clk_ctrl;
+#define HS_SPI_ACCUM_RST_ON_LOOP (15)
+#define HS_SPI_SPI_CLK_2X_SEL (14)
+#define HS_SPI_FREQ_CTRL_WORD (0)
+	
+	uint32 signal_ctrl;
+#define	HS_SPI_LAUNCH_RISING   (1 << 13)
+#define	HS_SPI_LATCH_RISING    (1 << 12)
+
+	uint32 mode_ctrl;
+#define HS_SPI_PREPENDBYTE_CNT (24)
+#define HS_SPI_MODE_ONE_WIRE (20)
+#define HS_SPI_MULTIDATA_WR_SIZE (18)
+#define HS_SPI_MULTIDATA_RD_SIZE (16)
+#define HS_SPI_MULTIDATA_WR_STRT (12)
+#define HS_SPI_MULTIDATA_RD_STRT (8)
+#define HS_SPI_FILLBYTE (0)
+
+	uint32 polling_config;
+	uint32 polling_and_mask;
+	uint32 polling_compare;
+	uint32 polling_timeout;
+	uint32 reserved;
+
+} HsSpiProfile;
+
+#define HS_SPI_OP_CODE 13
+    #define HS_SPI_OP_SLEEP (0)
+    #define HS_SPI_OP_READ_WRITE (1)
+    #define HS_SPI_OP_WRITE (2)
+    #define HS_SPI_OP_READ (3)
+    #define HS_SPI_OP_SETIRQ (4)
+
+#define	HS_SPI ((volatile HsSpiControl * const) HSSPIM_BASE)
+#define	HS_SPI_PINGPONG0 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0x80))
+#define	HS_SPI_PINGPONG1 ((volatile HsSpiPingPong * const) (HSSPIM_BASE+0xc0))
+#define	HS_SPI_PROFILES ((volatile HsSpiProfile * const) (HSSPIM_BASE+0x100))
+#define	HS_SPI_FIFO0 ((volatile uint8 * const) (HSSPIM_BASE+0x200))
+#define	HS_SPI_FIFO1 ((volatile uint8 * const) (HSSPIM_BASE+0x400))
+
+
+/*
+** Periph - Misc Register Set Definitions.
+*/
+
+typedef struct Misc {
+  uint32        miscMoCADiv ;              /* (0x0) MoCA Ref PLL Div */
+#define MISC_MOCA_DIV_REF_DIV_FB_MASK                              0xFF000000
+#define MISC_MOCA_DIV_REF_DIV_FB_SHIFT                             24
+#define MISC_MOCA_DIV_REF_OUTDIV_M1_MASK                           0x00FF0000
+#define MISC_MOCA_DIV_REF_OUTDIV_M1_SHIFT                          16
+#define MISC_MOCA_DIV_REF_OUTDIV_M4_MASK                           0x0000FF00
+#define MISC_MOCA_DIV_REF_OUTDIV_M4_SHIFT                          8
+#define MISC_MOCA_DIV_REF_OUTDIV_M5_MASK                           0x000000FF
+#define MISC_MOCA_DIV_REF_OUTDIV_M5_SHIFT                          0
+  uint32        miscMoCACtl ;              /* (0x4) MoCA Ref PLL Ctl */
+#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_MASK                       0x001FC000
+#define MISC_MOCA_CTL_REF_OUTCML_LOWCUR_SHIFT                      14
+#define MISC_MOCA_CTL_REF_CLFCNT_MASK                              0x00003000
+#define MISC_MOCA_CTL_REF_CLFCNT_SHIFT                             12
+#define MISC_MOCA_CTL_REF_QP_ICTRL_MASK                            0x00000E00
+#define MISC_MOCA_CTL_REF_QP_ICTRL_SHIFT                           9
+#define MISC_MOCA_CTL_REF_VCOBUF_LATCH_ON                          0x00000100
+#define MISC_MOCA_CTL_REF_LF_RCNTL_MASK                            0x000000E0
+#define MISC_MOCA_CTL_REF_LF_RCNTL_SHIFT                           5
+#define MISC_MOCA_CTL_REF_MUX_FBOFF                                0x00000010
+#define MISC_MOCA_CTL_REF_MUX_SEL_MASK                             0x0000000C
+#define MISC_MOCA_CTL_REF_MUX_SEL_SHIFT                            2
+#define MISC_MOCA_CTL_REF_REF_CMLBIAS_MASK                         0x00000003
+#define MISC_MOCA_CTL_REF_REF_CMLBIAS_SHIFT                        0
+  uint32        miscMoCAPwr ;              /* (0x8) MoCA Ref PLL Pwr */
+#define MISC_MOCA_PWR_REF_DEEP_PWRDN                               0x01000000
+#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_MASK                      0x00FE0000
+#define MISC_MOCA_PWR_REF_OUTDIV_PWRDN_M_SHIFT                     17
+#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_MASK                      0x0001FC00
+#define MISC_MOCA_PWR_REF_OUTCML_PWRDN_M_SHIFT                     10
+#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_MASK                     0x000003F8
+#define MISC_MOCA_PWR_REF_OUTCMOS_PWRDN_M_SHIFT                    3
+#define MISC_MOCA_PWR_REF_UGB_PWRDN                                0x00000004
+#define MISC_MOCA_PWR_REF_MUX_PWRDN                                0x00000002
+#define MISC_MOCA_PWR_REF_VCO_PWRDN                                0x00000001
+  uint32        miscMoCARst ;              /* (0xC) MoCA Ref PLL Rst */
+#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_MASK                      0x00000FE0
+#define MISC_MOCA_RST_REF_OUTDIV_RESET_M_SHIFT                     5
+#define MISC_MOCA_RST_REF_DIV2RST                                  0x00000010
+#define MISC_MOCA_RST_REF_MDIV2RST                                 0x00000008
+#define MISC_MOCA_RST_REF_FBDIVRST                                 0x00000004
+#define MISC_MOCA_RST_REF_LD_RESET_STRT                            0x00000002
+#define MISC_MOCA_RST_REF_VCRST                                    0x00000001
+  uint32        miscMemcControl ;          /* (0x10) MEMC Control     */
+#define MISC_MEMC_CONTROL_MC_UBUS_ASYNC_MODE                       0x00000008
+#define MISC_MEMC_CONTROL_MC_LMB_ASYNC_MODE                        0x00000004
+#define MISC_MEMC_CONTROL_DDR_TEST_DONE                            0x00000002
+#define MISC_MEMC_CONTROL_DDR_TEST_DISABLE                         0x00000001
+  uint32        miscStrapBus ;             /* (0x14) Strap Register   */
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_MASK                          0xF8000000
+#define MISC_STRAP_BUS_MIPS_PLL_FVCO_SHIFT                         27
+#define MISC_STRAP_BUS_HRD_RST_DELAY                               0x04000000
+#define MISC_STRAP_BUS_ALT_BFC_EN                                  0x02000000
+#define MISC_STRAP_BUS_MOCA_STANDALONE_B                           0x01000000
+#define MISC_STRAP_BUS_MOCA_CONFIG_RATIO                           0x00800000
+#define MISC_STRAP_BUS_IXTAL_ADJ_MASK                              0x00600000
+#define MISC_STRAP_BUS_IXTAL_ADJ_SHIFT                             21
+#define MISC_STRAP_BUS_BYPASS_XTAL                                 0x00100000
+#define MISC_STRAP_BUS_TS                                          0x00080000
+#define MISC_STRAP_BUS_APM_PICO_BOOT_ROM                           0x00040000
+#define MISC_STRAP_BUS_TA                                          0x00020000
+#define MISC_STRAP_BUS_ROBOSW_2_MODE_MASK                          0x00018000
+#define MISC_STRAP_BUS_ROBOSW_2_MODE_SHIFT                         15
+#define MISC_STRAP_BUS_ROBOSW_1_MODE_MASK                          0x00006000
+#define MISC_STRAP_BUS_ROBOSW_1_MODE_SHIFT                         13
+#define MISC_STRAP_BUS_BIST_CLRMEM_N                               0x00001000
+#define MISC_STRAP_BUS_PLL_MIPS_WAIT_FAST_N                        0x00000200
+#define MISC_STRAP_BUS_PLL_USE_LOCK                                0x00000100
+#define MISC_STRAP_BUS_PCIE_ROOT_COMPLEX                           0x00000080
+#define MISC_STRAP_BUS_LS_SPIM_ENABLED                             0x00000040
+#define MISC_STRAP_BUS_USE_SPI_MASTER                              0x00000020
+#define MISC_STRAP_BUS_SPI_CLK_FAST                                0x00000010
+#define MISC_STRAP_BUS_SPI_BOOT_DELAY                              0x00000008
+#define MISC_STRAP_BUS_MIPS_BOOT16                                 0x00000004
+#define MISC_STRAP_BUS_BOOT_SEL_MASK                               0x00000003
+#define MISC_STRAP_BUS_BOOT_SEL_SHIFT                              0
+#define MISC_STRAP_BUS_BOOT_PARALLEL                               0x03
+#define MISC_STRAP_BUS_BOOT_SERIAL                                 0x01
+#define MISC_STRAP_BUS_BOOT_NAND                                   0x02
+  uint32        miscStrapOverride ;        /* (0x18) Strap Override Reg */
+#define MISC_STRAP_OVERRIDE_INT_MPI_ARB                            0x00000008
+#define MISC_STRAP_OVERRIDE_INT_MPI_CLK                            0x00000004
+#define MISC_STRAP_OVERRIDE_INT_HOST                               0x00000002
+#define MISC_STRAP_OVERRIDE_STRAP_OVERRIDE                         0x00000001
+  uint32        miscMoCAClkStrapBus ;      /* (0x1C) MoCA Clock Strap Reg */
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_MASK              0x0000FF00
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_10_OVERRIDE_SHIFT             8
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_MASK               0x000000FF
+#define MISC_MOCA_CLK_STRAP_BUS_MDIV_9_OVERRIDE_SHIFT              0
+  uint32        miscMoCAClkStrapOverride ; /* (0x20) MoCA Clock Strap Overdide Reg */
+#define MISC_MOCA_CLK_STRAP_OVERRIDE_MOCA_CLK_STRAP_OVERRIDE_CTL   0x00000001
+  uint32        miscMoCAGpioOverlayLo ;    /* (0x24) MoCA GPIO Overlay bus lo Reg */
+  uint32        miscMoCAGpioOverlayHi ;    /* (0x28) MoCA GPIO Overlay bus hi Reg */
+#define MISC_MOCA_GPIO_UART                 0x000000C0
+  uint32        miscDdrPllOutEnCh ;        /* (0x2C) DDR PLL Out En Ch Number */
+#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_MASK                0x000001FF
+#define MISC_DDR_PLL_OUTEN_CH_DDR_PLL_OUTEN_CH_SHIFT               0
+#define MISC_DDR_PLL_OUTEN_CH_MOCA_CPU_CLK                 0x00000080
+#define MISC_DDR_PLL_OUTEN_CH_MOCA_PHY_CLK                 0x00000100
+  uint32        miscGpioDiagOverlay ;      /* (0x30) GPIO Diag Overlay Control Reg */
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_EN                     0x00000020
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_MASK                   0x0000001F
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_39_32             0x00000010
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_31_24             0x00000008
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_23_16             0x00000004
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_15_8              0x00000002
+#define MISC_GPIO_DIAG_OVERLAY_DIAG_OVERLAY_PORT_7_0               0x00000001
+  uint32        miscGpioModeCtrlHi ;       /* (0x34) GPIO Pin Mode Control Reg Hi */
+} Misc ;
+
+#define MISC ((volatile Misc * const) MISC_BASE)
+
+typedef struct HvgMiscRegisterChannelA {
+   uint32        mask;
+#define   K_PROP                          0x0000000f
+#define   K_INTEG                         0x000000f0
+#define   SER_TST_OUTPUT_SEL              0x00000700
+#define   CONT_OR_BLOCK                   0x00000800
+#define   HVG_MODE                        0x00003000
+#define   HVG_MODE_OFFHOOK_TRACKING       0x00001000
+#define   HVG_MODE_ONHOOK_FIXED           0x00002000
+#define   HVG_SOFT_INIT_0                 0x00004000
+#define   HVG_RR_SINGLE                   0x00008000
+} HvgMiscRegisterChannelA;
+
+#define HVG_MISC_REG_CHANNEL_A ((volatile HvgMiscRegisterChannelA * const) APM_HVG_BASE_REG_15)
+
+typedef struct HvgMiscRegisterChannelB {
+   uint32        mask;
+} HvgMiscRegisterChannelB;
+
+#define HVG_MISC_REG_CHANNEL_B ((volatile HvgMiscRegisterChannelB * const) APM_HVG_BASE_REG_19)
+
+#define IUDMA_MAX_CHANNELS          32
+
+/*
+** DMA Channel Configuration (1 .. 32)
+*/
+typedef struct DmaChannelCfg {
+  uint32        cfg;                    /* (00) assorted configuration */
+#define         DMA_ENABLE      0x00000001  /* set to enable channel */
+#define         DMA_PKT_HALT    0x00000002  /* idle after an EOP flag is detected */
+#define         DMA_BURST_HALT  0x00000004  /* idle after finish current memory burst */
+  uint32        intStat;                /* (04) interrupts control and status */
+  uint32        intMask;                /* (08) interrupts mask */
+#define         DMA_BUFF_DONE   0x00000001  /* buffer done */
+#define         DMA_DONE        0x00000002  /* packet xfer complete */
+#define         DMA_NO_DESC     0x00000004  /* no valid descriptors */
+  uint32        maxBurst;               /* (0C) max burst length permitted */
+#define         DMA_DESCSIZE_SEL 0x00040000  /* DMA Descriptor Size Selection */
+} DmaChannelCfg;
+
+/*
+** DMA State RAM (1 .. 16)
+*/
+typedef struct DmaStateRam {
+  uint32        baseDescPtr;            /* (00) descriptor ring start address */
+  uint32        state_data;             /* (04) state/bytes done/ring offset */
+  uint32        desc_len_status;        /* (08) buffer descriptor status and len */
+  uint32        desc_base_bufptr;       /* (0C) buffer descrpitor current processing */
+} DmaStateRam;
+
+
+/*
+** DMA Registers
+*/
+typedef struct DmaRegs {
+    uint32 controller_cfg;              /* (00) controller configuration */
+#define DMA_MASTER_EN           0x00000001
+#define DMA_FLOWC_CH1_EN        0x00000002
+#define DMA_FLOWC_CH3_EN        0x00000004
+
+    // Flow control Ch1
+    uint32 flowctl_ch1_thresh_lo;           /* 004 */
+    uint32 flowctl_ch1_thresh_hi;           /* 008 */
+    uint32 flowctl_ch1_alloc;               /* 00c */
+#define DMA_BUF_ALLOC_FORCE     0x80000000
+
+    // Flow control Ch3
+    uint32 flowctl_ch3_thresh_lo;           /* 010 */
+    uint32 flowctl_ch3_thresh_hi;           /* 014 */
+    uint32 flowctl_ch3_alloc;               /* 018 */
+
+    // Flow control Ch5
+    uint32 flowctl_ch5_thresh_lo;           /* 01C */
+    uint32 flowctl_ch5_thresh_hi;           /* 020 */
+    uint32 flowctl_ch5_alloc;               /* 024 */
+
+    // Flow control Ch7
+    uint32 flowctl_ch7_thresh_lo;           /* 028 */
+    uint32 flowctl_ch7_thresh_hi;           /* 02C */
+    uint32 flowctl_ch7_alloc;               /* 030 */
+
+    uint32 ctrl_channel_reset;              /* 034 */
+    uint32 ctrl_channel_debug;              /* 038 */
+    uint32 reserved1;                       /* 03C */
+    uint32 ctrl_global_interrupt_status;    /* 040 */
+    uint32 ctrl_global_interrupt_mask;      /* 044 */
+
+    // Unused words
+    uint8 reserved2[0x200-0x48];
+
+    // Per channel registers/state ram
+    DmaChannelCfg chcfg[IUDMA_MAX_CHANNELS];/* (200-3FF) Channel configuration */
+    union {
+        DmaStateRam     s[IUDMA_MAX_CHANNELS];
+        uint32          u32[4 * IUDMA_MAX_CHANNELS];
+    } stram;                                /* (400-5FF) state ram */
+} DmaRegs;
+
+#define SW_DMA ((volatile DmaRegs * const) SWITCH_DMA_BASE)
+
+/*
+** DMA Buffer
+*/
+typedef struct DmaDesc {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM    0x8000
+#define          DMA_DESC_MULTICAST 0x4000
+#define          DMA_DESC_BUFLENGTH 0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                /* address of data */
+} DmaDesc;
+
+/*
+** 16 Byte DMA Buffer
+*/
+typedef struct {
+  union {
+    struct {
+        uint16        length;                   /* in bytes of data in buffer */
+#define          DMA_DESC_USEFPM        0x8000
+#define          DMA_DESC_MULTICAST     0x4000
+#define          DMA_DESC_BUFLENGTH     0x0fff
+        uint16        status;                   /* buffer status */
+#define          DMA_OWN                0x8000  /* cleared by DMA, set by SW */
+#define          DMA_EOP                0x4000  /* last buffer in packet */
+#define          DMA_SOP                0x2000  /* first buffer in packet */
+#define          DMA_WRAP               0x1000  /* */
+#define          DMA_PRIO               0x0C00  /* Prio for Tx */
+#define          DMA_APPEND_BRCM_TAG    0x0200
+#define          DMA_APPEND_CRC         0x0100
+#define          USB_ZERO_PKT           (1<< 0) // Set to send zero length packet
+    };
+    uint32      word0;
+  };
+
+  uint32        address;                 /* address of data */
+  uint32        control;
+#define         GEM_ID_MASK             0x001F
+  uint32        reserved;
+} DmaDesc16;
+
+/*
+** External Bus Interface
+*/
+typedef struct EbiChipSelect {
+    uint32    base;                         /* base address in upper 24 bits */
+#define EBI_SIZE_8K         0
+#define EBI_SIZE_16K        1
+#define EBI_SIZE_32K        2
+#define EBI_SIZE_64K        3
+#define EBI_SIZE_128K       4
+#define EBI_SIZE_256K       5
+#define EBI_SIZE_512K       6
+#define EBI_SIZE_1M         7
+#define EBI_SIZE_2M         8
+#define EBI_SIZE_4M         9
+#define EBI_SIZE_8M         10
+#define EBI_SIZE_16M        11
+#define EBI_SIZE_32M        12
+#define EBI_SIZE_64M        13
+#define EBI_SIZE_128M       14
+#define EBI_SIZE_256M       15
+    uint32    config;
+#define EBI_ENABLE          0x00000001      /* .. enable this range */
+#define EBI_WAIT_STATES     0x0000000e      /* .. mask for wait states */
+#define EBI_WTST_SHIFT      1               /* .. for shifting wait states */
+#define EBI_WORD_WIDE       0x00000010      /* .. 16-bit peripheral, else 8 */
+#define EBI_WREN            0x00000020      /* enable posted writes */
+#define EBI_POLARITY        0x00000040      /* .. set to invert something,
+                                        **    don't know what yet */
+#define EBI_TS_TA_MODE      0x00000080      /* .. use TS/TA mode */
+#define EBI_TS_SEL          0x00000100      /* .. drive tsize, not bs_b */
+#define EBI_FIFO            0x00000200      /* .. use fifo */
+#define EBI_RE              0x00000400      /* .. Reverse Endian */
+#define EBI_SETUP_SHIFT     16
+#define EBI_HOLD_SHIFT      20
+#define EBI_SETUP_STATES    0x0f0000
+#define EBI_HOLD_STATES     0xf00000
+} EbiChipSelect;
+
+typedef struct MpiRegisters {
+  EbiChipSelect cs[7];                  /* size chip select configuration */
+#define EBI_CS0_BASE            0
+#define EBI_CS1_BASE            1
+#define EBI_CS2_BASE            2
+#define EBI_CS3_BASE            3
+#define EBI_CS4_BASE            4
+#define EBI_CS5_BASE            5
+#define EBI_CS6_BASE            6
+  uint32        unused0[2];             /* reserved */
+  uint32        ebi_control;            /* ebi control */
+#define EBI_ACCESS_TIMEOUT      0x000007FF
+  uint32        unused1[7];             /* reserved */
+
+  uint32        sp0range;               /* PCI to internal system bus address space */
+#define ADDR_SPACE_MASK         0xFFFF0000
+  uint32        sp0remap;
+  uint32        sp0cfg;
+  uint32        sp1range;
+  uint32        sp1remap;
+  uint32        sp1cfg;
+
+  uint32        EndianCfg;
+
+  uint32        l2pcfgctl;              /* internal system bus to PCI IO/Cfg control */
+#define DIR_CFG_SEL             0x80000000 /* change from PCI I/O access to PCI config access */
+#define DIR_CFG_USEREG          0x40000000 /* use this register info for PCI configuration access */
+#define DEVICE_NUMBER           0x00007C00 /* device number for the PCI configuration access */
+#define FUNC_NUMBER             0x00000300 /* function number for the PCI configuration access */
+#define REG_NUMBER              0x000000FC /* register number for the PCI configuration access */
+#define CONFIG_TYPE             0x00000003 /* configuration type for the PCI configuration access */
+
+  uint32        l2pmrange1;             /* internal system bus to PCI memory space */
+#define PCI_SIZE_64K            0xFFFF0000
+#define PCI_SIZE_128K           0xFFFE0000
+#define PCI_SIZE_256K           0xFFFC0000
+#define PCI_SIZE_512K           0xFFF80000
+#define PCI_SIZE_1M             0xFFF00000
+#define PCI_SIZE_2M             0xFFE00000
+#define PCI_SIZE_4M             0xFFC00000
+#define PCI_SIZE_8M             0xFF800000
+#define PCI_SIZE_16M            0xFF000000
+#define PCI_SIZE_32M            0xFE000000
+  uint32        l2pmbase1;              /* kseg0 or kseg1 address & 0x1FFFFFFF */
+  uint32        l2pmremap1;
+#define CARDBUS_MEM             0x00000004
+#define MEM_WINDOW_EN           0x00000001
+  uint32        l2pmrange2;
+  uint32        l2pmbase2;
+  uint32        l2pmremap2;
+  uint32        l2piorange;             /* internal system bus to PCI I/O space */
+  uint32        l2piobase;
+  uint32        l2pioremap;
+
+  uint32        pcimodesel;
+#define PCI_INT_BUS_RD_PREFETCH 0x000001F0
+#define PCI_BAR2_NOSWAP         0x00000002 /* BAR at offset 0x20 */
+#define PCI_BAR1_NOSWAP         0x00000001 /* BAR at affset 0x1c */
+
+  uint32        pciintstat;             /* PCI interrupt mask/status */
+#define MAILBOX1_SENT           0x08
+#define MAILBOX0_SENT           0x04
+#define MAILBOX1_MSG_RCV        0x02
+#define MAILBOX0_MSG_RCV        0x01
+  uint32        locbuscntrl;            /* internal system bus control */
+#define DIR_U2P_NOSWAP          0x00000002
+#define EN_PCI_GPIO             0x00000001
+  uint32        locintstat;             /* internal system bus interrupt mask/status */
+#define CSERR                   0x0200
+#define SERR                    0x0100
+#define EXT_PCI_INT             0x0080
+#define DIR_FAILED              0x0040
+#define DIR_COMPLETE            0x0020
+#define PCI_CFG                 0x0010
+  uint32        unused4[7];
+
+  uint32        mailbox0;
+  uint32        mailbox1;
+
+  uint32        pcicfgcntrl;            /* internal system bus PCI configuration control */
+#define PCI_CFG_REG_WRITE_EN    0x00000080
+#define PCI_CFG_ADDR            0x0000003C
+  uint32        pcicfgdata;             /* internal system bus PCI configuration data */
+
+  uint32        locch2ctl;              /* PCI to interrnal system bus DMA (downstream) local control */
+#define MPI_DMA_HALT            0x00000008  /* idle after finish current memory burst */
+#define MPI_DMA_PKT_HALT        0x00000004  /* idle after an EOP flag is detected */
+#define MPI_DMA_STALL           0x00000002  /* idle after an EOP flag is detected */
+#define MPI_DMA_ENABLE          0x00000001  /* set to enable channel */
+  uint32        locch2intStat;
+#define MPI_DMA_NO_DESC         0x00000004  /* no valid descriptors */
+#define MPI_DMA_DONE            0x00000002  /* packet xfer complete */
+#define MPI_DMA_BUFF_DONE       0x00000001  /* buffer done */
+  uint32        locch2intMask;
+  uint32        unused5;
+  uint32        locch2descaddr;
+  uint32        locch2status1;
+#define LOCAL_DESC_STATE        0xE0000000
+#define PCI_DESC_STATE          0x1C000000
+#define BYTE_DONE               0x03FFC000
+#define RING_ADDR               0x00003FFF
+  uint32        locch2status2;
+#define BUFPTR_OFFSET           0x1FFF0000
+#define PCI_MASTER_STATE        0x000000C0
+#define LOC_MASTER_STATE        0x00000038
+#define CONTROL_STATE           0x00000007
+  uint32        unused6;
+
+  uint32        locch1Ctl;              /*internal system bus to PCI DMA (upstream) local control */
+#define DMA_U2P_LE              0x00000200  /* local bus is little endian */
+#define DMA_U2P_NOSWAP          0x00000100  /* lccal bus is little endian but no data swapped */
+  uint32        locch1intstat;
+  uint32        locch1intmask;
+  uint32        unused7;
+  uint32        locch1descaddr;
+  uint32        locch1status1;
+  uint32        locch1status2;
+  uint32        unused8;
+
+  uint32        pcich1ctl;              /* internal system bus to PCI DMA PCI control */
+  uint32        pcich1intstat;
+  uint32        pcich1intmask;
+  uint32        pcich1descaddr;
+  uint32        pcich1status1;
+  uint32        pcich1status2;
+
+  uint32        pcich2Ctl;              /* PCI to internal system bus DMA PCI control */
+  uint32        pcich2intstat;
+  uint32        pcich2intmask;
+  uint32        pcich2descaddr;
+  uint32        pcich2status1;
+  uint32        pcich2status2;
+
+  uint32        perm_id;                /* permanent device and vendor id */
+  uint32        perm_rev;               /* permanent revision id */
+} MpiRegisters;
+
+#define MPI ((volatile MpiRegisters * const) MPI_BASE)
+
+/* PCI configuration address space start offset 0x40 */
+#define BRCM_PCI_CONFIG_TIMER               0x40
+#define BRCM_PCI_CONFIG_TIMER_RETRY_MASK    0x0000FF00
+#define BRCM_PCI_CONFIG_TIMER_TRDY_MASK     0x000000FF
+
+typedef struct USBControl {
+    uint32 BrtControl1;
+    uint32 BrtControl2;
+    uint32 BrtStatus1;
+    uint32 BrtStatus2;
+    uint32 UTMIControl1;
+    uint32 TestPortControl;
+    uint32 PllControl1;
+    uint32 SwapControl;
+#define USB_DEVICE_SEL          (1<<6)
+#define EHCI_LOGICAL_ADDRESS_EN (1<<5)
+#define EHCI_ENDIAN_SWAP        (1<<4)
+#define EHCI_DATA_SWAP          (1<<3)
+#define OHCI_LOGICAL_ADDRESS_EN (1<<2)
+#define OHCI_ENDIAN_SWAP        (1<<1)
+#define OHCI_DATA_SWAP          (1<<0)
+    uint32 unused1;
+    uint32 FrameAdjustValue;
+    uint32 Setup;
+#define USBH_IOC                (1<<4)
+    uint32 MDIO;
+    uint32 MDIO32;
+    uint32 USBSimControl;
+} USBControl;
+
+#define USBH ((volatile USBControl * const) USBH_CFG_BASE)
+
+/*
+** GPON SERDES Registers
+*/
+typedef struct GponSerdesRegs {
+  uint32 topCfg;
+  uint32 swReset;
+  uint32 aeCfg;
+  uint32 aeStatus;
+  uint32 phyCfg;
+  uint32 phyStatus;
+  uint32 mdioWr;
+  uint32 mdioRd;
+  uint32 reserved[2];
+  uint32 fifoCfg;
+  uint32 fifoStatus;
+  uint32 patternCfg[4];
+  uint32 patternStatus[2];
+  uint32 laserCfg;
+#define GPON_SERDES_LASERMODE_MASK (3<<30)
+#define GPON_SERDES_LASERMODE_NORMAL (0<<30)
+#define GPON_SERDES_LASERMODE_FORCE_OFF (1<<30)
+#define GPON_SERDES_LASERMODE_FORCE_ON (2<<30)
+  uint32 laserStatus;
+  uint32 miscCfg;
+  uint32 miscStatus;
+  uint32 phDet[5];
+} GponSerdesRegs;
+
+#define GPON_SERDES ((volatile GponSerdesRegs * const) GPON_SERDES_BASE)
+
+
+/*
+** PCI-E
+*/
+typedef struct PcieRegs{
+  uint32 devVenID;
+  uint16 command;
+  uint16 status;
+  uint32 revIdClassCode;
+  uint32 headerTypeLatCacheLineSize;
+  uint32 bar1;
+  uint32 bar2;
+  uint32 priSecBusNo;
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_MASK              0x00ff0000
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SUB_BUS_NO_SHIFT             16
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_MASK              0x0000ff00
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_SEC_BUS_NO_SHIFT             8
+#define PCIE_CFG_TYPE1_PRI_SEC_BUS_NO_PRI_BUS_NO_MASK              0x000000ff
+} PcieRegs;
+
+typedef struct PcieBlk404Regs{
+  uint32 unused;          /* 0x404 */
+  uint32 config2;         /* 0x408 */
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_SIZE_MASK         0x0000000f
+#define PCIE_IP_BLK404_CONFIG_2_BAR1_DISABLE           0
+  uint32 config3;         /* 0x40c */
+  uint32 pmDataA;         /* 0x410 */
+  uint32 pmDataB;         /* 0x414 */
+} PcieBlk404Regs;
+
+typedef struct PcieBlk428Regs{
+   uint32 vpdIntf;        /* 0x428 */
+   uint16 unused_g;       /* 0x42c */
+   uint16 vpdAddrFlag;    /* 0x42e */
+   uint32 vpdData;        /* 0x430 */
+   uint32 idVal1;         /* 0x434 */
+   uint32 idVal2;         /* 0x438 */
+   uint32 idVal3;         /* 0x43c */
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_MASK                    0xff000000
+#define PCIE_IP_BLK428_ID_VAL3_REVISION_ID_SHIFT                   24
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_MASK                     0x00ffffff
+#define PCIE_IP_BLK428_ID_VAL3_CLASS_CODE_SHIFT                    16
+#define PCIE_IP_BLK428_ID_VAL3_SUB_CLASS_CODE_SHIFT                 8
+}PcieBlk428Regs;
+
+typedef struct PcieBridgeRegs{
+   uint32 bar1Remap;       /* 0x0818*/
+   uint32 bar2Remap;       /* 0x081c*/
+   uint32 bridgeOptReg1;   /* 0x0820*/
+#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE                  (1 << 4)
+#define PCIE_BRIDGE_OPT_REG1_EN_RD_BE_NOSWAP           (1 << 5)
+   uint32 bridgeOptReg2;    /* 0x0824*/
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_MASK    0xe0000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_func_no_SHIFT   29
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_MASK     0x1f000000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_dev_no_SHIFT    24
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_MASK     0x00ff0000
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bus_no_SHIFT    16
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_MASK     0x00000080
+#define PCIE_BRIDGE_OPT_REG2_cfg_type1_bd_sel_SHIFT    7
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_MASK     0x00000040
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_timeout_SHIFT    6
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_MASK       0x00000020
+#define PCIE_BRIDGE_OPT_REG2_dis_pcie_abort_SHIFT      5
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_MASK    0x00000010
+#define PCIE_BRIDGE_OPT_REG2_enable_tx_crd_chk_SHIFT   4
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_MASK   0x00000004
+#define PCIE_BRIDGE_OPT_REG2_dis_ubus_ur_decode_SHIFT  2
+#define PCIE_BRIDGE_OPT_REG2_cfg_reserved_MASK         0x0000ff0b
+}PcieBridgeRegs;
+
+typedef struct PcieBlk1000Regs{
+   uint32 undisclosed[18]; /*0x1000 - 0x1044*/
+   uint32 dlStatus;        /* 0x1048 */
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_MASK                   0x00002000
+#define PCIE_IP_BLK1000_DL_STATUS_PHYLINKUP_SHIFT                  13
+}PcieBlk1000Regs;
+
+typedef struct PcieBlk1800Regs{
+#define NUM_PCIE_BLK_1800_PHY_CTRL_REGS         4
+  uint32 phyCtrl[NUM_PCIE_BLK_1800_PHY_CTRL_REGS];
+#define REG_POWERDOWN_P1PLL_ENA                      (1<<12)
+  uint32 phyErrorAttnVec;
+  uint32 phyErrorAttnMask;
+#define NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS   3
+  uint32 phyltssmHist[NUM_PCIE_BLK_1800_PHY_LTSSM_HIST_REGS];
+#define NUM_PCIE_BLK_1800_PHY_DBG_REGS          11
+  uint32 phyDbg[NUM_PCIE_BLK_1800_PHY_DBG_REGS];
+} PcieBlk1800Regs;
+
+#define PCIEH_DEV_OFFSET              0x8000
+#define PCIEH                         ((volatile uint32 * const) PCIE_BASE)
+#define PCIEH_REGS          ((volatile PcieCfeType1Regs * const) PCIE_BASE)
+#define PCIEH_BLK_404_REGS            ((volatile PcieBlk404Regs * const)(PCIE_BASE+0x404))
+#define PCIEH_BLK_428_REGS            ((volatile PcieBlk428Regs * const)(PCIE_BASE+0x428))
+#define PCIEH_BRIDGE_REGS             ((volatile PcieBridgeRegs * const) (PCIE_BASE+0x818))
+#define PCIEH_BLK_1000_REGS           ((volatile PcieBlk1000Regs * const) (PCIE_BASE+0x1000))
+#define PCIEH_BLK_1800_REGS           ((volatile PcieBlk1800Regs * const) (PCIE_BASE+0x1800))
+
+/*
+** NAND Controller Registers
+*/
+typedef struct NandCtrlRegs {
+    uint32 NandRevision;            /* NAND Revision */
+    uint32 NandCmdStart;            /* Nand Flash Command Start */
+    uint32 NandCmdExtAddr;          /* Nand Flash Command Extended Address */
+    uint32 NandCmdAddr;             /* Nand Flash Command Address */
+    uint32 NandCmdEndAddr;          /* Nand Flash Command End Address */
+    uint32 NandNandBootConfig;      /* Nand Flash Boot Config */
+#define NBC_AUTO_DEV_ID_CFG 0x40000000
+    uint32 NandCsNandXor;           /* Nand Flash EBI CS Address XOR with */
+} NandCtrlRegs;
+
+#define NAND ((volatile NandCtrlRegs * const) NAND_REG_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/shared/opensource/include/bcm963xx/bcmSpi.h b/shared/opensource/include/bcm963xx/bcmSpi.h
new file mode 100755
index 0000000..dfbfb4f
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/bcmSpi.h
@@ -0,0 +1,55 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCM_SPI_H__
+#define __BCM_SPI_H__
+
+#ifndef _CFE_ 
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+struct bcmspi
+{
+    spinlock_t               lock;
+    char *                   devName;
+    int                      irq;
+    unsigned                 bus_num;
+    unsigned                 num_chipselect;  
+    u8                       stopping;
+    struct list_head         queue;
+    struct platform_device  *pdev;
+    struct spi_transfer     *curTrans;
+};
+#endif
+
+#define BCM_SPI_READ  0
+#define BCM_SPI_WRITE 1
+#define BCM_SPI_FULL  2
+
+#endif /* __BCM_SPI_H__ */
+
diff --git a/shared/opensource/include/bcm963xx/bcmSpiRes.h b/shared/opensource/include/bcm963xx/bcmSpiRes.h
new file mode 100755
index 0000000..cb39756
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/bcmSpiRes.h
@@ -0,0 +1,101 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+#ifndef __BCMSPIRES_H__
+#define __BCMSPIRES_H__ 
+
+#ifndef _CFE_
+#include <linux/spi/spi.h> 
+#endif
+
+#define SPI_STATUS_OK                (0)
+#define SPI_STATUS_INVALID_LEN      (-1)
+#define SPI_STATUS_ERR              (-2)
+
+/* legacy and HS controllers can coexist - use bus num to differentiate */
+#define LEG_SPI_BUS_NUM  0
+#define HS_SPI_BUS_NUM   1
+
+#define LEG_SPI_CLOCK_DEF   2
+
+#if defined(_BCM96816_) || defined(CONFIG_BCM96816) || defined(_BCM96362_) || defined(CONFIG_BCM96362)
+#define HS_SPI_PLL_FREQ     400000000
+#else
+#define HS_SPI_PLL_FREQ     133333333
+#endif
+#define HS_SPI_CLOCK_DEF    40000000
+#define HS_SPI_BUFFER_LEN   512
+
+/* used to specify ctrlState for the interface BcmSpiReserveSlave2 
+   SPI_CONTROLLER_STATE_SET is used to differentiate a value of 0 which results in
+   the controller using default values and the case where CPHA_EXT, GATE_CLK_SSOFF,
+   CLK_POLARITY, and ASYNC_CLOCK all need to be 0 
+
+   SPI MODE sets the values for CPOL and CPHA
+   SPI_CONTROLLER_STATE_CPHA_EXT will extend these modes
+CPOL = 0 -> base value of clock is 0
+CPHA = 0, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge
+CPHA = 1, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge
+CPHA = 0, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge
+CPHA = 1, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge
+
+CPOL = 1 -> base value of clock is 1
+CPHA = 0, CPHA_EXT = 0 -> latch data on falling edge, launch data on rising edge
+CPHA = 1, CPHA_EXT = 0 -> latch data on rising edge, launch data on falling edge
+CPHA = 0, CPHA_EXT = 1 -> latch data on falling edge, launch data on falling edge
+CPHA = 1, CPHA_EXT = 1 -> latch data on rising edge, launch data on rising edge
+*/
+#define SPI_CONTROLLER_STATE_SET             (1 << 31)
+#define SPI_CONTROLLER_STATE_CPHA_EXT        (1 << 30)
+#define SPI_CONTROLLER_STATE_GATE_CLK_SSOFF  (1 << 29)
+#define SPI_CONTROLLER_STATE_CLK_POLARITY    (1 << 28)
+#define SPI_CONTROLLER_STATE_ASYNC_CLOCK     (1 << 27)
+
+/* set mode and controller state based on CHIP defaults 
+   these values do not matter for the legacy controller */
+#if defined(CONFIG_BCM96816)
+#define SPI_MODE_DEFAULT              SPI_MODE_1
+#define SPI_CONTROLLER_STATE_DEFAULT  (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF | SPI_CONTROLLER_STATE_CPHA_EXT)  
+#elif (defined(CONFIG_BCM96362) || defined(CONFIG_BCM96328))
+#define SPI_MODE_DEFAULT              SPI_MODE_0
+#define SPI_CONTROLLER_STATE_DEFAULT  (SPI_CONTROLLER_STATE_GATE_CLK_SSOFF)  
+#else
+#define SPI_MODE_DEFAULT              SPI_MODE_3
+#define SPI_CONTROLLER_STATE_DEFAULT  (0)
+#endif
+
+#ifndef _CFE_
+int BcmSpiReserveSlave(int busNum, int slaveId, int maxFreq);
+int BcmSpiReserveSlave2(int busNum, int slaveId, int maxFreq, int mode, int ctrlState);
+int BcmSpiReleaseSlave(int busNum, int slaveId);
+int BcmSpiSyncTrans(unsigned char *txBuf, unsigned char *rxBuf, int prependcnt, int nbytes, int busNum, int slaveId);
+#endif
+
+int BcmSpi_SetFlashCtrl( int, int, int, int, int );
+int BcmSpi_GetMaxRWSize( int );
+int BcmSpi_Read(unsigned char *, int, int, int, int, int);
+int BcmSpi_Write(unsigned char *, int, int, int, int);
+
+#endif /* __BCMSPIRES_H__ */
+
diff --git a/shared/opensource/include/bcm963xx/bcmTag.h b/shared/opensource/include/bcm963xx/bcmTag.h
new file mode 100755
index 0000000..8a1ca24
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/bcmTag.h
@@ -0,0 +1,175 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+//**************************************************************************************
+// File Name  : bcmTag.h
+//
+// Description: add tag with validation system to the firmware image file to be uploaded
+//              via http
+//
+// Created    : 02/28/2002  seanl
+//**************************************************************************************
+
+#ifndef _BCMTAG_H_
+#define _BCMTAG_H_
+
+
+#define BCM_SIG_1   "Broadcom Corporation"
+#define BCM_SIG_2   "ver. 2.0"          // was "firmware version 2.0" now it is split 6 char out for chip id.
+
+#define BCM_TAG_VER         "6"
+
+// file tag (head) structure all is in clear text except validationTokens (crc, md5, sha1, etc). Total: 128 unsigned chars
+#define TAG_LEN         256
+#define TAG_VER_LEN     4
+#define SIG_LEN         20
+#define SIG_LEN_2       14   // Original second SIG = 20 is now devided into 14 for SIG_LEN_2 and 6 for CHIP_ID
+#define CHIP_ID_LEN		6	
+#define IMAGE_LEN       10
+#define ADDRESS_LEN     12
+#define FLAG_LEN        2
+#define TOKEN_LEN       20
+#define BOARD_ID_LEN    16
+#define RESERVED_LEN    (TAG_LEN - TAG_VER_LEN - SIG_LEN - SIG_LEN_2 - CHIP_ID_LEN - BOARD_ID_LEN - \
+                        (4*IMAGE_LEN) - (3*ADDRESS_LEN) - (3*FLAG_LEN) - (2*TOKEN_LEN))
+
+
+// TAG for downloadable image (kernel plus file system)
+typedef struct _FILE_TAG
+{
+    char tagVersion[TAG_VER_LEN];       // tag version.  Will be 2 here.
+    char signiture_1[SIG_LEN];          // text line for company info
+    char signiture_2[SIG_LEN_2];        // additional info (can be version number)
+    char chipId[CHIP_ID_LEN];			 // chip id 
+    char boardId[BOARD_ID_LEN];         // board id
+    char bigEndian[FLAG_LEN];           // if = 1 - big, = 0 - little endia of the host
+    char totalImageLen[IMAGE_LEN];      // the sum of all the following length
+    char cfeAddress[ADDRESS_LEN];       // if non zero, cfe starting address
+    char cfeLen[IMAGE_LEN];             // if non zero, cfe size in clear ASCII text.
+    char rootfsAddress[ADDRESS_LEN];    // if non zero, filesystem starting address
+    char rootfsLen[IMAGE_LEN];          // if non zero, filesystem size in clear ASCII text.
+    char kernelAddress[ADDRESS_LEN];    // if non zero, kernel starting address
+    char kernelLen[IMAGE_LEN];          // if non zero, kernel size in clear ASCII text.
+    char imageSequence[FLAG_LEN * 2];   // incrments everytime an image is flashed
+    char reserved[RESERVED_LEN];        // reserved for later use
+    char imageValidationToken[TOKEN_LEN];// image validation token - can be crc, md5, sha;  for
+                                                 // now will be 4 unsigned char crc
+    char tagValidationToken[TOKEN_LEN]; // validation token for tag(from signiture_1 to end of // mageValidationToken)
+} FILE_TAG, *PFILE_TAG;
+
+/* Whole flash image TAG definitions. */
+#define WFI_VERSION             0x00005731
+#define WFI_ANY_VERS_MASK       0x0000ff00
+#define WFI_ANY_VERS            0x00005700
+#define WFI_NOR_FLASH           1
+#define WFI_NAND16_FLASH        2
+#define WFI_NAND128_FLASH       3
+
+/* TAG at end of whole flash ".w" image.  Size must be TOKEN_LEN. */
+typedef struct _WFI_TAG
+{
+    unsigned long wfiCrc;
+    unsigned long wfiVersion;
+    unsigned long wfiChipId;
+    unsigned long wfiFlashType;
+    unsigned long wfiReserved;
+} WFI_TAG, *PWFI_TAG;
+
+#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
+#define CRC_LEN 4
+
+// only included if for bcmTag.exe program
+#ifdef BCMTAG_EXE_USE
+
+static unsigned long Crc32_table[256] = {
+    0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
+    0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
+    0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
+    0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
+    0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
+    0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
+    0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
+    0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
+    0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
+    0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
+    0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
+    0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
+    0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
+    0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
+    0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
+    0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
+    0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
+    0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
+    0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
+    0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
+    0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
+    0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
+    0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
+    0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
+    0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
+    0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
+    0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
+    0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
+    0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
+    0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
+    0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
+    0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
+    0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
+    0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
+    0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
+    0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
+    0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
+    0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
+    0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
+    0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
+    0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
+    0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
+    0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
+    0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
+    0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
+    0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
+    0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
+    0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
+    0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
+    0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
+    0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
+    0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
+    0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
+    0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
+    0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
+    0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
+    0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
+    0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
+    0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
+    0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
+    0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
+    0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
+    0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
+    0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
+};
+#endif // BCMTAG_USE
+
+
+#endif // _BCMTAG_H_
+
diff --git a/shared/opensource/include/bcm963xx/bcm_hwdefs.h b/shared/opensource/include/bcm963xx/bcm_hwdefs.h
new file mode 100755
index 0000000..07ecc29
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/bcm_hwdefs.h
@@ -0,0 +1,193 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/***********************************************************************/
+/*                                                                     */
+/*   MODULE:  bcm_hwdefs.h                                             */
+/*   PURPOSE: Define all base device addresses and HW specific macros. */
+/*                                                                     */
+/***********************************************************************/
+#ifndef _BCM_HWDEFS_H
+#define _BCM_HWDEFS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define	DYING_GASP_API
+
+/*****************************************************************************/
+/*                    Physical Memory Map                                    */
+/*****************************************************************************/
+
+#define PHYS_DRAM_BASE          0x00000000      /* Dynamic RAM Base */
+#if defined(CONFIG_BRCM_IKOS)
+#define PHYS_FLASH_BASE         0x18000000      /* Flash Memory     */
+#else
+#define PHYS_FLASH_BASE         0x1FC00000      /* Flash Memory     */
+#endif
+
+/*****************************************************************************/
+/* Note that the addresses above are physical addresses and that programs    */
+/* have to use converted addresses defined below:                            */
+/*****************************************************************************/
+#define DRAM_BASE           (0x80000000 | PHYS_DRAM_BASE)   /* cached DRAM */
+#define DRAM_BASE_NOCACHE   (0xA0000000 | PHYS_DRAM_BASE)   /* uncached DRAM */
+
+/* Binary images are always built for a standard MIPS boot address */
+#define IMAGE_BASE          (0xA0000000 | PHYS_FLASH_BASE)
+
+/* Some chips don't support alternative boot vector */
+#if defined(CONFIG_BRCM_IKOS)
+#define FLASH_BASE          (0xA0000000 | PHYS_FLASH_BASE)  /* uncached Flash  */
+#define BOOT_OFFSET         0
+#else
+#if defined(_BCM96328_) || defined(CONFIG_BCM96328) || defined(_BCM96362_) || defined(CONFIG_BCM96362)
+#define FLASH_BASE          0xB8000000
+#else
+#define FLASH_BASE          (0xA0000000 | (MPI->cs[0].base & 0xFFFFFF00))
+#endif
+#define BOOT_OFFSET         (FLASH_BASE - IMAGE_BASE)
+#endif
+
+/*****************************************************************************/
+/*  Select the PLL value to get the desired CPU clock frequency.             */
+/*****************************************************************************/
+#define FPERIPH            50000000
+
+/*****************************************************************************/
+/* Board memory type offset                                                  */
+/*****************************************************************************/
+#define ONEK                            1024
+#define FLASH_LENGTH_BOOT_ROM           (64*ONEK)
+
+#define PROJECT_ID_LEN          7 /* Foxconn added by zacker, 02/29/2008, strlen("U12H094") */
+#ifdef _CFE_
+#define FLASH_SIZE              32 * 1024 * 1024
+#endif
+#define BOARD_DATA_ADDR         (FLASH_BASE + FLASH_SIZE - 0x20000)
+#define BOARD_FOXNVRAM_ADDR     (FLASH_BASE + FLASH_SIZE - 0x10000)
+#define FOX_BOARD_ID_MAX_LEN    64
+#define BOARD_ID                "U12L161"
+/*****************************************************************************/
+/*       NVRAM Offset and definition                                         */
+/*****************************************************************************/
+#define NVRAM_SECTOR                    0
+#define NVRAM_DATA_OFFSET               0x0580
+#define NVRAM_DATA_ID                   0x0f1e2d3c  // This is only for backwards compatability
+
+#define NVRAM_LENGTH                    ONEK    // 1k nvram 
+#define NVRAM_VERSION_NUMBER            6
+#define NVRAM_FULL_LEN_VERSION_NUMBER   5 /* version in which the checksum was
+                                             placed at the end of the NVRAM
+                                             structure */
+
+#define NVRAM_BOOTLINE_LEN              256
+#define NVRAM_BOARD_ID_STRING_LEN       16
+#define NVRAM_MAC_ADDRESS_LEN           6
+
+#define NVRAM_GPON_SERIAL_NUMBER_LEN    13
+#define NVRAM_GPON_PASSWORD_LEN         11
+
+#define NVRAM_WLAN_PARAMS_LEN      256
+#define NVRAM_WPS_DEVICE_PIN_LEN   8
+
+#define THREAD_NUM_ADDRESS_OFFSET       (NVRAM_DATA_OFFSET + 4 + NVRAM_BOOTLINE_LEN + NVRAM_BOARD_ID_STRING_LEN)
+#define THREAD_NUM_ADDRESS              (0x80000000 + THREAD_NUM_ADDRESS_OFFSET)
+
+#define DEFAULT_BOOTLINE    "e=192.168.1.1:ffffff00 h=192.168.1.100 g= r=f f=vmlinux i=bcm963xx_fs_kernel d=1 p=0 "
+#define DEFAULT_BOARD_IP    "192.168.1.1"
+#define DEFAULT_MAC_NUM     10
+#define DEFAULT_BOARD_MAC   "00:10:18:00:00:00"
+#define DEFAULT_TP_NUM      0
+#define DEFAULT_PSI_SIZE    24
+#define DEFAULT_GPON_SN     "BRCM12345678"
+#define DEFAULT_GPON_PW     "          "
+
+#define DEFAULT_WPS_DEVICE_PIN     "12345670"
+
+#define DEFAULT_VOICE_BOARD_ID     "NONE"
+
+#define NVRAM_MAC_COUNT_MAX 32
+#define NVRAM_MAX_PSI_SIZE  64
+#define NVRAM_MAX_SYSLOG_SIZE  256
+
+#define NP_BOOT             0
+#define NP_ROOTFS_1         1
+#define NP_ROOTFS_2         2
+#define NP_DATA             3
+#define NP_BBT              4
+#define NP_TOTAL            5
+
+#define NAND_DATA_SIZE_KB       1024
+#define NAND_BBT_THRESHOLD_KB   (512 * 1024)
+#define NAND_BBT_SMALL_SIZE_KB  1024
+#define NAND_BBT_BIG_SIZE_KB    4096
+
+#define NAND_CFE_RAM_NAME   "cferam.000"
+
+#ifndef _LANGUAGE_ASSEMBLY
+typedef struct
+{
+    unsigned long ulVersion;
+    char szBootline[NVRAM_BOOTLINE_LEN];
+    char szBoardId[NVRAM_BOARD_ID_STRING_LEN];
+    unsigned long ulMainTpNum;
+    unsigned long ulPsiSize;
+    unsigned long ulNumMacAddrs;
+    unsigned char ucaBaseMacAddr[NVRAM_MAC_ADDRESS_LEN];
+    char pad;
+    char backupPsi;  /**< if 0x01, allocate space for a backup PSI */
+    unsigned long ulCheckSumV4;
+    char gponSerialNumber[NVRAM_GPON_SERIAL_NUMBER_LEN];
+    char gponPassword[NVRAM_GPON_PASSWORD_LEN];
+    char wpsDevicePin[NVRAM_WPS_DEVICE_PIN_LEN];
+    char wlanParams[NVRAM_WLAN_PARAMS_LEN];
+    unsigned long ulSyslogSize; /**< number of KB to allocate for persistent syslog */
+    unsigned long ulNandPartOfsKb[NP_TOTAL];
+    unsigned long ulNandPartSizeKb[NP_TOTAL];
+    char szVoiceBoardId[NVRAM_BOARD_ID_STRING_LEN];
+    unsigned long afeId[2];
+    char szFirmwareUpgradeBoardId[32];		/* foxconn added Bob, 07/12/2010, for TFTP firmware upgrade */
+    char chUnused[332];		/* reduce array size from 364 to 332, total size of NVRAM_DATA is unchanged, Bob, 07/12/2010 */
+    unsigned long ulCheckSum;
+} NVRAM_DATA, *PNVRAM_DATA;
+#endif
+
+#define BOOT_LATEST_IMAGE   '0'
+#define BOOT_PREVIOUS_IMAGE '1'
+
+/*****************************************************************************/
+/*       Misc Offsets                                                        */
+/*****************************************************************************/
+#define CFE_VERSION_OFFSET           0x0570
+#define CFE_VERSION_MARK_SIZE        5
+#define CFE_VERSION_SIZE             5
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BCM_HWDEFS_H */
+
diff --git a/shared/opensource/include/bcm963xx/bcmnetlink.h b/shared/opensource/include/bcm963xx/bcmnetlink.h
new file mode 100755
index 0000000..e5fc77f
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/bcmnetlink.h
@@ -0,0 +1,47 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/**************************************************************************
+ * File Name  : bcmnetlink.h
+ *
+ * Description: This file defines broadcom specific netlink message types
+ ***************************************************************************/
+#ifndef _BCMNETLINK_H
+#define _BCMNETLINK_H
+
+#include<linux/netlink.h>
+
+#ifndef NETLINK_BRCM_MONITOR
+#define NETLINK_BRCM_MONITOR 25
+#endif
+
+/* message types exchanged using NETLINK_BRCM_MONITOR */
+#define MSG_NETLINK_BRCM_WAKEUP_MONITOR_TASK 0X1000
+
+#define MSG_NETLINK_BRCM_LINK_STATUS_CHANGED 0X2000
+
+
+extern void kerSysSendtoMonitorTask(int msgType, char *msgData, int msgDataLen);
+
+#endif /*_BCMNETLINK_H */
diff --git a/shared/opensource/include/bcm963xx/boardparms.h b/shared/opensource/include/bcm963xx/boardparms.h
new file mode 100755
index 0000000..7fec91c
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/boardparms.h
@@ -0,0 +1,453 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/**************************************************************************
+ * File Name  : boardparms.h
+ *
+ * Description: This file contains definitions and function prototypes for
+ *              the BCM63xx board parameter access functions.
+ *
+ * Updates    : 07/14/2003  Created.
+ ***************************************************************************/
+
+#if !defined(_BOARDPARMS_H)
+#define _BOARDPARMS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Return codes. */
+#define BP_SUCCESS                              0
+#define BP_BOARD_ID_NOT_FOUND                   1
+#define BP_VALUE_NOT_DEFINED                    2
+#define BP_BOARD_ID_NOT_SET                     3
+
+/* Values for EthernetMacInfo PhyType. */
+#define BP_ENET_NO_PHY                          0
+#define BP_ENET_INTERNAL_PHY                    1
+#define BP_ENET_EXTERNAL_SWITCH                 2
+#define BP_ENET_SWITCH_VIA_INTERNAL_PHY         3      /* it is for cpu internal phy connects to port 4 of 5325e */
+
+/* Values for EthernetMacInfo Configuration type. */
+#define BP_ENET_CONFIG_MDIO                     0       /* Internal PHY, External PHY, Switch+(no GPIO, no SPI, no MDIO Pseudo phy */
+#define BP_ENET_CONFIG_MDIO_PSEUDO_PHY          1
+#define BP_ENET_CONFIG_SPI_SSB_0                2
+#define BP_ENET_CONFIG_SPI_SSB_1                3
+#define BP_ENET_CONFIG_SPI_SSB_2                4
+#define BP_ENET_CONFIG_SPI_SSB_3                5
+#define BP_ENET_CONFIG_MMAP                     6
+#define BP_ENET_CONFIG_GPIO_MDIO                7       /* use GPIO to simulate MDC/MDIO */
+
+/* Values for VoIPDSPInfo DSPType. */
+#define BP_VOIP_NO_DSP                          0
+#define BP_VOIP_DSP                             1
+#define BP_VOIP_MIPS                            2
+
+/* Values for GPIO pin assignments (AH = Active High, AL = Active Low). */
+#define BP_GPIO_NUM_MASK                        0x00FF
+#define BP_ACTIVE_MASK                          0x8000
+#define BP_ACTIVE_HIGH                          0x0000
+#define BP_ACTIVE_LOW                           0x8000
+#define BP_GPIO_SERIAL                          0x4000
+
+#define BP_GPIO_0_AH                            (0)
+#define BP_GPIO_0_AL                            (0  | BP_ACTIVE_LOW)
+#define BP_GPIO_1_AH                            (1)
+#define BP_GPIO_1_AL                            (1  | BP_ACTIVE_LOW)
+#define BP_GPIO_2_AH                            (2)
+#define BP_GPIO_2_AL                            (2  | BP_ACTIVE_LOW)
+#define BP_GPIO_3_AH                            (3)
+#define BP_GPIO_3_AL                            (3  | BP_ACTIVE_LOW)
+#define BP_GPIO_4_AH                            (4)
+#define BP_GPIO_4_AL                            (4  | BP_ACTIVE_LOW)
+#define BP_GPIO_5_AH                            (5)
+#define BP_GPIO_5_AL                            (5  | BP_ACTIVE_LOW)
+#define BP_GPIO_6_AH                            (6)
+#define BP_GPIO_6_AL                            (6  | BP_ACTIVE_LOW)
+#define BP_GPIO_7_AH                            (7)
+#define BP_GPIO_7_AL                            (7  | BP_ACTIVE_LOW)
+#define BP_GPIO_8_AH                            (8)
+#define BP_GPIO_8_AL                            (8  | BP_ACTIVE_LOW)
+#define BP_GPIO_9_AH                            (9)
+#define BP_GPIO_9_AL                            (9  | BP_ACTIVE_LOW)
+#define BP_GPIO_10_AH                           (10)
+#define BP_GPIO_10_AL                           (10 | BP_ACTIVE_LOW)
+#define BP_GPIO_11_AH                           (11)
+#define BP_GPIO_11_AL                           (11 | BP_ACTIVE_LOW)
+#define BP_GPIO_12_AH                           (12)
+#define BP_GPIO_12_AL                           (12 | BP_ACTIVE_LOW)
+#define BP_GPIO_13_AH                           (13)
+#define BP_GPIO_13_AL                           (13 | BP_ACTIVE_LOW)
+#define BP_GPIO_14_AH                           (14)
+#define BP_GPIO_14_AL                           (14 | BP_ACTIVE_LOW)
+#define BP_GPIO_15_AH                           (15)
+#define BP_GPIO_15_AL                           (15 | BP_ACTIVE_LOW)
+#define BP_GPIO_16_AH                           (16)
+#define BP_GPIO_16_AL                           (16 | BP_ACTIVE_LOW)
+#define BP_GPIO_17_AH                           (17)
+#define BP_GPIO_17_AL                           (17 | BP_ACTIVE_LOW)
+#define BP_GPIO_18_AH                           (18)
+#define BP_GPIO_18_AL                           (18 | BP_ACTIVE_LOW)
+#define BP_GPIO_19_AH                           (19)
+#define BP_GPIO_19_AL                           (19 | BP_ACTIVE_LOW)
+#define BP_GPIO_20_AH                           (20)
+#define BP_GPIO_20_AL                           (20 | BP_ACTIVE_LOW)
+#define BP_GPIO_21_AH                           (21)
+#define BP_GPIO_21_AL                           (21 | BP_ACTIVE_LOW)
+#define BP_GPIO_22_AH                           (22)
+#define BP_GPIO_22_AL                           (22 | BP_ACTIVE_LOW)
+#define BP_GPIO_23_AH                           (23)
+#define BP_GPIO_23_AL                           (23 | BP_ACTIVE_LOW)
+#define BP_GPIO_24_AH                           (24)
+#define BP_GPIO_24_AL                           (24 | BP_ACTIVE_LOW)
+#define BP_GPIO_25_AH                           (25)
+#define BP_GPIO_25_AL                           (25 | BP_ACTIVE_LOW)
+#define BP_GPIO_26_AH                           (26)
+#define BP_GPIO_26_AL                           (26 | BP_ACTIVE_LOW)
+#define BP_GPIO_27_AH                           (27)
+#define BP_GPIO_27_AL                           (27 | BP_ACTIVE_LOW)
+#define BP_GPIO_28_AH                           (28)
+#define BP_GPIO_28_AL                           (28 | BP_ACTIVE_LOW)
+#define BP_GPIO_29_AH                           (29)
+#define BP_GPIO_29_AL                           (29 | BP_ACTIVE_LOW)
+#define BP_GPIO_30_AH                           (30)
+#define BP_GPIO_30_AL                           (30 | BP_ACTIVE_LOW)
+#define BP_GPIO_31_AH                           (31)
+#define BP_GPIO_31_AL                           (31 | BP_ACTIVE_LOW)
+#define BP_GPIO_32_AH                           (32)
+#define BP_GPIO_32_AL                           (32 | BP_ACTIVE_LOW)
+#define BP_GPIO_33_AH                           (33)
+#define BP_GPIO_33_AL                           (33 | BP_ACTIVE_LOW)
+#define BP_GPIO_34_AH                           (34)
+#define BP_GPIO_34_AL                           (34 | BP_ACTIVE_LOW)
+#define BP_GPIO_35_AH                           (35)
+#define BP_GPIO_35_AL                           (35 | BP_ACTIVE_LOW)
+#define BP_GPIO_36_AH                           (36)
+#define BP_GPIO_36_AL                           (36 | BP_ACTIVE_LOW)
+#define BP_GPIO_37_AH                           (37)
+#define BP_GPIO_37_AL                           (37 | BP_ACTIVE_LOW)
+#define BP_GPIO_38_AH                           (38)
+#define BP_GPIO_38_AL                           (38 | BP_ACTIVE_LOW)
+#define BP_GPIO_39_AH                           (39)
+#define BP_GPIO_39_AL                           (39 | BP_ACTIVE_LOW)
+#define BP_GPIO_40_AH                           (40)
+#define BP_GPIO_40_AL                           (40 | BP_ACTIVE_LOW)
+#define BP_GPIO_41_AH                           (41)
+#define BP_GPIO_41_AL                           (41 | BP_ACTIVE_LOW)
+#define BP_GPIO_42_AH                           (42)
+#define BP_GPIO_42_AL                           (42 | BP_ACTIVE_LOW)
+#define BP_GPIO_43_AH                           (43)
+#define BP_GPIO_43_AL                           (43 | BP_ACTIVE_LOW)
+#define BP_GPIO_44_AH                           (44)
+#define BP_GPIO_44_AL                           (44 | BP_ACTIVE_LOW)
+#define BP_GPIO_45_AH                           (45)
+#define BP_GPIO_45_AL                           (45 | BP_ACTIVE_LOW)
+#define BP_GPIO_46_AH                           (46)
+#define BP_GPIO_46_AL                           (46 | BP_ACTIVE_LOW)
+#define BP_GPIO_47_AH                           (47)
+#define BP_GPIO_47_AL                           (47 | BP_ACTIVE_LOW)
+
+#define BP_SERIAL_GPIO_0_AH                     (0  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_0_AL                     (0  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_1_AH                     (1  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_1_AL                     (1  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_2_AH                     (2  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_2_AL                     (2  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_3_AH                     (3  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_3_AL                     (3  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_4_AH                     (4  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_4_AL                     (4  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_5_AH                     (5  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_5_AL                     (5  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_6_AH                     (6  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_6_AL                     (6  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_7_AH                     (7  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_7_AL                     (7  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_8_AH                     (8  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_8_AL                     (8  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_9_AH                     (9  | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_9_AL                     (9  | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_10_AH                    (10 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_10_AL                    (10 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_11_AH                    (11 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_11_AL                    (11 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_12_AH                    (12 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_12_AL                    (12 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_13_AH                    (13 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_13_AL                    (13 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_14_AH                    (14 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_14_AL                    (14 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_15_AH                    (15 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_15_AL                    (15 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_16_AH                    (16 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_16_AL                    (16 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_17_AH                    (17 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_17_AL                    (17 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_18_AH                    (18 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_18_AL                    (18 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_19_AH                    (19 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_19_AL                    (19 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_20_AH                    (20 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_20_AL                    (20 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_21_AH                    (21 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_21_AL                    (21 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_22_AH                    (22 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_22_AL                    (22 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+#define BP_SERIAL_GPIO_23_AH                    (23 | BP_GPIO_SERIAL)
+#define BP_SERIAL_GPIO_23_AL                    (23 | BP_GPIO_SERIAL | BP_ACTIVE_LOW)
+
+/* Values for external interrupt assignments. */
+#define BP_EXT_INTR_0                           0
+#define BP_EXT_INTR_1                           1
+#define BP_EXT_INTR_2                           2
+#define BP_EXT_INTR_3                           3
+#define BP_EXT_INTR_4                           4
+#define BP_EXT_INTR_5                           5
+
+/* Values for chip select assignments. */
+#define BP_CS_0                                 0
+#define BP_CS_1                                 1
+#define BP_CS_2                                 2
+#define BP_CS_3                                 3
+
+#define BP_OVERLAY_GPON_TX_EN_L                 (1<<0)
+#define BP_OVERLAY_PCI                          (1<<0)
+#define BP_OVERLAY_CB                           (1<<1)
+#define BP_OVERLAY_SPI_EXT_CS                   (1<<2)
+#define BP_OVERLAY_UART1                        (1<<3)
+#define BP_OVERLAY_PHY                          (1<<4)
+#define BP_OVERLAY_SERIAL_LEDS                  (1<<5)
+#define BP_OVERLAY_EPHY_LED_0                   (1<<6)
+#define BP_OVERLAY_EPHY_LED_1                   (1<<7)
+#define BP_OVERLAY_GPHY_LED_0                   (1<<6)
+#define BP_OVERLAY_GPHY_LED_1                   (1<<7)
+#define BP_OVERLAY_EPHY_LED_2                   (1<<8)
+#define BP_OVERLAY_EPHY_LED_3                   (1<<9)
+#define BP_OVERLAY_INET_LED                     (1<<10)
+#define BP_OVERLAY_MOCA_LED                     (1<<11)
+#define BP_OVERLAY_USB_LED                      (1<<12)
+#define BP_OVERLAY_USB_DEVICE                   (1<<13)
+
+/* Value for GPIO and external interrupt fields that are not used. */
+#define BP_NOT_DEFINED                          0xffff
+
+/* Maximum size of the board id string. */
+#define BP_BOARD_ID_LEN                         16
+
+/* Maximum number of Ethernet MACs. */
+#define BP_MAX_ENET_MACS                        2
+#define BP_MAX_SWITCH_PORTS                     8
+/* Maximum number of VoIP DSPs. */
+#define BP_MAX_VOIP_DSP                         2
+
+/* Wireless Antenna Settings. */
+#define BP_WLAN_ANT_MAIN                        0
+#define BP_WLAN_ANT_AUX                         1
+#define BP_WLAN_ANT_BOTH                        3
+
+/* Wireless FLAGS */
+#define BP_WLAN_MAC_ADDR_OVERRIDE               0x0001   /* use kerSysGetMacAddress for mac address */
+#define BP_WLAN_EXCLUDE_ONBOARD                 0x0002   /* exclude onboard wireless  */
+#define BP_WLAN_EXCLUDE_ONBOARD_FORCE           0x0004   /* force exclude onboard wireless even without addon card*/
+#define BP_WLAN_USE_OTP                         0x0008   /* don't use sw srom map, may fall to OTP or uninitialzed */
+
+#define BP_WLAN_NVRAM_NAME_LEN      16
+#define BP_WLAN_MAX_PATCH_ENTRY     32
+
+/* AFE IDs */
+#define BP_AFE_DEFAULT                  0
+
+#define BP_AFE_CHIP_INT                 (1 << 28)
+#define BP_AFE_CHIP_6505                (2 << 28)
+#define BP_AFE_CHIP_6306                (3 << 28)
+
+#define BP_AFE_LD_ISIL1556              (1 << 21)
+#define BP_AFE_LD_6301                  (2 << 21)
+#define BP_AFE_LD_6302                  (3 << 21)
+
+#define BP_AFE_FE_ANNEXA                (1 << 15)
+#define BP_AFE_FE_ANNEXB                (2 << 15)
+#define BP_AFE_FE_ANNEXJ                (3 << 15)
+
+#define BP_AFE_FE_AVMODE_COMBO          (0 << 13)
+#define BP_AFE_FE_AVMODE_ADSL           (1 << 13)
+#define BP_AFE_FE_AVMODE_VDSL           (2 << 13)
+
+/* VDSL only */
+#define BP_AFE_FE_REV_ISIL_REV1         (1 << 8)
+/* Combo */
+#define BP_AFE_FE_REV_6302_REV1         (1 << 8)
+#define BP_AFE_FE_REV_6302_REV_7_12     (1 << 8)
+#define BP_AFE_FE_REV_6302_REV_7_4      (2 << 8)
+
+#define BP_AFE_FE_REV_6302_REV_7_2_1    (3 << 8)
+#define BP_AFE_FE_REV_6302_REV_7_2      (4 << 8)
+#define BP_AFE_FE_REV_6302_REV_7_2_UR2  (5 << 8)
+#define BP_AFE_FE_REV_6302_REV_7_2_2    (6 << 8)
+/* ADSL only*/
+#define BP_AFE_FE_REV_6302_REV_5_2_1    (1 << 8)
+#define BP_AFE_FE_REV_6302_REV_5_2_2    (2 << 8)
+#define BP_AFE_FE_REV_6301_REV_5_1_1    (1 << 8)
+
+#define BP_GET_EXT_AFE_DEFINED
+
+#if !defined(__ASSEMBLER__)
+
+/* Information about Ethernet switch */
+typedef struct {
+  int port_map;
+  int phy_id[BP_MAX_SWITCH_PORTS];
+} ETHERNET_SW_INFO;
+
+/* WAN port flag in the phy_id of ETHERNET_SW_INFO */
+#define BCM_WAN_PORT                        0x40
+#define IsWanPort(id)                       (((id) & BCM_WAN_PORT) && ((id) != 0xFF))
+
+#define c0(n) (((n) & 0x55555555) + (((n) >> 1) & 0x55555555))
+#define c1(n) (((n) & 0x33333333) + (((n) >> 2) & 0x33333333))
+#define c2(n) (((n) & 0x0f0f0f0f) + (((n) >> 4) & 0x0f0f0f0f))
+#define bitcount(r, n) {r = n; r = c0(r); r = c1(r); r = c2(r); r %= 255;}
+
+/* Information about an Ethernet MAC.  If ucPhyType is BP_ENET_NO_PHY,
+ * then the other fields are not valid.
+ */
+typedef struct EthernetMacInfo
+{
+    unsigned char ucPhyType;                    /* BP_ENET_xxx             */
+    unsigned char ucPhyAddress;                 /* 0 to 31                 */
+    unsigned short usGpioLedPhyLinkSpeed;       /* GPIO pin or not defined */
+    unsigned short usConfigType;                /* Configuration type */
+    ETHERNET_SW_INFO sw;                        /* switch information */
+    unsigned short usGpioMDC;                   /* GPIO pin to simulate MDC */
+    unsigned short usGpioMDIO;                  /* GPIO pin to simulate MDIO */
+} ETHERNET_MAC_INFO, *PETHERNET_MAC_INFO;
+
+typedef struct WlanSromEntry {
+    char name[BP_WLAN_NVRAM_NAME_LEN];
+    unsigned short wordOffset;
+    unsigned short value;
+} WLAN_SROM_ENTRY;
+
+typedef struct WlanSromPatchInfo {
+    char szboardId[BP_BOARD_ID_LEN];
+    unsigned short usWirelessChipId;
+    unsigned short usNeededSize;
+    WLAN_SROM_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY];
+} WLAN_SROM_PATCH_INFO, *PWLAN_SROM_PATCH_INFO;
+
+typedef struct WlanPciEntry {
+    char name[BP_WLAN_NVRAM_NAME_LEN];
+    unsigned int dwordOffset;
+    unsigned int value;
+} WLAN_PCI_ENTRY;
+
+typedef struct WlanPciPatchInfo {
+    char szboardId[BP_BOARD_ID_LEN];
+    unsigned int usWirelessPciId;
+    int usNeededSize;
+    WLAN_PCI_ENTRY entries[BP_WLAN_MAX_PATCH_ENTRY];
+} WLAN_PCI_PATCH_INFO, *PWLAN_PCI_PATCH_INFO;
+
+/* Information about VoIP DSPs.  If ucDspType is BP_VOIP_NO_DSP,
+ * then the other fields are not valid.
+ */
+typedef struct VoIPDspInfo
+{
+    unsigned char  ucDspType;
+    unsigned char  ucDspAddress;
+    unsigned short usGpioLedVoip;
+    unsigned short usGpioVoip1Led;
+    unsigned short usGpioVoip1LedFail;
+    unsigned short usGpioVoip2Led;
+    unsigned short usGpioVoip2LedFail;
+    unsigned short usGpioPotsLed;
+    unsigned short usGpioDectLed;
+
+} VOIP_DSP_INFO;
+
+int BpSetBoardId( char *pszBoardId );
+int BpGetBoardId( char *pszBoardId);
+int BpGetBoardIds( char *pszBoardIds, int nBoardIdsSize );
+
+int BpGetGPIOverlays( unsigned short *pusValue );
+
+int BpGetRj11InnerOuterPairGpios( unsigned short *pusInner, unsigned short *pusOuter );
+int BpGetRtsCtsUartGpios( unsigned short *pusRts, unsigned short *pusCts );
+
+int BpGetAdslLedGpio( unsigned short *pusValue );
+int BpGetAdslFailLedGpio( unsigned short *pusValue );
+int BpGetSecAdslLedGpio( unsigned short *pusValue );
+int BpGetSecAdslFailLedGpio( unsigned short *pusValue );
+int BpGetWirelessSesLedGpio( unsigned short *pusValue );
+int BpGetHpnaLedGpio( unsigned short *pusValue );
+int BpGetWanDataLedGpio( unsigned short *pusValue );
+int BpGetWanErrorLedGpio( unsigned short *pusValue );
+int BpGetBootloaderPowerOnLedGpio( unsigned short *pusValue );
+int BpGetBootloaderStopLedGpio( unsigned short *pusValue );
+int BpGetFpgaResetGpio( unsigned short *pusValue );
+int BpGetGponLedGpio( unsigned short *pusValue );
+int BpGetGponFailLedGpio( unsigned short *pusValue );
+int BpGetMoCALedGpio( unsigned short *pusValue );
+int BpGetMoCAFailLedGpio( unsigned short *pusValue );
+
+int BpGetResetToDefaultExtIntr( unsigned short *pusValue );
+int BpGetWirelessSesExtIntr( unsigned short *pusValue );
+int BpGetHpnaExtIntr( unsigned long *pulValue );
+
+int BpGetHpnaChipSelect( unsigned long *pulValue );
+
+int BpGetWirelessAntInUse( unsigned short *pusValue );
+int BpGetWirelessFlags( unsigned short *pusValue );
+int BpGetWirelessPowerDownGpio( unsigned short *pusValue );
+int BpUpdateWirelessSromMap(unsigned short chipID, unsigned short* pBase, int sizeInWords);
+int BpUpdateWirelessPciConfig (unsigned long pciID, unsigned long* pBase, int sizeInDWords);
+
+int BpGetEthernetMacInfo( PETHERNET_MAC_INFO pEnetInfos, int nNumEnetInfos );
+int BpGet6829PortInfo( unsigned char *portInfo6829 );
+int BpGetDslPhyAfeIds( unsigned long *pulValues );
+int BpGetExtAFEResetGpio( unsigned short *pulValues );
+int BpGetExtAFELDPwrGpio( unsigned short *pulValues );
+int BpGetExtAFELDModeGpio( unsigned short *pulValues );
+
+VOIP_DSP_INFO *BpGetVoipDspConfig( unsigned char dspNum );
+int BpGetVoipLedGpio( unsigned short *pusValue );
+int BpGetVoip1LedGpio( unsigned short *pusValue );
+int BpGetVoip1FailLedGpio( unsigned short *pusValue );
+int BpGetVoip2LedGpio( unsigned short *pusValue );
+int BpGetVoip2FailLedGpio( unsigned short *pusValue );
+int BpGetPotsLedGpio( unsigned short *pusValue );
+int BpGetDectLedGpio( unsigned short *pusValue );
+
+int bpstrcmp(const char *dest,const char *src);
+
+
+#endif /* __ASSEMBLER__ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BOARDPARMS_H */
+
diff --git a/shared/opensource/include/bcm963xx/boardparms_voice.h b/shared/opensource/include/bcm963xx/boardparms_voice.h
new file mode 100755
index 0000000..5d3c7e5
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/boardparms_voice.h
@@ -0,0 +1,392 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/**************************************************************************
+ * File Name  : boardparms_voice.h
+ *
+ * Description: This file contains definitions and function prototypes for
+ *              the BCM63xx voice board parameter access functions.
+ *
+ ***************************************************************************/
+
+#if !defined(_BOARDPARMS_VOICE_H)
+#define _BOARDPARMS_VOICE_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <boardparms.h>
+
+#define SI32261ENABLE    /* Temporary #def until fully supported */
+#define SI32267ENABLE   /* Temporary #def until fully supported */
+
+/* Board string defines */
+
+#define VOICECFG_NOSLIC_STR            "NOSLIC"
+#define VOICECFG_LE88276_STR           "LE88276"
+#define VOICECFG_LE88506_STR           "LE88506"
+#define VOICECFG_LE9530_STR            "LE9530"
+#define VOICECFG_VE890_STR             "VE890"
+#define VOICECFG_SI32178_STR           "SI32178"
+#define VOICECFG_SI3217X_STR           "SI3217X"
+#define VOICECFG_SI3226_STR            "SI3226"
+#define VOICECFG_6328AVNG_LE88276_NTR_STR         "LE88276-NTR"
+#define VOICECFG_6328AVNG_SI32267_STR             "AVNG_SI32267"
+#define VOICECFG_6328AVNG_VE890HV_PARTIAL_STR     "AVNG_VE890HVP"
+#define VOICECFG_6328AVNG_VE890HV_STR             "AVNG_VE890HV"
+
+#define VOICECFG_6328AVNGR_SI32176_STR         "AVNGR_SI32176"
+#define VOICECFG_6328AVNGR_LE89116_STR         "AVNGR_LE89116"
+#define VOICECFG_6328AVNGR_SI3217X_STR         "AVNGR_SI3217X"
+
+#define VOICECFG_6368MVWG_STR                     "MVWG"
+#define VOICECFG_6368MBG_LE88276_STR              "MBG_LE88276"
+#define VOICECFG_6368MBG_LE88506_STR              "MBG_LE88506"
+#define VOICECFG_6368MBG_VE890_STR                "MBG_VE890"
+#define VOICECFG_6368MBG_LE89116_STR              "MBG_LE89116"
+#define VOICECFG_6368MBG_LE89316_STR              "MBG_LE89316"
+#define VOICECFG_6368MBG_SI3217X_STR              "MBG_SI3217X"
+#define VOICECFG_6368MBG_SI32176_STR              "MBG_SI32176"
+#define VOICECFG_6368MBG_SI32178_STR              "MBG_SI32178"
+#define VOICECFG_6368MBG_SI3226_STR               "MBG_SI3226"
+
+#define VOICECFG_6362ADVNGP5_NOSLIC_STR           "ADVNGP5_NOSLIC"
+#define VOICECFG_6362ADVNGP5_SI3217X_STR          "ADVNGP5_SI3217X"
+#define VOICECFG_6362ADVNGP5_SI32176_STR          "ADVNGP5_SI32176"
+#define VOICECFG_6362ADVNGP5_SI32178_STR          "ADVNGP5_SI32178"
+#define VOICECFG_6362ADVNGP5_VE890_STR            "ADVNGP5_VE890"
+#define VOICECFG_6362ADVNGP5_LE89116_STR          "ADVNGP5_LE89116"
+#define VOICECFG_6362ADVNGP5_LE89316_STR          "ADVNGP5_LE89316"
+#define VOICECFG_6362ADVNGP5_LE88506_STR          "ADVNGP5_LE88506"
+#define VOICECFG_6362ADVNGP5_LE88276_STR          "ADVNGP5_LE88276"
+#define VOICECFG_6362ADVNGP5_SI3226_STR           "ADVNGP5_SI3226"
+
+#define VOICECFG_6362ADVNGR_SI3217X_STR           "ADVNGR_SI3217X"
+#define VOICECFG_6362ADVNGR_SI32176_STR           "ADVNGR_SI32176"
+#define VOICECFG_6362ADVNGR_SI32178_STR           "ADVNGR_SI32178"
+#define VOICECFG_6362ADVNGR_SI3217X_NOFXO_STR     "ADVNGR_SI3217XN"
+#define VOICECFG_6362ADVNGR_VE890_STR             "ADVNGR_VE890"
+#define VOICECFG_6362ADVNGR_LE89116_STR           "ADVNGR_LE89116"
+#define VOICECFG_6362ADVNGR_LE89316_STR           "ADVNGR_LE89316"
+#define VOICECFG_6362ADVNGR_LE88506_STR           "ADVNGR_LE88506"
+#define VOICECFG_6362ADVNGR_LE88276_STR           "ADVNGR_LE88276"
+#define VOICECFG_6362ADVNGR_SI3226_STR            "ADVNGR_SI3226"
+#define VOICECFG_6362ADVNGR_SI32261_STR           "ADVNGR_SI32261"
+#define VOICECFG_6362ADVNGR_SI32267_STR           "ADVNGR_SI32267"
+#define VOICECFG_6362ADVNGR_VE890HV_PARTIAL_STR   "ADVNGR_VE890HVP"
+#define VOICECFG_6362ADVNGR_VE890HV_STR           "ADVNGR_VE890HV"
+
+#define VOICECFG_6362ADVNGR2_SI3217X_STR          "ADVNGR2_SI3217X"
+#define VOICECFG_6362ADVNGR2_VE890_STR            "ADVNGR2_VE890"
+#define VOICECFG_6362ADVNGR2_LE88506_STR          "ADVNGR2_LE88506"
+#define VOICECFG_6362ADVNGR2_LE88276_STR          "ADVNGR2_LE88276"
+#define VOICECFG_6362ADVNGR2_SI3226_STR           "ADVNGR2_SI3226"
+
+#define VOICECFG_6368MVNGR_SI3217X_STR            "MVNGR_SI3217X"
+#define VOICECFG_6368MVNGR_SI32176_STR            "MVNGR_SI32176"
+#define VOICECFG_6368MVNGR_SI32178_STR            "MVNGR_SI32178"
+#define VOICECFG_6368MVNGR_SI3217X_NOFXO_STR      "MVNGR_SI3217XN"
+#define VOICECFG_6368MVNGR_VE890_STR              "MVNGR_VE890"
+#define VOICECFG_6368MVNGR_LE89116_STR            "MVNGR_LE89116"
+#define VOICECFG_6368MVNGR_LE89316_STR            "MVNGR_LE89316"
+#define VOICECFG_6368MVNGR_LE88506_STR            "MVNGR_LE88506"
+#define VOICECFG_6368MVNGR_LE88276_STR            "MVNGR_LE88276"
+#define VOICECFG_6368MVNGR_SI3226_STR             "MVNGR_SI3226"
+#define VOICECFG_6368MVNGR_VE890HV_PARTIAL_STR    "MVNGR_VE890HVP"
+#define VOICECFG_6368MVNGR_VE890HV_STR            "MVNGR_VE890HV"
+
+
+/* Maximum number of devices in the system (on the board).
+** Devices can refer to DECT, SLAC/SLIC, or SLAC/DAA combo. */
+#define BP_MAX_VOICE_DEVICES           5 
+
+/* Maximum numbers of channels per SLAC. */
+#define BP_MAX_CHANNELS_PER_DEVICE     2
+
+/* Maximum number of voice channels in the system.
+** This represents the sum of all channels available on the devices in the system */
+#define BP_MAX_VOICE_CHAN              (BP_MAX_VOICE_DEVICES * BP_MAX_CHANNELS_PER_DEVICE)
+
+/* Max number of GPIO pins used for controling PSTN failover relays
+** Note: the number of PSTN failover relays can be larger if multiple
+** relays are controlled by single GPIO */
+#define BP_MAX_RELAY_PINS              2
+
+#define BP_TIMESLOT_INVALID            0xFF
+
+/* General-purpose flag definitions (rename as appropriate) */
+#define BP_FLAG_DSP_APMHAL_ENABLE            (1 << 0)
+#define BP_FLAG_ISI_SUPPORT                  (1 << 1)
+#define BP_FLAG_MODNAME_TESTNAME2            (1 << 2)
+#define BP_FLAG_MODNAME_TESTNAME3            (1 << 3)
+#define BP_FLAG_MODNAME_TESTNAME4            (1 << 4)
+#define BP_FLAG_MODNAME_TESTNAME5            (1 << 5)
+#define BP_FLAG_MODNAME_TESTNAME6            (1 << 6)
+#define BP_FLAG_MODNAME_TESTNAME7            (1 << 7)
+#define BP_FLAG_MODNAME_TESTNAME8            (1 << 8)
+
+/* 
+** Device-specific definitions 
+*/
+typedef enum
+{
+   BP_VD_NONE = -1,
+   BP_VD_IDECT1,  /* Do not move this around, otherwise rebuild dect_driver.bin */
+   BP_VD_EDECT1,  
+   BP_VD_SILABS_3050,
+   BP_VD_SILABS_3215,
+   BP_VD_SILABS_3216,
+   BP_VD_SILABS_3217,
+   BP_VD_SILABS_32176,
+   BP_VD_SILABS_32178,
+   BP_VD_SILABS_3226,
+   BP_VD_SILABS_32261,
+   BP_VD_SILABS_32267,
+   BP_VD_ZARLINK_88010,
+   BP_VD_ZARLINK_88221,
+   BP_VD_ZARLINK_88276,
+   BP_VD_ZARLINK_88506,
+   BP_VD_ZARLINK_89010,
+   BP_VD_ZARLINK_89116,
+   BP_VD_ZARLINK_89316,
+   BP_VD_ZARLINK_9530,
+   BP_VD_ZARLINK_89136,
+   BP_VD_ZARLINK_89336,
+   BP_VD_MAX,
+} BP_VOICE_DEVICE_TYPE;
+
+
+/* 
+** Channel-specific definitions 
+*/
+
+typedef enum
+{
+   BP_VOICE_CHANNEL_ACTIVE,
+   BP_VOICE_CHANNEL_INACTIVE,
+} BP_VOICE_CHANNEL_STATUS;
+
+typedef enum
+{
+   BP_VCTYPE_NONE = -1,
+   BP_VCTYPE_SLIC,
+   BP_VCTYPE_DAA,
+   BP_VCTYPE_DECT
+} BP_VOICE_CHANNEL_TYPE;
+
+typedef enum
+{
+   BP_VOICE_CHANNEL_SAMPLE_SIZE_16BITS,
+   BP_VOICE_CHANNEL_SAMPLE_SIZE_8BITS,
+} BP_VOICE_CHANNEL_SAMPLE_SIZE;
+
+typedef enum
+{
+   BP_VOICE_CHANNEL_NARROWBAND,
+   BP_VOICE_CHANNEL_WIDEBAND,
+} BP_VOICE_CHANNEL_FREQRANGE;
+
+
+typedef enum
+{
+   BP_VOICE_CHANNEL_ENDIAN_BIG,
+   BP_VOICE_CHANNEL_ENDIAN_LITTLE,
+} BP_VOICE_CHANNEL_ENDIAN_MODE;
+
+typedef enum
+{
+   BP_VOICE_CHANNEL_PCMCOMP_MODE_NONE,
+   BP_VOICE_CHANNEL_PCMCOMP_MODE_ALAW,
+   BP_VOICE_CHANNEL_PCMCOMP_MODE_ULAW,
+} BP_VOICE_CHANNEL_PCMCOMP_MODE;
+
+
+typedef struct
+{
+   unsigned int  status;        /* active/inactive */
+   unsigned int  type;          /* SLIC/DAA/DECT */
+   unsigned int  pcmCompMode;   /* u-law/a-law (applicable for 8-bit samples) */
+   unsigned int  freqRange;     /* narrowband/wideband */
+   unsigned int  sampleSize;    /* 8-bit / 16-bit */
+   unsigned int  endianMode;    /* big/little */
+   unsigned int  rxTimeslot;    /* Receive timeslot for the channel */
+   unsigned int  txTimeslot;    /* Sending timeslot for the channel */
+
+} BP_VOICE_CHANNEL;
+
+/* TODO: This structure could possibly be turned into union if needed */
+typedef struct
+{
+   int                  spiDevId;               /* SPI device id */
+   unsigned short       spiGpio;                /* SPI GPIO (if used for SPI control) */
+} BP_VOICE_SPI_CONTROL;
+
+typedef struct
+{
+   unsigned short       relayGpio[BP_MAX_RELAY_PINS];
+} BP_PSTN_RELAY_CONTROL;
+
+typedef struct
+{
+   unsigned short       dectUartGpioTx;
+   unsigned short       dectUartGpioRx;
+} BP_DECT_UART_CONTROL;
+
+typedef struct
+{
+   unsigned int         voiceDeviceType;        /* Specific type of device (Le88276, Si32176, etc.) */
+   BP_VOICE_SPI_CONTROL spiCtrl;                /* SPI control through dedicated SPI pin or GPIO */
+   int                  requiresReset;          /* Does the device requires reset (through GPIO) */
+   unsigned short       resetGpio;              /* Reset GPIO */
+   BP_VOICE_CHANNEL     channel[BP_MAX_CHANNELS_PER_DEVICE];   /* Device channels */
+
+} BP_VOICE_DEVICE;
+
+
+/*
+** Main structure for defining the board parameters and used by boardHal
+** for proper initialization of the DSP and devices (SLACs, DECT, etc.)
+*/
+typedef struct VOICE_BOARD_PARMS
+{
+   char                    szBoardId[BP_BOARD_ID_LEN];   /* board id string */
+   unsigned int            numFxsLines;            /* Number of FXS lines in the system */
+   unsigned int            numFxoLines;            /* Number of FXO lines in the system */
+   unsigned int            numDectLines;           /* Number of DECT lines in the system */
+   unsigned int            numFailoverRelayPins;   /* Number of GPIO pins controling PSTN failover relays */
+   BP_VOICE_DEVICE         voiceDevice[BP_MAX_VOICE_DEVICES];  /* Voice devices in the system */
+   BP_PSTN_RELAY_CONTROL   pstnRelayCtrl;          /* Control for PSTN failover relays */
+   BP_DECT_UART_CONTROL    dectUartControl;        /* Control for external DECT UART */
+   unsigned int            flags;                  /* General-purpose flags */
+} VOICE_BOARD_PARMS, *PVOICE_BOARD_PARMS;
+
+/* --- End of voice-specific structures and enums --- */
+
+int BpGetVoiceParms( char* pszBoardId, VOICE_BOARD_PARMS* voiceParms );
+int BpSetVoiceBoardId( char *pszBoardId );
+int BpGetVoiceBoardId( char *pszBoardId );
+int BpGetVoiceBoardIds( char *pszBoardIds, int nBoardIdsSize );
+
+/* Variable externs */
+
+#if defined(_BCM96328_) || defined(CONFIG_BCM96328)
+
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3226;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_SI32267;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_LE88276_NTR;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV_Partial;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNG_VE890HV;
+
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI32176;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_LE89116;
+extern VOICE_BOARD_PARMS voiceBoard_96328AVNGR_SI3217X;
+
+#endif
+
+#if defined(_BCM96362_) || defined(CONFIG_BCM96362)
+
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_NOSLIC;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89116;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE89316;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32176;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI32178;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_SI3226;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGP5_LE88506; 
+
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32176;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32178;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3217X_NOFXO;   
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89116;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE89316;     
+
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI3226;  
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32261;      
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_SI32267;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HVP;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNgr_VE890HV;
+
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96362ADVNGR2_SI3226;
+
+#endif
+
+#if defined(_BCM96368_) || defined(CONFIG_BCM96368)
+
+extern VOICE_BOARD_PARMS voiceBoard_96368MVWG;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89116;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_LE89316;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32176;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI32178;
+extern VOICE_BOARD_PARMS voiceBoard_96368MBG_SI3226;
+
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32176;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI32178;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3217X_NOFXO;   
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89116;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE89316;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_SI3226; 
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV_Partial;
+extern VOICE_BOARD_PARMS voiceBoard_96368MVNgr_VE890HV;
+
+#endif
+
+
+#if defined(_BCM96816_) || defined(CONFIG_BCM96816)
+
+extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88276;
+extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_SI3226;
+extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE88506;
+extern VOICE_BOARD_PARMS voiceBoard_96816PVWM_LE9530;
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BOARDPARMS_VOICE_H */
+
diff --git a/shared/opensource/include/bcm963xx/fap_mod_size.h b/shared/opensource/include/bcm963xx/fap_mod_size.h
new file mode 100644
index 0000000..03bb799
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/fap_mod_size.h
@@ -0,0 +1,2 @@
+#define FAP_CORE_SIZE 0
+#define FAP_INIT_SIZE 0
diff --git a/shared/opensource/include/bcm963xx/flash_api.h b/shared/opensource/include/bcm963xx/flash_api.h
new file mode 100755
index 0000000..7ac8022
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/flash_api.h
@@ -0,0 +1,90 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL?, available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/***************************************************************************
+ * File Name  : flash_api.h
+ *
+ * Description: This file contains definitions and prototypes for a public
+ *              flash device interface and an internal flash device interface.
+ ***************************************************************************/
+
+#if !defined(_FLASH_API_H)
+#define _FLASH_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Flash definitions. */
+#define FLASH_API_OK                1
+#define FLASH_API_ERROR             -1
+
+#define FLASH_IFC_UNKNOWN           0
+#define FLASH_IFC_PARALLEL          1
+#define FLASH_IFC_SPI               2
+#define FLASH_IFC_HS_SPI            3
+#define FLASH_IFC_NAND              4
+
+#define NAND_REINIT_FLASH           0xffff
+
+/* Public Interface Prototypes. */
+int flash_init(void);
+int flash_sector_erase_int(unsigned short sector);
+int flash_read_buf(unsigned short sector, int offset, unsigned char *buffer,
+    int numbytes);
+int flash_write_buf(unsigned short sector, int offset, unsigned char *buffer,
+    int numbytes);
+int flash_get_numsectors(void);
+int flash_get_sector_size(unsigned short sector);
+unsigned char *flash_get_memptr(unsigned short sector);
+int flash_get_blk(int addr);
+int flash_get_total_size(void);
+int flash_get_flash_type(void);
+void flash_change_flash_type(int type);
+
+/* Internal Flash Device Driver Information. */
+typedef struct flash_device_info_s
+{
+    unsigned short flash_device_id;
+    unsigned short flash_type;
+    char flash_device_name[30];
+
+    int (*fn_flash_sector_erase_int) (unsigned short sector);
+    int (*fn_flash_read_buf) (unsigned short sector, int offset,
+        unsigned char *buffer, int numbytes);
+    int (*fn_flash_write_buf) (unsigned short sector, int offset,
+        unsigned char *buffer, int numbytes);
+    int (*fn_flash_get_numsectors) (void);
+    int (*fn_flash_get_sector_size) (unsigned short sector);
+    unsigned char * (*fn_flash_get_memptr) (unsigned short sector);
+    int (*fn_flash_get_blk) (int addr);
+    int (*fn_flash_get_total_size) (void);
+} flash_device_info_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLASH_API_H */
+
diff --git a/shared/opensource/include/bcm963xx/flash_common.h b/shared/opensource/include/bcm963xx/flash_common.h
new file mode 100755
index 0000000..4fcceca
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/flash_common.h
@@ -0,0 +1,103 @@
+/*
+    Copyright 2000-2010 Broadcom Corporation
+
+    Unless you and Broadcom execute a separate written software license
+    agreement governing use of this software, this software is licensed
+    to you under the terms of the GNU General Public License version 2
+    (the “GPL”), available at http://www.broadcom.com/licenses/GPLv2.php,
+    with the following added to such license:
+
+        As a special exception, the copyright holders of this software give
+        you permission to link this software with independent modules, and to
+        copy and distribute the resulting executable under terms of your
+        choice, provided that you also meet, for each linked independent
+        module, the terms and conditions of the license of that module. 
+        An independent module is a module which is not derived from this
+        software.  The special exception does not apply to any modifications
+        of the software.
+
+    Notwithstanding the above, under no circumstances may you combine this
+    software in any way with any other Broadcom software provided under a
+    license other than the GPL, without Broadcom's express prior written
+    consent.
+*/                       
+
+/*!\file flash_common.h
+ * \brief This file contains definitions and prototypes used by both
+ *        CFE and kernel.
+ *
+ */
+
+#if !defined(_FLASH_COMMON_H)
+#define _FLASH_COMMON_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/** default scratch pad length */
+#define SP_MAX_LEN          (8 * 1024)
+
+
+/** Flash storage address information that is determined by the flash driver.
+ *
+ *  This structure is used by CFE and kernel.
+ */
+typedef struct flashaddrinfo
+{
+    int flash_persistent_start_blk;   /**< primary psi, for config file */
+    int flash_persistent_number_blk;
+    int flash_persistent_length;      /**< in bytes */
+    unsigned long flash_persistent_blk_offset;
+    int flash_scratch_pad_start_blk;  /**< start of scratch pad */
+    int flash_scratch_pad_number_blk;
+    int flash_scratch_pad_length;     /**< in bytes */
+    unsigned long flash_scratch_pad_blk_offset;
+    unsigned long flash_rootfs_start_offset; /**< offset from start of flash to fs+kernel image */
+    int flash_backup_psi_start_blk;  /**< starting block of backup psi. Length is
+                                          the same as primary psi.  
+                                          Start at begining of sector, so offset is always 0.
+                                          No sharing sectors with anybody else. */
+    int flash_backup_psi_number_blk;  /**< The number of sectors for primary and backup
+                                       *   psi may be different due to the irregular
+                                       *   sector sizes at the end of the flash. */
+    int flash_syslog_start_blk;  /**< starting block of persistent syslog. */
+    int flash_syslog_number_blk; /**< number of blocks */
+    int flash_syslog_length;     /**< in bytes, set from CFE, note busybox syslogd uses 16KB buffer.
+                                      Like backup_psi, always start at beginning of sector,
+                                      so offset is 0, and no sharing of sectors. */
+    int flash_meta_start_blk; /**< The first block which is used for meta info such
+                                   as the psi, scratch pad, syslog, backup psi.
+                                   The kernel can use everything above this sector. */
+} FLASH_ADDR_INFO, *PFLASH_ADDR_INFO;
+
+
+/** Fill in the fInfo structure with primary PSI, scratch pad, syslog, secondary PSI info.
+ *
+ * @param nvRam (IN) nvram info.
+ * @param fInfo (OUT) flash addr info that will be filled out by this function.
+ */
+void flash_init_info(const NVRAM_DATA *nvRam, FLASH_ADDR_INFO *fInfo);
+
+
+/** Get the total number of bytes at the bottom of the flash used for PSI, scratch pad, etc.
+ *
+ * Even though this function is returning the number of bytes, it it guaranteed to
+ * return the number of bytes of whole sectors at the end which are in use.
+ * If customer enables backup PSI and persistent syslog, the number of bytes
+ * may go above 64KB. This function replaces the old FLASH_RESERVED_AT_END define.
+ *
+ * @param fInfo (IN) Pointer to flash_addr_info struct.
+ *
+ * @return number of bytes reserved at the end.
+ */
+unsigned int flash_get_reserved_bytes_at_end(const FLASH_ADDR_INFO *fInfo);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLASH_COMMON_H */
+
diff --git a/shared/opensource/include/bcm963xx/gpio_drv.h b/shared/opensource/include/bcm963xx/gpio_drv.h
new file mode 100755
index 0000000..8131153
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/gpio_drv.h
@@ -0,0 +1,40 @@
+/***************************************************************************
+***
+***    Copyright 2008  Hon Hai Precision Ind. Co. Ltd.
+***    All Rights Reserved.
+***    No portions of this material shall be reproduced in any form without the
+***    written permission of Hon Hai Precision Ind. Co. Ltd.
+***
+***    All information contained in this document is Hon Hai Precision Ind.  
+***    Co. Ltd. company private, proprietary, and trade secret property and 
+***    are protected by international intellectual property laws and treaties.
+***
+****************************************************************************/
+
+#ifndef __GPIO_DRV_H__
+#define __GPIO_DRV_H__
+
+#define DEV_GPIO_DRV        "gpio_drv"
+
+#define GPIO_IOCTL_NUM   'W'
+
+#define IOCTL_LAN_LED_STATE       _IOWR(GPIO_IOCTL_NUM, 0, int *)
+#define IOCTL_USB_LED_STATE       _IOWR(GPIO_IOCTL_NUM, 1, int *)
+#define IOCTL_WPS_LED_STATE       _IOWR(GPIO_IOCTL_NUM, 2, int *)
+#define IOCTL_VOIP_LED_OFF        _IOWR(GPIO_IOCTL_NUM, 3, int *)
+#define IOCTL_VOIP_LED_ON         _IOWR(GPIO_IOCTL_NUM, 4, int *)
+#define IOCTL_VOIP_LED_BS         _IOWR(GPIO_IOCTL_NUM, 5, int *)
+#define IOCTL_VOIP_LED_BF         _IOWR(GPIO_IOCTL_NUM, 6, int *)
+#define IOCTL_VOIP_LED_BN         _IOWR(GPIO_IOCTL_NUM, 7, int *)
+#define IOCTL_WAN_LED_STATE       _IOWR(GPIO_IOCTL_NUM, 8, int *)
+#define IOCTL_LAN_VLAN_ID         _IOWR(GPIO_IOCTL_NUM, 9, int *)
+#define IOCTL_WAN_VLAN_ID         _IOWR(GPIO_IOCTL_NUM, 10, int *)
+#define IOCTL_3G_LED_STATE        _IOWR(GPIO_IOCTL_NUM, 11, int *)  //Foxconn added, Neil Chen, 2009/11/2
+/* Foxconn added start Bob, 01/28/2010, for wan detection */
+#define IOCTL_PVC_DET_START       _IOWR(GPIO_IOCTL_NUM, 12, int *)  
+#define IOCTL_PVC_DET_STOP        _IOWR(GPIO_IOCTL_NUM, 13, int *)
+#define IOCTL_PVC_DET_RESULT      _IOWR(GPIO_IOCTL_NUM, 14, int *)
+/* Foxconn added end Bob, 01/28/2010, for wan detection */
+#define IOCTL_LAN_UNTAGGED_VLAN_ID 	_IOWR(GPIO_IOCTL_NUM, 15, int *) /* Foxconn added Bob, 10/25/2010, for tag based vlan */
+
+#endif  /* __GPIO_DRV_H__ */
diff --git a/shared/opensource/include/bcm963xx/wan_det.h b/shared/opensource/include/bcm963xx/wan_det.h
new file mode 100755
index 0000000..d8a5645
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/wan_det.h
@@ -0,0 +1,245 @@
+/***************************************************************************
+***
+***    Copyright 2008  Hon Hai Precision Ind. Co. Ltd.
+***    All Rights Reserved.
+***    No portions of this material shall be reproduced in any form without the
+***    written permission of Hon Hai Precision Ind. Co. Ltd.
+***
+***    All information contained in this document is Hon Hai Precision Ind.  
+***    Co. Ltd. company private, proprietary, and trade secret property and 
+***    are protected by international intellectual property laws and treaties.
+***
+****************************************************************************/
+
+#ifndef __WAN_DET_H__
+#define __WAN_DET_H__
+
+/* Foxconn added start Bob, 01/22/2010 */
+
+#define MAX_SCAN_SERVICE    8
+
+typedef struct _vpivcitable
+{
+    int portId;
+	int vpi;
+	int vci;
+}_VpiVciTable;
+
+
+typedef struct scanResult
+{
+    _VpiVciTable service[MAX_SCAN_SERVICE];
+    _VpiVciTable oam;
+    _VpiVciTable BPDU;
+}SCAN_RESULT;
+/* Foxconn added end Bob, 01/22/2010 */
+
+typedef unsigned short  U16;

+typedef unsigned int    U32;

+typedef unsigned char   U8;

+

+#define PATTERN_ROUTED      0

+#define PATTERN_BRIDGED     1

+

+#define ETHER_TYPE_OFFSET               12

+#define ETHERTYPE_IP              		0x0800

+#define ETHERTYPE_ARP             		0x0806

+#define ETHERTYPE_PPPOE_DISCOVERY 		0x8863

+#define ETHERHEADER_LEN                 14

+

+typedef struct _PacketContent

+{

+    U32 length;

+    U8 *data;

+}PacketContent;

+

+typedef struct _Pattern

+{

+    const char *name;

+    const  PacketContent *payload;

+    int protoType;

+    U16 ethertype;

+    const PacketContent *header;

+    const PacketContent *expected_payload;

+    

+}Pattern;

+

+

+static U8 dhcp_request_bytes[] = {

+

+  // IP header

+  0x45, 0x00, 0x01, 0x48, // version, IHL, TOS, Total Length

+  0x00, 0x04, 0x00, 0x00, // ident, flags, frag off

+  0x9b, 0x11, 0x1e, 0xa2, // TTL, proto, hdr checksum

+  0x00, 0x00, 0x00, 0x00, // source addr

+  0xff, 0xff, 0xff, 0xff, // destination addr

+

+  // UDP header

+  0x00, 0x44, 0x00, 0x43, 0x01, 0x34, 0xe6, 0x9a, 0x01, 0x01, 0x06, 0x00,

+  0xb3, 0x05, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x2b, 0x00, 0x74, 0xb1, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x63, 0x82, 0x53, 0x63, 0x35, 0x01, 0x01, 0x33,

+  0x04, 0x00, 0x00, 0x1c, 0x20, 0x37, 0x07, 0x01, 0x1c, 0x02, 0x03, 0x0f, 0x06, 0x0c, 0xff, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00

+

+};

+

+static PacketContent dhcp_request = { sizeof(dhcp_request_bytes), dhcp_request_bytes 

+};

+    

+static U8 pppoe_padi_bytes[] = {

+  0x11, 0x09, 0x00, 0x00, 0x00, 0x04, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,

+};

+static PacketContent pppoe_padi = { sizeof(pppoe_padi_bytes), pppoe_padi_bytes };

+

+/** Sequence of bytes for a PPP LCP Configure-Request (RFC1661). */

+static U8 ppp_lcp_confreq_bytes[] = {

+    0xc0, 0x21, // LCP

+    0x01,       // Configure Request

+    0x99,       // randomish identifier

+    0x00, 0x04, // length 

+};

+static PacketContent ppp_lcp_confreq = { sizeof(ppp_lcp_confreq_bytes), ppp_lcp_confreq_bytes };

+

+/** Expected response from NULL (aka VcMux) encapsulated PPP/LCP */

+static U8 ppp_lcp_response_bytes[] = { 0xc0, 0x21 };

+static PacketContent ppp_lcp_response = { sizeof(ppp_lcp_response_bytes), ppp_lcp_response_bytes };

+

+/** SNAP/LLC routed */

+static U8 snap_llc_routed_bytes[] = { 0xaa, 0xaa, 3, 0, 0, 0, 8, 0 };

+static PacketContent snap_llc_routed = { sizeof(snap_llc_routed_bytes), snap_llc_routed_bytes };

+

+/** SNAP/LLC bridged, no fcs */

+static U8 snap_llc_bridged_bytes[] = {

+    0xaa, 0xaa, 0x3,       // LLC 

+    0x0,  0x80, 0xc2,      // OUI

+    0x00, 0x07,            // PID

+    0x00, 0x00             // PAD

+ };

+static PacketContent snap_llc_bridged = { sizeof(snap_llc_bridged_bytes), snap_llc_bridged_bytes };

+

+/* foxconn added start Bob, 12/07/2009, ignore BPDU frame */

+/** SNAP/LLC bridged BPDU */

+static U8 snap_llc_bridged_BPDU_bytes[] = {

+    0xaa, 0xaa, 0x3,       // LLC 

+    0x0,  0x80, 0xc2,      // OUI

+    0x00, 0x0e,            // PID

+ };

+ /* foxconn added end Bob, 12/07/2009, ignore BPDU frame */

+

+/** LLC for PPPoA. See RFC2364 section 6. */

+static U8 llc_pppoa_bytes[] = { 0xfe, 0xfe, 0x03, 0xcf };

+static PacketContent llc_pppoa = {

+    sizeof(llc_pppoa_bytes), llc_pppoa_bytes

+};

+

+static U8 vcmux_bridged_bytes[] = { 0, 0 };

+static PacketContent vcmux_bridged = { sizeof(vcmux_bridged_bytes), vcmux_bridged_bytes };

+

+/**

+Patterns to be sent to CO side

+1. PPPoE LLC Bridged

+2. VcMux encapsulated PPPoA

+3. LLC encapsulated PPPoA

+4. RFC1483 SNAP/LLC Routed

+5. RFC1483 VcMux Bridged

+6. PPPoE VCMux Bridged

+7. RFC1483 SNAP/LLC Bridged

+8. RFC1483 VcMux Routed

+*/

+static Pattern patterns[] = 

+{

+    { 

+        "PPPoE LLC Bridged",

+        &pppoe_padi,

+        PATTERN_BRIDGED,

+        ETHERTYPE_PPPOE_DISCOVERY, 

+        &snap_llc_bridged, 

+        NULL

+    },

+    { 

+        "VcMux encapsulated PPPoA",

+        &ppp_lcp_confreq,

+        PATTERN_ROUTED, 

+        0, // no need for etherheader!

+        NULL,

+        &ppp_lcp_response

+    },

+

+    { 

+        "LLC encapsulated PPPoA",

+        &ppp_lcp_confreq,

+        PATTERN_ROUTED, 

+        0, // no need for etherheader!

+        &llc_pppoa,  // encapsulated with PPPoA LLC header

+        NULL

+    },

+

+    /* RFC1483 SNAP/LLC routed */

+    { 

+        "RFC1483 SNAP/LLC Routed",

+        &dhcp_request,

+        PATTERN_ROUTED, 

+        0, 

+        &snap_llc_routed, 

+        NULL

+    },

+

+    /* RFC1483 VC mux bridged */

+    { 

+        "RFC1483 VcMux Bridged",

+        &dhcp_request,

+        PATTERN_BRIDGED, 

+        ETHERTYPE_IP,

+        &vcmux_bridged, 

+        NULL

+    },

+

+    /* PPPOE VCMux Bridged*/

+    {

+        "PPPoE VCMux Bridged",

+        &pppoe_padi,

+        PATTERN_BRIDGED,

+        ETHERTYPE_PPPOE_DISCOVERY,

+        &vcmux_bridged,

+        NULL

+    },

+

+    /* RFC1483 SNAP/LLC bridged */

+    { 

+        "RFC1483 SNAP/LLC Bridged",

+        &dhcp_request,

+        PATTERN_BRIDGED, 

+        ETHERTYPE_IP, 

+        &snap_llc_bridged, 

+        NULL      

+    },

+

+    /* RFC1483 VC mux routed */

+    { 

+        "RFC1483 VcMux Routed",

+        &dhcp_request,

+        PATTERN_ROUTED, 

+        0,

+        NULL, 

+        NULL

+    },

+};
+
+#endif  /* __WAN_DET_H__ */
diff --git a/shared/opensource/include/bcm963xx/wps_led.h b/shared/opensource/include/bcm963xx/wps_led.h
new file mode 100755
index 0000000..69f8682
--- /dev/null
+++ b/shared/opensource/include/bcm963xx/wps_led.h
@@ -0,0 +1,28 @@
+/***************************************************************************
+***
+***    Copyright 2007  Hon Hai Precision Ind. Co. Ltd.
+***    All Rights Reserved.
+***    No portions of this material shall be reproduced in any form without the
+***    written permission of Hon Hai Precision Ind. Co. Ltd.
+***
+***    All information contained in this document is Hon Hai Precision Ind.  
+***    Co. Ltd. company private, proprietary, and trade secret property and 
+***    are protected by international intellectual property laws and treaties.
+***
+****************************************************************************/
+
+#ifndef __WPS_LED_H__
+#define __WPS_LED_H__
+
+#define DEV_GPIO_DRV        "wps_led"
+
+#define WPS_LED_IOCTL_NUM   'W'
+
+#define WPS_LED_BLINK_NORMAL   _IOWR(WPS_LED_IOCTL_NUM, 0, int *)
+#define WPS_LED_BLINK_QUICK    _IOWR(WPS_LED_IOCTL_NUM, 1, int *)
+#define WPS_LED_BLINK_OFF      _IOWR(WPS_LED_IOCTL_NUM, 2, int *)
+#define WPS_LED_CHANGE_GREEN   _IOWR(WPS_LED_IOCTL_NUM, 3, int *)
+#define WPS_LED_CHANGE_AMBER   _IOWR(WPS_LED_IOCTL_NUM, 4, int *)
+#define WPS_LED_BLINK_QUICK2   _IOWR(WPS_LED_IOCTL_NUM, 5, int *)
+
+#endif