diff options
Diffstat (limited to 'target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex')
6 files changed, 0 insertions, 2461 deletions
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt deleted file mode 100644 index 38a9264400..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvCompVer.txt +++ /dev/null @@ -1,4 +0,0 @@ -Global HAL Version: FEROCEON_HAL_3_1_7
-Unit HAL Version: 3.1.4
-Description: This component includes an implementation of the unit HAL drivers
-
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c deleted file mode 100644 index 068aac2bf8..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.c +++ /dev/null @@ -1,1143 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#include "pex/mvPex.h" - -#include "ctrlEnv/mvCtrlEnvLib.h" - -/* defines */ -#ifdef MV_DEBUG -#define DB(x) x -#else -#define DB(x) -#endif - -MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType) -{ - MV_PEX_MODE pexMode; - MV_U32 regVal; - MV_U32 status; - - /* First implement Guideline (GL# PCI Express-2) Wrong Default Value */ - /* to Transmitter Output Current (TXAMP) Relevant for: 88F5181-A1/B0/B1 */ - /* and 88F5281-B0 and above, 88F5182, 88F5082, 88F5181L, 88F6082/L */ - - if ((mvCtrlModelGet() != MV_1281_DEV_ID) && - (mvCtrlModelGet() != MV_6281_DEV_ID) && - (mvCtrlModelGet() != MV_6192_DEV_ID) && - (mvCtrlModelGet() != MV_6190_DEV_ID) && - (mvCtrlModelGet() != MV_6180_DEV_ID) && - (mvCtrlModelGet() != MV_6183_DEV_ID) && - (mvCtrlModelGet() != MV_6183L_DEV_ID) && - (mvCtrlModelGet() != MV_78100_DEV_ID) && - (mvCtrlModelGet() != MV_78200_DEV_ID) && - (mvCtrlModelGet() != MV_76100_DEV_ID) && - (mvCtrlModelGet() != MV_78XX0_DEV_ID)) - { - - /* Read current value of TXAMP */ - MV_REG_WRITE(0x41b00, 0x80820000); /* Write the read command */ - - regVal = MV_REG_READ(0x41b00); /* Extract the data */ - - /* Prepare new data for write */ - regVal &= ~0x7; /* Clear bits [2:0] */ - regVal |= 0x4; /* Set the new value */ - regVal &= ~0x80000000; /* Set "write" command */ - MV_REG_WRITE(0x41b00, regVal); /* Write the write command */ - - } - else - { - /* Implement 1.0V termination GL for 88F1281 device only */ - /* BIT0 - Common mode feedback */ - /* BIT3 - TxBuf, extra drive for 1.0V termination */ - if (mvCtrlModelGet() == MV_1281_DEV_ID) - { - MV_REG_WRITE(0x41b00, 0x80860000); /* Write the read command */ - regVal = MV_REG_READ(0x41b00); /* Extract the data */ - regVal |= (BIT0 | BIT3); - regVal &= ~0x80000000; /* Set "write" command */ - MV_REG_WRITE(0x41b00, regVal); /* Write the write command */ - - MV_REG_WRITE(0x31b00, 0x80860000); /* Write the read command */ - regVal = MV_REG_READ(0x31b00); /* Extract the data */ - regVal |= (BIT0 | BIT3); - regVal &= ~0x80000000; /* Set "write" command */ - MV_REG_WRITE(0x31b00, regVal); /* Write the write command */ - } - } - - if( mvPexModeGet(pexIf, &pexMode) != MV_OK) - { - mvOsPrintf("PEX init ERR. mvPexModeGet failed (pexType=%d)\n",pexMode.pexType); - return MV_ERROR; - } - - /* Check that required PEX type is the one set in reset time */ - if (pexType != pexMode.pexType) - { - /* No Link. Shut down the Phy */ - mvPexPowerDown(pexIf); - mvOsPrintf("PEX init ERR. PEX type sampled mismatch (%d,%d)\n",pexType,pexMode.pexType); - return MV_ERROR; - } - - if (MV_PEX_ROOT_COMPLEX == pexType) - { - mvPexLocalBusNumSet(pexIf, PEX_HOST_BUS_NUM(pexIf)); - mvPexLocalDevNumSet(pexIf, PEX_HOST_DEV_NUM(pexIf)); - - /* Local device master Enable */ - mvPexMasterEnable(pexIf, MV_TRUE); - - /* Local device slave Enable */ - mvPexSlaveEnable(pexIf, mvPexLocalBusNumGet(pexIf), - mvPexLocalDevNumGet(pexIf), MV_TRUE); - /* Interrupt disable */ - status = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND)); - status |= PXSAC_INT_DIS; - MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_STATUS_AND_COMMAND), status); - } - - /* now wait 500 ms to be sure the link is valid (spec compliant) */ - mvOsDelay(500); - /* Check if we have link */ - if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) - { - mvOsPrintf("PEX%d interface detected no Link.\n",pexIf); - return MV_NO_SUCH; - } - - if (MV_PEX_WITDH_X1 == pexMode.pexWidth) - { - mvOsPrintf("PEX%d interface detected Link X1\n",pexIf); - } - else - { - mvOsPrintf("PEX%d interface detected Link X4\n",pexIf); - } - -#ifdef PCIE_VIRTUAL_BRIDGE_SUPPORT - mvPexVrtBrgInit(pexIf); -#endif - return MV_OK; -} - -/******************************************************************************* -* mvPexModeGet - Get Pex Mode -* -* DESCRIPTION: -* -* INPUT: -* pexIf - PEX interface number. -* -* OUTPUT: -* pexMode - Pex mode structure -* -* RETURN: -* MV_OK on success , MV_ERROR otherwise -* -*******************************************************************************/ -MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode) -{ - MV_U32 pexData; - - /* Parameter checking */ - if (PEX_DEFAULT_IF != pexIf) - { - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexModeGet: ERR. Invalid PEX interface %d\n",pexIf); - return MV_ERROR; - } - } - - pexData = MV_REG_READ(PEX_CTRL_REG(pexIf)); - - switch (pexData & PXCR_DEV_TYPE_CTRL_MASK) - { - case PXCR_DEV_TYPE_CTRL_CMPLX: - pexMode->pexType = MV_PEX_ROOT_COMPLEX; - break; - case PXCR_DEV_TYPE_CTRL_POINT: - pexMode->pexType = MV_PEX_END_POINT; - break; - - } - - /* Check if we have link */ - if (MV_REG_READ(PEX_STATUS_REG(pexIf)) & PXSR_DL_DOWN) - { - pexMode->pexLinkUp = MV_FALSE; - - /* If there is no link, the auto negotiation data is worthless */ - pexMode->pexWidth = MV_PEX_WITDH_INVALID; - } - else - { - pexMode->pexLinkUp = MV_TRUE; - - /* We have link. The link width is now valid */ - pexData = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)); - pexMode->pexWidth = ((pexData & PXLCSR_NEG_LNK_WDTH_MASK) >> - PXLCSR_NEG_LNK_WDTH_OFFS); - } - - return MV_OK; -} - - -/* PEX configuration space read write */ - -/******************************************************************************* -* mvPexConfigRead - Read from configuration space -* -* DESCRIPTION: -* This function performs a 32 bit read from PEX configuration space. -* It supports both type 0 and type 1 of Configuration Transactions -* (local and over bridge). In order to read from local bus segment, use -* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -* will result configuration transaction of type 1 (over bridge). -* -* INPUT: -* pexIf - PEX interface number. -* bus - PEX segment bus number. -* dev - PEX device number. -* func - Function number. -* regOffs - Register offset. -* -* OUTPUT: -* None. -* -* RETURN: -* 32bit register data, 0xffffffff on error -* -*******************************************************************************/ -MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, - MV_U32 regOff) -{ -#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) - return mvPexVrtBrgConfigRead (pexIf, bus, dev, func, regOff); -} - -MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, - MV_U32 regOff) -{ -#endif - MV_U32 pexData = 0; - MV_U32 localDev,localBus; - - /* Parameter checking */ - if (PEX_DEFAULT_IF != pexIf) - { - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexConfigRead: ERR. Invalid PEX interface %d\n",pexIf); - return 0xFFFFFFFF; - } - } - - if (dev >= MAX_PEX_DEVICES) - { - DB(mvOsPrintf("mvPexConfigRead: ERR. device number illigal %d\n", dev)); - return 0xFFFFFFFF; - } - - if (func >= MAX_PEX_FUNCS) - { - DB(mvOsPrintf("mvPexConfigRead: ERR. function num illigal %d\n", func)); - return 0xFFFFFFFF; - } - - if (bus >= MAX_PEX_BUSSES) - { - DB(mvOsPrintf("mvPexConfigRead: ERR. bus number illigal %d\n", bus)); - return MV_ERROR; - } - - DB(mvOsPrintf("mvPexConfigRead: pexIf %d, bus %d, dev %d, func %d, regOff 0x%x\n", - pexIf, bus, dev, func, regOff)); - - localDev = mvPexLocalDevNumGet(pexIf); - localBus = mvPexLocalBusNumGet(pexIf); - - /* Speed up the process. In case on no link, return MV_ERROR */ - if ((dev != localDev) || (bus != localBus)) - { - pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - if ((pexData & PXSR_DL_DOWN)) - { - return MV_ERROR; - } - } - - /* in PCI Express we have only one device number */ - /* and this number is the first number we encounter - else that the localDev*/ - /* spec pex define return on config read/write on any device */ - if (bus == localBus) - { - if (localDev == 0) - { - /* if local dev is 0 then the first number we encounter - after 0 is 1 */ - if ((dev != 1)&&(dev != localDev)) - { - return MV_ERROR; - } - } - else - { - /* if local dev is not 0 then the first number we encounter - is 0 */ - - if ((dev != 0)&&(dev != localDev)) - { - return MV_ERROR; - } - } - if(func != 0 ) /* i.e bridge */ - { - return MV_ERROR; - } - } - - - /* Creating PEX address to be passed */ - pexData = (bus << PXCAR_BUS_NUM_OFFS); - pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); - pexData |= (func << PXCAR_FUNC_NUM_OFFS); - pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ - /* extended register space */ - pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> - PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); - - pexData |= PXCAR_CONFIG_EN; - - /* Write the address to the PEX configuration address register */ - MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); - - DB(mvOsPrintf("mvPexConfigRead:address pexData=%x ",pexData)); - - - /* In order to let the PEX controller absorbed the address of the read */ - /* transaction we perform a validity check that the address was written */ - if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) - { - return MV_ERROR; - } - - /* cleaning Master Abort */ - MV_REG_BIT_SET(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), - PXSAC_MABORT); -#if 0 - /* Guideline (GL# PCI Express-1) Erroneous Read Data on Configuration */ - /* This guideline is relevant for all devices except of the following devices: - 88F5281-BO and above, 88F5181L-A0 and above, 88F1281 A0 and above - 88F6183 A0 and above, 88F6183L */ - if ( ( (dev != localDev) || (bus != localBus) ) && - ( - !(MV_5281_DEV_ID == mvCtrlModelGet())&& - !((MV_5181_DEV_ID == mvCtrlModelGet())&& (mvCtrlRevGet() >= MV_5181L_A0_REV))&& - !(MV_1281_DEV_ID == mvCtrlModelGet())&& - !(MV_6183_DEV_ID == mvCtrlModelGet())&& - !(MV_6183L_DEV_ID == mvCtrlModelGet())&& - !(MV_6281_DEV_ID == mvCtrlModelGet())&& - !(MV_6192_DEV_ID == mvCtrlModelGet())&& - !(MV_6190_DEV_ID == mvCtrlModelGet())&& - !(MV_6180_DEV_ID == mvCtrlModelGet())&& - !(MV_78XX0_DEV_ID == mvCtrlModelGet()) - )) - { - - /* PCI-Express configuration read work-around */ - - /* we will use one of the Punit (AHBToMbus) windows to access the xbar - and read the data from there */ - /* - Need to configure the 2 free Punit (AHB to MBus bridge) - address decoding windows: - Configure the flash Window to handle Configuration space requests - for PEX0/1: - 1. write 0x7931/0x7941 to the flash window and the size, - 79-xbar attr (pci cfg), 3/4-xbar target (pex0/1), 1-WinEn - 2. write base to flash window - - Configuration transactions from the CPU should write/read the data - to/from address of the form: - addr[31:28] = 0x5 (for PEX0) or 0x6 (for PEX1) - addr[27:24] = extended register number - addr[23:16] = bus number - addr[15:11] = device number - addr[10:8] = function number - addr[7:0] = register number - */ - - #include "ctrlEnv/sys/mvAhbToMbus.h" - { - MV_U32 winNum; - MV_AHB_TO_MBUS_DEC_WIN originWin; - MV_U32 pciAddr=0; - MV_U32 remapLow=0,remapHigh=0; - - /* - We will use DEV_CS2\Flash window for this workarround - */ - - winNum = mvAhbToMbusWinTargetGet(PEX_CONFIG_RW_WA_TARGET); - - /* save remap values if exist */ - if ((1 == winNum)||(0 == winNum)) - { - remapLow = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum)); - remapHigh = MV_REG_READ(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum)); - - } - - - /* save the original window values */ - mvAhbToMbusWinGet(winNum,&originWin); - - if (PEX_CONFIG_RW_WA_USE_ORIGINAL_WIN_VALUES) - { - /* set the window as xbar window */ - if (pexIf) - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), - (0x7931 | (((originWin.addrWin.size >> 16)-1) ) << 16)); - } - else - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), - (0x7941 | (((originWin.addrWin.size >> 16)-1) ) << 16)); - } - - MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), - originWin.addrWin.baseLow); - - /*pciAddr = originWin.addrWin.baseLow;*/ - pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR( - (MV_U32)originWin.addrWin.baseLow); - - } - else - { - /* set the window as xbar window */ - if (pexIf) - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), - (0x7931 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); - } - else - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_CTRL_REG(winNum), - (0x7941 | (((PEX_CONFIG_RW_WA_SIZE >> 16)-1) ) << 16)); - } - - MV_REG_WRITE(AHB_TO_MBUS_WIN_BASE_REG(winNum), - PEX_CONFIG_RW_WA_BASE); - - pciAddr = (MV_U32)CPU_MEMIO_UNCACHED_ADDR(PEX_CONFIG_RW_WA_BASE); - } - - - /* remap should be as base */ - if ((1 == winNum)||(0 == winNum)) - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),pciAddr); - MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),0); - - } - - /* extended register space */ - pciAddr |= (bus << 16); - pciAddr |= (dev << 11); - pciAddr |= (func << 8); - pciAddr |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ - - pexData = *(MV_U32*)pciAddr; - pexData = MV_32BIT_LE(pexData); /* Data always in LE */ - - /* restore the original window values */ - mvAhbToMbusWinSet(winNum,&originWin); - - /* restore original remap values*/ - if ((1 == winNum)||(0 == winNum)) - { - MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_LOW_REG(winNum),remapLow); - MV_REG_WRITE(AHB_TO_MBUS_WIN_REMAP_HIGH_REG(winNum),remapHigh); - - } - } - } - else -#endif - { - /* Read the Data returned in the PEX Data register */ - pexData = MV_REG_READ(PEX_CFG_DATA_REG(pexIf)); - - } - - DB(mvOsPrintf("mvPexConfigRead: got : %x \n",pexData)); - - return pexData; - -} - -/******************************************************************************* -* mvPexConfigWrite - Write to configuration space -* -* DESCRIPTION: -* This function performs a 32 bit write to PEX configuration space. -* It supports both type 0 and type 1 of Configuration Transactions -* (local and over bridge). In order to write to local bus segment, use -* bus number retrieved from mvPexLocalBusNumGet(). Other bus numbers -* will result configuration transaction of type 1 (over bridge). -* -* INPUT: -* pexIf - PEX interface number. -* bus - PEX segment bus number. -* dev - PEX device number. -* func - Function number. -* regOffs - Register offset. -* data - 32bit data. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, - MV_U32 func, MV_U32 regOff, MV_U32 data) -{ -#if defined(PCIE_VIRTUAL_BRIDGE_SUPPORT) - return mvPexVrtBrgConfigWrite (pexIf, bus, dev, func, regOff, data); -} - -MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, - MV_U32 func, MV_U32 regOff, MV_U32 data) -{ -#endif - MV_U32 pexData = 0; - MV_U32 localDev,localBus; - - /* Parameter checking */ - if (PEX_DEFAULT_IF != pexIf) - { - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexConfigWrite: ERR. Invalid PEX interface %d\n", - pexIf); - return MV_ERROR; - } - } - - if (dev >= MAX_PEX_DEVICES) - { - mvOsPrintf("mvPexConfigWrite: ERR. device number illigal %d\n",dev); - return MV_BAD_PARAM; - } - - if (func >= MAX_PEX_FUNCS) - { - mvOsPrintf("mvPexConfigWrite: ERR. function number illigal %d\n", func); - return MV_ERROR; - } - - if (bus >= MAX_PEX_BUSSES) - { - mvOsPrintf("mvPexConfigWrite: ERR. bus number illigal %d\n", bus); - return MV_ERROR; - } - - - - localDev = mvPexLocalDevNumGet(pexIf); - localBus = mvPexLocalBusNumGet(pexIf); - - - /* in PCI Express we have only one device number other than ourselves*/ - /* and this number is the first number we encounter - else than the localDev that can be any valid dev number*/ - /* pex spec define return on config read/write on any device */ - if (bus == localBus) - { - - if (localDev == 0) - { - /* if local dev is 0 then the first number we encounter - after 0 is 1 */ - if ((dev != 1)&&(dev != localDev)) - { - return MV_ERROR; - } - - } - else - { - /* if local dev is not 0 then the first number we encounter - is 0 */ - - if ((dev != 0)&&(dev != localDev)) - { - return MV_ERROR; - } - } - - - } - - /* if we are not accessing ourselves , then check the link */ - if ((dev != localDev) || (bus != localBus) ) - { - /* workarround */ - /* when no link return MV_ERROR */ - - pexData = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - if ((pexData & PXSR_DL_DOWN)) - { - return MV_ERROR; - } - - } - - pexData =0; - - /* Creating PEX address to be passed */ - pexData |= (bus << PXCAR_BUS_NUM_OFFS); - pexData |= (dev << PXCAR_DEVICE_NUM_OFFS); - pexData |= (func << PXCAR_FUNC_NUM_OFFS); - pexData |= (regOff & PXCAR_REG_NUM_MASK); /* lgacy register space */ - /* extended register space */ - pexData |=(((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> - PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS); - pexData |= PXCAR_CONFIG_EN; - - DB(mvOsPrintf("mvPexConfigWrite: If=%x bus=%x func=%x dev=%x regOff=%x data=%x \n", - pexIf,bus,func,dev,regOff,data,pexData) ); - - /* Write the address to the PEX configuration address register */ - MV_REG_WRITE(PEX_CFG_ADDR_REG(pexIf), pexData); - - /* Clear CPU pipe. Important where CPU can perform OOO execution */ - CPU_PIPE_FLUSH; - - /* In order to let the PEX controller absorbed the address of the read */ - /* transaction we perform a validity check that the address was written */ - if(pexData != MV_REG_READ(PEX_CFG_ADDR_REG(pexIf))) - { - return MV_ERROR; - } - - /* Write the Data passed to the PEX Data register */ - MV_REG_WRITE(PEX_CFG_DATA_REG(pexIf), data); - - return MV_OK; - -} - -/******************************************************************************* -* mvPexMasterEnable - Enable/disale PEX interface master transactions. -* -* DESCRIPTION: -* This function performs read modified write to PEX command status -* (offset 0x4) to set/reset bit 2. After this bit is set, the PEX -* master is allowed to gain ownership on the bus, otherwise it is -* incapable to do so. -* -* INPUT: -* pexIf - PEX interface number. -* enable - Enable/disable parameter. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable) -{ - MV_U32 pexCommandStatus; - MV_U32 localBus; - MV_U32 localDev; - - /* Parameter checking */ - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexMasterEnable: ERR. Invalid PEX interface %d\n", pexIf); - return MV_ERROR; - } - - localBus = mvPexLocalBusNumGet(pexIf); - localDev = mvPexLocalDevNumGet(pexIf); - - pexCommandStatus = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, - PEX_STATUS_AND_COMMAND)); - - - if (MV_TRUE == enable) - { - pexCommandStatus |= PXSAC_MASTER_EN; - } - else - { - pexCommandStatus &= ~PXSAC_MASTER_EN; - } - - - MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf,PEX_STATUS_AND_COMMAND), - pexCommandStatus); - - return MV_OK; -} - - -/******************************************************************************* -* mvPexSlaveEnable - Enable/disale PEX interface slave transactions. -* -* DESCRIPTION: -* This function performs read modified write to PEX command status -* (offset 0x4) to set/reset bit 0 and 1. After those bits are set, -* the PEX slave is allowed to respond to PEX IO space access (bit 0) -* and PEX memory space access (bit 1). -* -* INPUT: -* pexIf - PEX interface number. -* dev - PEX device number. -* enable - Enable/disable parameter. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_BAD_PARAM for bad parameters ,MV_ERROR on error ! otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable) -{ - MV_U32 pexCommandStatus; - MV_U32 RegOffs; - - /* Parameter checking */ - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexSlaveEnable: ERR. Invalid PEX interface %d\n", pexIf); - return MV_BAD_PARAM; - } - if (dev >= MAX_PEX_DEVICES) - { - mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", dev); - return MV_BAD_PARAM; - - } - - - RegOffs = PEX_STATUS_AND_COMMAND; - - pexCommandStatus = mvPexConfigRead(pexIf, bus, dev, 0, RegOffs); - - if (MV_TRUE == enable) - { - pexCommandStatus |= (PXSAC_IO_EN | PXSAC_MEM_EN); - } - else - { - pexCommandStatus &= ~(PXSAC_IO_EN | PXSAC_MEM_EN); - } - - mvPexConfigWrite(pexIf, bus, dev, 0, RegOffs, pexCommandStatus); - - return MV_OK; - -} - -/******************************************************************************* -* mvPexLocalBusNumSet - Set PEX interface local bus number. -* -* DESCRIPTION: -* This function sets given PEX interface its local bus number. -* Note: In case the PEX interface is PEX-X, the information is read-only. -* -* INPUT: -* pexIf - PEX interface number. -* busNum - Bus number. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_NOT_ALLOWED in case PEX interface is PEX-X. -* MV_BAD_PARAM on bad parameters , -* otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum) -{ - MV_U32 pexStatus; - MV_U32 localBus; - MV_U32 localDev; - - - /* Parameter checking */ - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexLocalBusNumSet: ERR. Invalid PEX interface %d\n",pexIf); - return MV_BAD_PARAM; - } - if (busNum >= MAX_PEX_BUSSES) - { - mvOsPrintf("mvPexLocalBusNumSet: ERR. bus number illigal %d\n", busNum); - return MV_ERROR; - - } - - localBus = mvPexLocalBusNumGet(pexIf); - localDev = mvPexLocalDevNumGet(pexIf); - - - - pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - pexStatus &= ~PXSR_PEX_BUS_NUM_MASK; - - pexStatus |= (busNum << PXSR_PEX_BUS_NUM_OFFS) & PXSR_PEX_BUS_NUM_MASK; - - MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); - - - return MV_OK; -} - - -/******************************************************************************* -* mvPexLocalBusNumGet - Get PEX interface local bus number. -* -* DESCRIPTION: -* This function gets the local bus number of a given PEX interface. -* -* INPUT: -* pexIf - PEX interface number. -* -* OUTPUT: -* None. -* -* RETURN: -* Local bus number.0xffffffff on Error -* -*******************************************************************************/ -MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf) -{ - MV_U32 pexStatus; - - /* Parameter checking */ - if (PEX_DEFAULT_IF != pexIf) - { - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexLocalBusNumGet: ERR. Invalid PEX interface %d\n",pexIf); - return 0xFFFFFFFF; - } - } - - - pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - pexStatus &= PXSR_PEX_BUS_NUM_MASK; - - return (pexStatus >> PXSR_PEX_BUS_NUM_OFFS); - -} - - -/******************************************************************************* -* mvPexLocalDevNumSet - Set PEX interface local device number. -* -* DESCRIPTION: -* This function sets given PEX interface its local device number. -* Note: In case the PEX interface is PEX-X, the information is read-only. -* -* INPUT: -* pexIf - PEX interface number. -* devNum - Device number. -* -* OUTPUT: -* None. -* -* RETURN: -* MV_NOT_ALLOWED in case PEX interface is PEX-X. -* MV_BAD_PARAM on bad parameters , -* otherwise MV_OK -* -*******************************************************************************/ -MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum) -{ - MV_U32 pexStatus; - MV_U32 localBus; - MV_U32 localDev; - - /* Parameter checking */ - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexLocalDevNumSet: ERR. Invalid PEX interface %d\n",pexIf); - return MV_BAD_PARAM; - } - if (devNum >= MAX_PEX_DEVICES) - { - mvOsPrintf("mvPexLocalDevNumSet: ERR. device number illigal %d\n", - devNum); - return MV_BAD_PARAM; - - } - - localBus = mvPexLocalBusNumGet(pexIf); - localDev = mvPexLocalDevNumGet(pexIf); - - - pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - pexStatus &= ~PXSR_PEX_DEV_NUM_MASK; - - pexStatus |= (devNum << PXSR_PEX_DEV_NUM_OFFS) & PXSR_PEX_DEV_NUM_MASK; - - MV_REG_WRITE(PEX_STATUS_REG(pexIf), pexStatus); - - - return MV_OK; -} - -/******************************************************************************* -* mvPexLocalDevNumGet - Get PEX interface local device number. -* -* DESCRIPTION: -* This function gets the local device number of a given PEX interface. -* -* INPUT: -* pexIf - PEX interface number. -* -* OUTPUT: -* None. -* -* RETURN: -* Local device number. 0xffffffff on Error -* -*******************************************************************************/ -MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf) -{ - MV_U32 pexStatus; - - /* Parameter checking */ - - if (PEX_DEFAULT_IF != pexIf) - { - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexLocalDevNumGet: ERR. Invalid PEX interface %d\n", - pexIf); - return 0xFFFFFFFF; - } - } - - pexStatus = MV_REG_READ(PEX_STATUS_REG(pexIf)); - - pexStatus &= PXSR_PEX_DEV_NUM_MASK; - - return (pexStatus >> PXSR_PEX_DEV_NUM_OFFS); -} - -MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value) -{ - - MV_U32 regAddr; - if (pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexPhyRegRead: ERR. Invalid PEX interface %d\n", pexIf); - return; - } - regAddr = (BIT31 | ((regOffset & 0x3fff) << 16)); - MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); - *value = MV_REG_READ(PEX_PHY_ACCESS_REG(pexIf)); -} - - -MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value) -{ - - MV_U32 regAddr; - if(pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexPhyRegWrite: ERR. Invalid PEX interface %d\n", pexIf); - return; - } - regAddr = (((regOffset & 0x3fff) << 16) | value); - MV_REG_WRITE(PEX_PHY_ACCESS_REG(pexIf), regAddr); -} - -/******************************************************************************* -* mvPexActiveStateLinkPMEnable -* -* DESCRIPTION: -* Enable Active Link State Power Management -* -* INPUT: -* pexIf - PEX interface number. -* enable - MV_TRUE to enable ASPM, MV_FALSE to disable. -* -* OUTPUT: -* None -* -* RETURN: -* MV_OK on success , MV_ERROR otherwise -* -*******************************************************************************/ -MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable) -{ - MV_U32 reg; - - if(pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexActiveStateLinkPMEnable: ERR. Invalid PEX interface %d\n", pexIf); - return MV_ERROR; - } - - reg = MV_REG_READ(PEX_PWR_MNG_EXT_REG(pexIf)) & ~PXPMER_L1_ASPM_EN_MASK; - if(enable == MV_TRUE) - reg |= PXPMER_L1_ASPM_EN_MASK; - MV_REG_WRITE(PEX_PWR_MNG_EXT_REG(pexIf), reg); - - /* Enable / Disable L0/1 entry */ - reg = MV_REG_READ(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG)) - & ~PXLCSR_ASPM_CNT_MASK; - if(enable == MV_TRUE) - reg |= PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP; - MV_REG_WRITE(PEX_CFG_DIRECT_ACCESS(pexIf, PEX_LINK_CTRL_STAT_REG), reg); - - return MV_OK; -} - - -/******************************************************************************* -* mvPexForceX1 -* -* DESCRIPTION: -* shut down lanes 1-3 if recognize that attached to an x1 end-point -* INPUT: -* pexIf - PEX interface number. -* -* OUTPUT: -* None -* -* RETURN: -* MV_OK on success , MV_ERROR otherwise -* -*******************************************************************************/ -MV_U32 mvPexForceX1(MV_U32 pexIf) -{ - MV_U32 regData = 0; - if(pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexForceX1: ERR. Invalid PEX interface %d\n", pexIf); - return MV_BAD_PARAM; - } - - regData = MV_REG_READ(PEX_CTRL_REG(pexIf)) & ~(PXCR_CONF_LINK_MASK) ; - regData |= PXCR_CONF_LINK_X1; - - MV_REG_WRITE(PEX_CTRL_REG(pexIf), regData); - return MV_OK; -} - -MV_BOOL mvPexIsPowerUp(MV_U32 pexIf) -{ - if(pexIf >= mvCtrlPexMaxIfGet()) - { - mvOsPrintf("mvPexIsPowerUp: ERR. Invalid PEX interface %d\n", pexIf); - return MV_FALSE; - } - return mvCtrlPwrClckGet(PEX_UNIT_ID, pexIf); -} - - -MV_VOID mvPexPowerDown(MV_U32 pexIf) -{ - if ( (mvCtrlModelGet() == MV_78XX0_DEV_ID) || - (mvCtrlModelGet() == MV_76100_DEV_ID) || - (mvCtrlModelGet() == MV_78100_DEV_ID) || - (mvCtrlModelGet() == MV_78200_DEV_ID) ) - { - mvCtrlPwrClckSet(PEX_UNIT_ID, pexIf, MV_FALSE); - } - else - { - MV_REG_WRITE((0x41B00 -(pexIf)*0x10000), 0x20800087); - } -} - - - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h deleted file mode 100644 index d8f1cdd9f9..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPex.h +++ /dev/null @@ -1,168 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCPEXH -#define __INCPEXH - -#include "mvCommon.h" -#include "mvOs.h" -#include "pex/mvPexRegs.h" -#include "ctrlEnv/mvCtrlEnvSpec.h" - - - -/* NOTE not supported in this driver:*/ - - -/* defines */ -/* The number of supported PEX interfaces depend on Marvell controller */ -/* device number. This device number ID is located on the PEX unit */ -/* configuration header. This creates a loop where calling PEX */ -/* configuration read/write routine results a call to get PEX configuration */ -/* information etc. This macro defines a default PEX interface. This PEX */ -/* interface is sure to exist. */ -#define PEX_DEFAULT_IF 0 - - -/* typedefs */ -/* The Marvell controller supports both root complex and end point devices */ -/* This enumeration describes the PEX type. */ -typedef enum _mvPexType -{ - MV_PEX_ROOT_COMPLEX, /* root complex device */ - MV_PEX_END_POINT /* end point device */ -}MV_PEX_TYPE; - -typedef enum _mvPexWidth -{ - MV_PEX_WITDH_X1 = 1, - MV_PEX_WITDH_X2, - MV_PEX_WITDH_X3, - MV_PEX_WITDH_X4, - MV_PEX_WITDH_INVALID -}MV_PEX_WIDTH; - -/* PEX Bar attributes */ -typedef struct _mvPexMode -{ - MV_PEX_TYPE pexType; - MV_PEX_WIDTH pexWidth; - MV_BOOL pexLinkUp; -}MV_PEX_MODE; - - - -/* Global Functions prototypes */ -/* mvPexInit - Initialize PEX interfaces*/ -MV_STATUS mvPexHalInit(MV_U32 pexIf, MV_PEX_TYPE pexType); - -/* mvPexModeGet - Get Pex If mode */ -MV_U32 mvPexModeGet(MV_U32 pexIf,MV_PEX_MODE *pexMode); - -/* mvPexConfigRead - Read from configuration space */ -MV_U32 mvPexConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, - MV_U32 func,MV_U32 regOff); - -/* mvPexConfigWrite - Write to configuration space */ -MV_STATUS mvPexConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, - MV_U32 func, MV_U32 regOff, MV_U32 data); - -/* mvPexMasterEnable - Enable/disale PEX interface master transactions.*/ -MV_STATUS mvPexMasterEnable(MV_U32 pexIf, MV_BOOL enable); - -/* mvPexSlaveEnable - Enable/disale PEX interface slave transactions.*/ -MV_STATUS mvPexSlaveEnable(MV_U32 pexIf, MV_U32 bus,MV_U32 dev, MV_BOOL enable); - -/* mvPexLocalBusNumSet - Set PEX interface local bus number.*/ -MV_STATUS mvPexLocalBusNumSet(MV_U32 pexIf, MV_U32 busNum); - -/* mvPexLocalBusNumGet - Get PEX interface local bus number.*/ -MV_U32 mvPexLocalBusNumGet(MV_U32 pexIf); - -/* mvPexLocalDevNumSet - Set PEX interface local device number.*/ -MV_STATUS mvPexLocalDevNumSet(MV_U32 pexIf, MV_U32 devNum); - -/* mvPexLocalDevNumGet - Get PEX interface local device number.*/ -MV_U32 mvPexLocalDevNumGet(MV_U32 pexIf); -/* mvPexForceX1 - Force PEX interface to X1 mode. */ -MV_U32 mvPexForceX1(MV_U32 pexIf); - -/* mvPexIsPowerUp - Is PEX interface Power up? */ -MV_BOOL mvPexIsPowerUp(MV_U32 pexIf); - -/* mvPexPowerDown - Power Down */ -MV_VOID mvPexPowerDown(MV_U32 pexIf); - -/* mvPexPowerUp - Power Up */ -MV_VOID mvPexPowerUp(MV_U32 pexIf); - -/* mvPexPhyRegRead - Pex phy read */ -MV_VOID mvPexPhyRegRead(MV_U32 pexIf, MV_U32 regOffset, MV_U16 *value); - -/* mvPexPhyRegWrite - Pex phy write */ -MV_VOID mvPexPhyRegWrite(MV_U32 pexIf, MV_U32 regOffset, MV_U16 value); - -MV_STATUS mvPexActiveStateLinkPMEnable(MV_U32 pexIf, MV_BOOL enable); - -#endif /* #ifndef __INCPEXH */ diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h deleted file mode 100644 index 8ac1698364..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvPexRegs.h +++ /dev/null @@ -1,751 +0,0 @@ -/******************************************************************************* -Copyright (C) Marvell International Ltd. and its affiliates - -This software file (the "File") is owned and distributed by Marvell -International Ltd. and/or its affiliates ("Marvell") under the following -alternative licensing terms. Once you have made an election to distribute the -File under one of the following license alternatives, please (i) delete this -introductory statement regarding license alternatives, (ii) delete the two -license alternatives that you have not elected to use and (iii) preserve the -Marvell copyright notice above. - -******************************************************************************** -Marvell Commercial License Option - -If you received this File from Marvell and you have entered into a commercial -license agreement (a "Commercial License") with Marvell, the File is licensed -to you under the terms of the applicable Commercial License. - -******************************************************************************** -Marvell GPL License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File in accordance with the terms and conditions of the General -Public License Version 2, June 1991 (the "GPL License"), a copy of which is -available along with the File in the license.txt file or by writing to the Free -Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or -on the worldwide web at http://www.gnu.org/licenses/gpl.txt. - -THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED -WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY -DISCLAIMED. The GPL License provides additional details about this warranty -disclaimer. -******************************************************************************** -Marvell BSD License Option - -If you received this File from Marvell, you may opt to use, redistribute and/or -modify this File under the following licensing terms. -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - - * Redistributions of source code must retain the above copyright notice, - this list of conditions and the following disclaimer. - - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - * Neither the name of Marvell nor the names of its contributors may be - used to endorse or promote products derived from this software without - specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - -*******************************************************************************/ - -#ifndef __INCPEXREGSH -#define __INCPEXREGSH - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* defines */ -#define MAX_PEX_DEVICES 32 -#define MAX_PEX_FUNCS 8 -#define MAX_PEX_BUSSES 256 - - - -/*********************************************************/ -/* PCI Express Configuration Cycles Generation Registers */ -/*********************************************************/ - -#define PEX_CFG_ADDR_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18F8) -#define PEX_CFG_DATA_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x18FC) -#define PEX_PHY_ACCESS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1B00) -/* PCI Express Configuration Address Register */ -/* PEX_CFG_ADDR_REG (PXCAR)*/ - -#define PXCAR_REG_NUM_OFFS 2 -#define PXCAR_REG_NUM_MAX 0x3F -#define PXCAR_REG_NUM_MASK (PXCAR_REG_NUM_MAX << PXCAR_REG_NUM_OFFS) -#define PXCAR_FUNC_NUM_OFFS 8 -#define PXCAR_FUNC_NUM_MAX 0x7 -#define PXCAR_FUNC_NUM_MASK (PXCAR_FUNC_NUM_MAX << PXCAR_FUNC_NUM_OFFS) -#define PXCAR_DEVICE_NUM_OFFS 11 -#define PXCAR_DEVICE_NUM_MAX 0x1F -#define PXCAR_DEVICE_NUM_MASK (PXCAR_DEVICE_NUM_MAX << PXCAR_DEVICE_NUM_OFFS) -#define PXCAR_BUS_NUM_OFFS 16 -#define PXCAR_BUS_NUM_MAX 0xFF -#define PXCAR_BUS_NUM_MASK (PXCAR_BUS_NUM_MAX << PXCAR_BUS_NUM_OFFS) -#define PXCAR_EXT_REG_NUM_OFFS 24 -#define PXCAR_EXT_REG_NUM_MAX 0xF - -/* in pci express register address is now the legacy register address (8 bits) -with the new extended register address (more 4 bits) , below is the mask of -the upper 4 bits of the full register address */ - -#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -#define PXCAR_EXT_REG_NUM_MASK (PXCAR_EXT_REG_NUM_MAX << PXCAR_EXT_REG_NUM_OFFS) -#define PXCAR_CONFIG_EN BIT31 - -#define PXCAR_REAL_EXT_REG_NUM_OFFS 8 -#define PXCAR_REAL_EXT_REG_NUM_MASK (0xF << PXCAR_REAL_EXT_REG_NUM_OFFS) - -/* The traditional PCI spec defined 6-bit field to describe register offset.*/ -/* The new PCI Express extend the register offset by an extra 4-bits. */ -/* The below macro assign 10-bit register offset into the apprpreate */ -/* fields in the CFG_ADDR_REG */ -#define PXCAR_REG_OFFS_SET(regOffs) \ - ( (regOff & PXCAR_REG_NUM_MASK) | \ - ( ((regOff & PXCAR_REAL_EXT_REG_NUM_MASK) >> PXCAR_REAL_EXT_REG_NUM_OFFS) << PXCAR_EXT_REG_NUM_OFFS) ) - -/***********************************/ -/* PCI Express Interrupt registers */ -/***********************************/ -#define PEX_CAUSE_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1900) -#define PEX_MASK_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1910) - -#define PXICR_TX_REQ_IN_DLDOWN_ERR BIT0 /* Transmit request while field */ - /* <DLDown> of the PCI Express */ -/* PCI Express Interrupt Cause */ -/* PEX_INT_CAUSE_REG (PXICR)*/ -/* PEX_INT_MASK_REG*/ -/* -NOTE:All bits except bits[27:24] are Read/Write Clear only. A cause bit sets -upon an error event occurrence. A write of 0 clears the bit. A write of 1 has -no affect. Bits[24:27} are set and cleared upon reception of interrupt -emulation messages. - -Mask bit per cause bit. If a bit is set to 1, the corresponding event is -enabled. Mask does not affect setting of the Interrupt Cause register bits; -it only affects the assertion of the interrupt .*/ - - -#define PXICR_MDIS_CAUSE BIT1 /* Attempt to generate PCI transaction - while master is disabled */ -#define PXICR_ERR_WRTO_REG_CAUSE BIT3 /* Erroneous write attempt to - PCI Express internal register*/ -#define PXICR_HIT_DFLT_WIN_ERR BIT4 /* Hit Default Window Error */ -#define PXICR_RX_RAM_PAR_ERR BIT6 /* Rx RAM Parity Error */ -#define PXICR_TX_RAM_PAR_ERR BIT7 /* Tx RAM Parity Error */ -#define PXICR_COR_ERR_DET BIT8 /* Correctable Error Detected*/ -#define PXICR_NF_ERR_DET BIT9 /* Non-Fatal Error Detected*/ -#define PXICR_FERR_DET BIT10 /* Fatal Error Detected*/ -#define PXICR_DSTATE_CHANGE BIT11 /* Dstate Change Indication*/ -#define PXICR_BIST BIT12 /* PCI-Express BIST activated*/ -#define PXICR_FLW_CTRL_PROT BIT14 /* Flow Control Protocol Error */ - -#define PXICR_RCV_UR_CA_ERR BIT15 /* Received UR or CA status. */ -#define PXICR_RCV_ERR_FATAL BIT16 /* Received ERR_FATAL message.*/ -#define PXICR_RCV_ERR_NON_FATAL BIT17 /* Received ERR_NONFATAL message*/ -#define PXICR_RCV_ERR_COR BIT18 /* Received ERR_COR message.*/ -#define PXICR_RCV_CRS BIT19 /* Received CRS completion status*/ -#define PXICR_SLV_HOT_RESET BIT20 /* Received Hot Reset Indication*/ -#define PXICR_SLV_DIS_LINK BIT21 /* Slave Disable Link Indication*/ -#define PXICR_SLV_LB BIT22 /* Slave Loopback Indication*/ -#define PXICR_LINK_FAIL BIT23 /* Link Failure indication.*/ -#define PXICR_RCV_INTA BIT24 /* IntA status.*/ -#define PXICR_RCV_INTB BIT25 /* IntB status.*/ -#define PXICR_RCV_INTC BIT26 /* IntC status.*/ -#define PXICR_RCV_INTD BIT27 /* IntD status.*/ -#define PXICR_RCV_PM_PME BIT28 /* Received PM_PME message. */ - - -/********************************************/ -/* PCI Express Control and Status Registers */ -/********************************************/ -#define PEX_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A00) -#define PEX_STATUS_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A04) -#define PEX_COMPLT_TMEOUT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A10) -#define PEX_PWR_MNG_EXT_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A18) -#define PEX_FLOW_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A20) -#define PEX_ACK_TMR_4X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A30) -#define PEX_ACK_TMR_1X_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A40) -#define PEX_TL_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1AB0) - - -#define PEX_RAM_PARITY_CTRL_REG(pexIf) ((PEX_IF_BASE(pexIf)) + 0x1A50) -/* PCI Express Control Register */ -/* PEX_CTRL_REG (PXCR) */ - -#define PXCR_CONF_LINK_OFFS 0 -#define PXCR_CONF_LINK_MASK (1 << PXCR_CONF_LINK_OFFS) -#define PXCR_CONF_LINK_X4 (0 << PXCR_CONF_LINK_OFFS) -#define PXCR_CONF_LINK_X1 (1 << PXCR_CONF_LINK_OFFS) -#define PXCR_DEV_TYPE_CTRL_OFFS 1 /*PCI ExpressDevice Type Control*/ -#define PXCR_DEV_TYPE_CTRL_MASK BIT1 -#define PXCR_DEV_TYPE_CTRL_CMPLX (1 << PXCR_DEV_TYPE_CTRL_OFFS) -#define PXCR_DEV_TYPE_CTRL_POINT (0 << PXCR_DEV_TYPE_CTRL_OFFS) -#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping - to Memory Space Enable */ - -#define PXCR_CFG_MAP_TO_MEM_EN BIT2 /* Configuration Header Mapping - to Memory Space Enable*/ - -#define PXCR_RSRV1_OFFS 5 -#define PXCR_RSRV1_MASK (0x7 << PXCR_RSRV1_OFFS) -#define PXCR_RSRV1_VAL (0x0 << PXCR_RSRV1_OFFS) - -#define PXCR_CONF_MAX_OUTSTND_OFFS 8 /*Maximum outstanding NP requests as a master*/ -#define PXCR_CONF_MAX_OUTSTND_MASK (0x3 << PXCR_CONF_MAX_OUTSTND_OFFS) - - -#define PXCR_CONF_NFTS_OFFS 16 /*number of FTS Ordered-Sets*/ -#define PXCR_CONF_NFTS_MASK (0xff << PXCR_CONF_NFTS_OFFS) - -#define PXCR_CONF_MSTR_HOT_RESET BIT24 /*Master Hot-Reset.*/ -#define PXCR_CONF_MSTR_LB BIT26 /* Master Loopback */ -#define PXCR_CONF_MSTR_DIS_SCRMB BIT27 /* Master Disable Scrambling*/ -#define PXCR_CONF_DIRECT_DIS_SCRMB BIT28 /* Direct Disable Scrambling*/ - -/* PCI Express Status Register */ -/* PEX_STATUS_REG (PXSR) */ - -#define PXSR_DL_DOWN BIT0 /* DL_Down indication.*/ - -#define PXSR_PEX_BUS_NUM_OFFS 8 /* Bus Number Indication */ -#define PXSR_PEX_BUS_NUM_MASK (0xff << PXSR_PEX_BUS_NUM_OFFS) - -#define PXSR_PEX_DEV_NUM_OFFS 16 /* Device Number Indication */ -#define PXSR_PEX_DEV_NUM_MASK (0x1f << PXSR_PEX_DEV_NUM_OFFS) - -#define PXSR_PEX_SLV_HOT_RESET BIT24 /* Slave Hot Reset Indication*/ -#define PXSR_PEX_SLV_DIS_LINK BIT25 /* Slave Disable Link Indication*/ -#define PXSR_PEX_SLV_LB BIT26 /* Slave Loopback Indication*/ -#define PXSR_PEX_SLV_DIS_SCRMB BIT27 /* Slave Disable Scrambling Indication*/ - - -/* PCI Express Completion Timeout Register */ -/* PEX_COMPLT_TMEOUT_REG (PXCTR)*/ - -#define PXCTR_CMP_TO_THRSHLD_OFFS 0 /* Completion Timeout Threshold */ -#define PXCTR_CMP_TO_THRSHLD_MASK (0xffff << PXCTR_CMP_TO_THRSHLD_OFFS) - -/* PCI Express Power Management Extended Register */ -/* PEX_PWR_MNG_EXT_REG (PXPMER) */ - -#define PXPMER_L1_ASPM_EN_OFFS 1 -#define PXPMER_L1_ASPM_EN_MASK (0x1 << PXPMER_L1_ASPM_EN_OFFS) - -/* PCI Express Flow Control Register */ -/* PEX_FLOW_CTRL_REG (PXFCR)*/ - -#define PXFCR_PH_INIT_FC_OFFS 0 /*Posted Headers Flow Control Credit - Initial Value.*/ -#define PXFCR_PH_INIT_FC_MASK (0xff << PXFCR_PH_INIT_FC_OFFS) - - -#define PXFCR_NPH_INIT_FC_OFFS 8 /* Classified Non-Posted Headers - Flow Control Credit Initial Value*/ -#define PXFCR_NPH_INIT_FC_MASK (0xff << PXFCR_NPH_INIT_FC_OFFS) - -#define PXFCR_CH_INIT_FC_OFFS 16 /* Completion Headers Flow Control - Credit Initial Value Infinite*/ - -#define PXFCR_CH_INIT_FC_MASK (0xff << PXFCR_CH_INIT_FC_OFFS) - -#define PXFCR_FC_UPDATE_TO_OFFS 24 /* Flow Control Update Timeout */ -#define PXFCR_FC_UPDATE_TO_MASK (0xff << PXFCR_FC_UPDATE_TO_OFFS) - -/* PCI Express Acknowledge Timers (4X) Register */ -/* PEX_ACK_TMR_4X_REG (PXAT4R) */ -#define PXAT1R_ACK_LAT_TOX4_OFFS 0 /* Ack Latency Timer Timeout Value */ -#define PXAT1R_ACK_LAT_TOX4_MASK (0xffff << PXAT4R_ACK_LAT_TOX1_OFFS) -#define PXAT1R_ACK_RPLY_TOX4_OFFS 16 /* Ack Replay Timer Timeout Value */ -#define PXAT1R_ACK_RPLY_TOX4_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) - -/* PCI Express Acknowledge Timers (1X) Register */ -/* PEX_ACK_TMR_1X_REG (PXAT1R) */ - -#define PXAT1R_ACK_LAT_TOX1_OFFS 0 /* Acknowledge Latency Timer Timeout - Value for 1X Link*/ -#define PXAT1R_ACK_LAT_TOX1_MASK (0xffff << PXAT1R_ACK_LAT_TOX1_OFFS) - -#define PXAT1R_ACK_RPLY_TOX1_OFFS 16 /* Acknowledge Replay Timer Timeout - Value for 1X*/ -#define PXAT1R_ACK_RPLY_TOX1_MASK (0xffff << PXAT1R_ACK_RPLY_TOX1_OFFS) - - -/* PCI Express TL Control Register */ -/* PEX_TL_CTRL_REG (PXTCR) */ - -#define PXTCR_TX_CMP_BUFF_NO_OFFS 8 /*Number of completion buffers in Tx*/ -#define PXTCR_TX_CMP_BUFF_NO_MASK (0xf << PXTCR_TX_CMP_BUFF_NO_OFFS) - -/* PCI Express Debug MAC Control Register */ -/* PEX_DEBUG_MAC_CTRL_REG (PXDMCR) */ - -#define PXDMCR_LINKUP BIT4 - - - -/**********************************************/ -/* PCI Express Configuration Header Registers */ -/**********************************************/ -#define PEX_CFG_DIRECT_ACCESS(pexIf,cfgReg) ((PEX_IF_BASE(pexIf)) + (cfgReg)) - -#define PEX_DEVICE_AND_VENDOR_ID 0x000 -#define PEX_STATUS_AND_COMMAND 0x004 -#define PEX_CLASS_CODE_AND_REVISION_ID 0x008 -#define PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE 0x00C -#define PEX_MEMORY_BAR_BASE_ADDR(barNum) (0x010 + ((barNum) << 2)) -#define PEX_MV_BAR_BASE(barNum) (0x010 + (barNum) * 8) -#define PEX_MV_BAR_BASE_HIGH(barNum) (0x014 + (barNum) * 8) -#define PEX_BAR0_INTER_REG 0x010 -#define PEX_BAR0_INTER_REG_HIGH 0x014 -#define PEX_BAR1_REG 0x018 -#define PEX_BAR1_REG_HIGH 0x01C -#define PEX_BAR2_REG 0x020 -#define PEX_BAR2_REG_HIGH 0x024 - -#define PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID 0x02C -#define PEX_EXPANSION_ROM_BASE_ADDR_REG 0x030 -#define PEX_CAPABILTY_LIST_POINTER 0x034 -#define PEX_INTERRUPT_PIN_AND_LINE 0x03C - -/* capability list */ -#define PEX_POWER_MNG_CAPABILITY 0x040 -#define PEX_POWER_MNG_STATUS_CONTROL 0x044 - -#define PEX_MSI_MESSAGE_CONTROL 0x050 -#define PEX_MSI_MESSAGE_ADDR 0x054 -#define PEX_MSI_MESSAGE_HIGH_ADDR 0x058 -#define PEX_MSI_MESSAGE_DATA 0x05C - -#define PEX_CAPABILITY_REG 0x60 -#define PEX_DEV_CAPABILITY_REG 0x64 -#define PEX_DEV_CTRL_STAT_REG 0x68 -#define PEX_LINK_CAPABILITY_REG 0x6C -#define PEX_LINK_CTRL_STAT_REG 0x70 - -#define PEX_ADV_ERR_RPRT_HDR_TRGT_REG 0x100 -#define PEX_UNCORRECT_ERR_STAT_REG 0x104 -#define PEX_UNCORRECT_ERR_MASK_REG 0x108 -#define PEX_UNCORRECT_ERR_SERVITY_REG 0x10C -#define PEX_CORRECT_ERR_STAT_REG 0x110 -#define PEX_CORRECT_ERR_MASK_REG 0x114 -#define PEX_ADV_ERR_CAPABILITY_CTRL_REG 0x118 -#define PEX_HDR_LOG_FIRST_DWORD_REG 0x11C -#define PEX_HDR_LOG_SECOND_DWORD_REG 0x120 -#define PEX_HDR_LOG_THIRD_DWORD_REG 0x124 -#define PEX_HDR_LOG_FOURTH_DWORD_REG 0x128 - - - -/* PCI Express Device and Vendor ID Register*/ -/*PEX_DEVICE_AND_VENDOR_ID (PXDAVI)*/ - -#define PXDAVI_VEN_ID_OFFS 0 /* Vendor ID */ -#define PXDAVI_VEN_ID_MASK (0xffff << PXDAVI_VEN_ID_OFFS) - -#define PXDAVI_DEV_ID_OFFS 16 /* Device ID */ -#define PXDAVI_DEV_ID_MASK (0xffff << PXDAVI_DEV_ID_OFFS) - - -/* PCI Express Command and Status Register*/ -/*PEX_STATUS_AND_COMMAND (PXSAC)*/ - -#define PXSAC_IO_EN BIT0 /* IO Enable */ -#define PXSAC_MEM_EN BIT1 /* Memory Enable */ -#define PXSAC_MASTER_EN BIT2 /* Master Enable */ -#define PXSAC_PERR_EN BIT6 /* Parity Errors Respond Enable */ -#define PXSAC_SERR_EN BIT8 /* Ability to assert SERR# line */ -#define PXSAC_INT_DIS BIT10 /* Interrupt Disable */ -#define PXSAC_INT_STAT BIT19 /* Interrupt Status */ -#define PXSAC_CAP_LIST BIT20 /* Capability List Support */ -#define PXSAC_MAS_DATA_PERR BIT24 /* Master Data Parity Error */ -#define PXSAC_SLAVE_TABORT BIT27 /* Signalled Target Abort */ -#define PXSAC_RT_ABORT BIT28 /* Recieved Target Abort */ -#define PXSAC_MABORT BIT29 /* Recieved Master Abort */ -#define PXSAC_SYSERR BIT30 /* Signalled system error */ -#define PXSAC_DET_PARERR BIT31 /* Detect Parity Error */ - - -/* PCI Express Class Code and Revision ID Register*/ -/*PEX_CLASS_CODE_AND_REVISION_ID (PXCCARI)*/ - -#define PXCCARI_REVID_OFFS 0 /* Revision ID */ -#define PXCCARI_REVID_MASK (0xff << PXCCARI_REVID_OFFS) - -#define PXCCARI_FULL_CLASS_OFFS 8 /* Full Class Code */ -#define PXCCARI_FULL_CLASS_MASK (0xffffff << PXCCARI_FULL_CLASS_OFFS) - -#define PXCCARI_PROGIF_OFFS 8 /* Prog .I/F*/ -#define PXCCARI_PROGIF_MASK (0xff << PXCCARI_PROGIF_OFFS) - -#define PXCCARI_SUB_CLASS_OFFS 16 /* Sub Class*/ -#define PXCCARI_SUB_CLASS_MASK (0xff << PXCCARI_SUB_CLASS_OFFS) - -#define PXCCARI_BASE_CLASS_OFFS 24 /* Base Class*/ -#define PXCCARI_BASE_CLASS_MASK (0xff << PXCCARI_BASE_CLASS_OFFS) - - -/* PCI Express BIST, Header Type and Cache Line Size Register*/ -/*PEX_BIST_HDR_TYPE_LAT_TMR_CACHE_LINE (PXBHTLTCL)*/ - -#define PXBHTLTCL_CACHELINE_OFFS 0 /* Specifies the cache line size */ -#define PXBHTLTCL_CACHELINE_MASK (0xff << PXBHTLTCL_CACHELINE_OFFS) - -#define PXBHTLTCL_HEADTYPE_FULL_OFFS 16 /* Full Header Type */ -#define PXBHTLTCL_HEADTYPE_FULL_MASK (0xff << PXBHTLTCL_HEADTYPE_FULL_OFFS) - -#define PXBHTLTCL_MULTI_FUNC BIT23 /* Multi/Single function */ - -#define PXBHTLTCL_HEADER_OFFS 16 /* Header type */ -#define PXBHTLTCL_HEADER_MASK (0x7f << PXBHTLTCL_HEADER_OFFS) -#define PXBHTLTCL_HEADER_STANDARD (0x0 << PXBHTLTCL_HEADER_OFFS) -#define PXBHTLTCL_HEADER_PCI2PCI_BRIDGE (0x1 << PXBHTLTCL_HEADER_OFFS) - - -#define PXBHTLTCL_BISTCOMP_OFFS 24 /* BIST Completion Code */ -#define PXBHTLTCL_BISTCOMP_MASK (0xf << PXBHTLTCL_BISTCOMP_OFFS) - -#define PXBHTLTCL_BISTACT BIT30 /* BIST Activate bit */ -#define PXBHTLTCL_BISTCAP BIT31 /* BIST Capable Bit */ -#define PXBHTLTCL_BISTCAP_OFFS 31 -#define PXBHTLTCL_BISTCAP_MASK BIT31 -#define PXBHTLTCL_BISTCAP_VAL 0 - - -/* PCI Express Subsystem Device and Vendor ID */ -/*PEX_SUBSYS_ID_AND_SUBSYS_VENDOR_ID (PXSIASVI)*/ - -#define PXSIASVI_VENID_OFFS 0 /* Subsystem Manufacturer Vendor ID Number */ -#define PXSIASVI_VENID_MASK (0xffff << PXSIASVI_VENID_OFFS) - -#define PXSIASVI_DEVID_OFFS 16 /* Subsystem Device ID Number */ -#define PXSIASVI_DEVID_MASK (0xffff << PXSIASVI_DEVID_OFFS) - - -/* PCI Express Capability List Pointer Register*/ -/*PEX_CAPABILTY_LIST_POINTER (PXCLP)*/ - -#define PXCLP_CAPPTR_OFFS 0 /* Capability List Pointer */ -#define PXCLP_CAPPTR_MASK (0xff << PXCLP_CAPPTR_OFFS) - -/* PCI Express Interrupt Pin and Line Register */ -/*PEX_INTERRUPT_PIN_AND_LINE (PXIPAL)*/ - -#define PXIPAL_INTLINE_OFFS 0 /* Interrupt line (IRQ) */ -#define PXIPAL_INTLINE_MASK (0xff << PXIPAL_INTLINE_OFFS) - -#define PXIPAL_INTPIN_OFFS 8 /* interrupt pin (A,B,C,D) */ -#define PXIPAL_INTPIN_MASK (0xff << PXIPAL_INTPIN_OFFS) - - -/* PCI Express Power Management Capability Header Register*/ -/*PEX_POWER_MNG_CAPABILITY (PXPMC)*/ - -#define PXPMC_CAP_ID_OFFS 0 /* Capability ID */ -#define PXPMC_CAP_ID_MASK (0xff << PXPMC_CAP_ID_OFFS) - -#define PXPMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -#define PXPMC_NEXT_PTR_MASK (0xff << PXPMC_NEXT_PTR_OFFS) - -#define PXPMC_PMC_VER_OFFS 16 /* PCI Power Management Capability Version*/ -#define PXPMC_PMC_VER_MASK (0x7 << PXPMC_PMC_VER_OFFS) - -#define PXPMC_DSI BIT21/* Device Specific Initialization */ - -#define PXPMC_AUX_CUR_OFFS 22 /* Auxiliary Current Requirements */ -#define PXPMC_AUX_CUR_MASK (0x7 << PXPMC_AUX_CUR_OFFS) - -#define PXPMC_D1_SUP BIT25 /* D1 Power Management support*/ - -#define PXPMC_D2_SUP BIT26 /* D2 Power Management support*/ - -#define PXPMC_PME_SUP_OFFS 27 /* PM Event generation support*/ -#define PXPMC_PME_SUP_MASK (0x1f << PXPMC_PME_SUP_OFFS) - -/* PCI Express Power Management Control and Status Register*/ -/*PEX_POWER_MNG_STATUS_CONTROL (PXPMSC)*/ - -#define PXPMSC_PM_STATE_OFFS 0 /* Power State */ -#define PXPMSC_PM_STATE_MASK (0x3 << PXPMSC_PM_STATE_OFFS) -#define PXPMSC_PM_STATE_D0 (0x0 << PXPMSC_PM_STATE_OFFS) -#define PXPMSC_PM_STATE_D1 (0x1 << PXPMSC_PM_STATE_OFFS) -#define PXPMSC_PM_STATE_D2 (0x2 << PXPMSC_PM_STATE_OFFS) -#define PXPMSC_PM_STATE_D3 (0x3 << PXPMSC_PM_STATE_OFFS) - -#define PXPMSC_PME_EN BIT8/* PM_PME Message Generation Enable */ - -#define PXPMSC_PM_DATA_SEL_OFFS 9 /* Data Select*/ -#define PXPMSC_PM_DATA_SEL_MASK (0xf << PXPMSC_PM_DATA_SEL_OFFS) - -#define PXPMSC_PM_DATA_SCALE_OFFS 13 /* Data Scale */ -#define PXPMSC_PM_DATA_SCALE_MASK (0x3 << PXPMSC_PM_DATA_SCALE_OFFS) - -#define PXPMSC_PME_STAT BIT15/* PME Status */ - -#define PXPMSC_PM_DATA_OFFS 24 /* State Data */ -#define PXPMSC_PM_DATA_MASK (0xff << PXPMSC_PM_DATA_OFFS) - - -/* PCI Express MSI Message Control Register*/ -/*PEX_MSI_MESSAGE_CONTROL (PXMMC)*/ - -#define PXMMC_CAP_ID_OFFS 0 /* Capability ID */ -#define PXMMC_CAP_ID_MASK (0xff << PXMMC_CAP_ID_OFFS) - -#define PXMMC_NEXT_PTR_OFFS 8 /* Next Item Pointer */ -#define PXMMC_NEXT_PTR_MASK (0xff << PXMMC_NEXT_PTR_OFFS) - -#define PXMMC_MSI_EN BIT18 /* MSI Enable */ - -#define PXMMC_MULTI_CAP_OFFS 17 /* Multiple Message Capable */ -#define PXMMC_MULTI_CAP_MASK (0x7 << PXMMC_MULTI_CAP_OFFS) - -#define PXMMC_MULTI_EN_OFFS 20 /* Multiple Messages Enable */ -#define PXMMC_MULTI_EN_MASK (0x7 << PXMMC_MULTI_EN_OFFS) - -#define PXMMC_ADDR64 BIT23 /* 64-bit Addressing Capable */ - - -/* PCI Express MSI Message Address Register*/ -/*PEX_MSI_MESSAGE_ADDR (PXMMA)*/ - -#define PXMMA_MSI_ADDR_OFFS 2 /* Message Address corresponds to - Address[31:2] of the MSI MWr TLP*/ -#define PXMMA_MSI_ADDR_MASK (0x3fffffff << PXMMA_MSI_ADDR_OFFS) - - -/* PCI Express MSI Message Address (High) Register */ -/*PEX_MSI_MESSAGE_HIGH_ADDR (PXMMHA)*/ - -#define PXMMA_MSI_ADDR_H_OFFS 0 /* Message Upper Address corresponds to - Address[63:32] of the MSI MWr TLP*/ -#define PXMMA_MSI_ADDR_H_MASK (0xffffffff << PXMMA_MSI_ADDR_H_OFFS ) - - -/* PCI Express MSI Message Data Register*/ -/*PEX_MSI_MESSAGE_DATA (PXMMD)*/ - -#define PXMMD_MSI_DATA_OFFS 0 /* Message Data */ -#define PXMMD_MSI_DATA_MASK (0xffff << PXMMD_MSI_DATA_OFFS ) - - -/* PCI Express Capability Register*/ -/*PEX_CAPABILITY_REG (PXCR)*/ - -#define PXCR_CAP_ID_OFFS 0 /* Capability ID*/ -#define PXCR_CAP_ID_MASK (0xff << PXCR_CAP_ID_OFFS) - -#define PXCR_NEXT_PTR_OFFS 8 /* Next Item Pointer*/ -#define PXCR_NEXT_PTR_MASK (0xff << PXCR_NEXT_PTR_OFFS) - -#define PXCR_CAP_VER_OFFS 16 /* Capability Version*/ -#define PXCR_CAP_VER_MASK (0xf << PXCR_CAP_VER_OFFS) - -#define PXCR_DEV_TYPE_OFFS 20 /* Device/Port Type*/ -#define PXCR_DEV_TYPE_MASK (0xf << PXCR_DEV_TYPE_OFFS) - -#define PXCR_SLOT_IMP BIT24 /* Slot Implemented*/ - -#define PXCR_INT_MSG_NUM_OFFS 25 /* Interrupt Message Number*/ -#define PXCR_INT_MSG_NUM_MASK (0x1f << PXCR_INT_MSG_NUM_OFFS) - - -/* PCI Express Device Capabilities Register */ -/*PEX_DEV_CAPABILITY_REG (PXDCR)*/ - -#define PXDCR_MAX_PLD_SIZE_SUP_OFFS 0 /* Maximum Payload Size Supported*/ -#define PXDCR_MAX_PLD_SIZE_SUP_MASK (0x7 << PXDCR_MAX_PLD_SIZE_SUP_OFFS) - -#define PXDCR_EP_L0S_ACC_LAT_OFFS 6/* Endpoint L0s Acceptable Latency*/ -#define PXDCR_EP_L0S_ACC_LAT_MASK (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L0S_ACC_LAT_OFFS) -#define PXDCR_EP_L0S_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L0S_ACC_LAT_OFFS) - -#define PXDCR_EP_L1_ACC_LAT_OFFS 9 /* Endpoint L1 Acceptable Latency*/ -#define PXDCR_EP_L1_ACC_LAT_MASK (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXDCR_EP_L1_ACC_LAT_4US_MORE (0x7 << PXDCR_EP_L1_ACC_LAT_OFFS) - - -#define PXDCR_ATT_BUT_PRS_OFFS 12 /* Attention Button Present*/ -#define PXDCR_ATT_BUT_PRS_MASK BIT12 -#define PXDCR_ATT_BUT_PRS_IMPLEMENTED BIT12 - -#define PXDCR_ATT_IND_PRS_OFFS 13 /* Attention Indicator Present*/ -#define PXDCR_ATT_IND_PRS_MASK BIT13 -#define PXDCR_ATT_IND_PRS_IMPLEMENTED BIT13 - -#define PXDCR_PWR_IND_PRS_OFFS 14/* Power Indicator Present*/ -#define PXDCR_PWR_IND_PRS_MASK BIT14 -#define PXDCR_PWR_IND_PRS_IMPLEMENTED BIT14 - -#define PXDCR_CAP_SPL_VAL_OFFS 18 /*Captured Slot Power Limit - Value*/ -#define PXDCR_CAP_SPL_VAL_MASK (0xff << PXDCR_CAP_SPL_VAL_OFFS) - -#define PXDCR_CAP_SP_LSCL_OFFS 26 /* Captured Slot Power Limit - Scale */ -#define PXDCR_CAP_SP_LSCL_MASK (0x3 << PXDCR_CAP_SP_LSCL_OFFS) - -/* PCI Express Device Control Status Register */ -/*PEX_DEV_CTRL_STAT_REG (PXDCSR)*/ - -#define PXDCSR_COR_ERR_REP_EN BIT0 /* Correctable Error Reporting Enable*/ -#define PXDCSR_NF_ERR_REP_EN BIT1 /* Non-Fatal Error Reporting Enable*/ -#define PXDCSR_F_ERR_REP_EN BIT2 /* Fatal Error Reporting Enable*/ -#define PXDCSR_UR_REP_EN BIT3 /* Unsupported Request (UR) - Reporting Enable*/ -#define PXDCSR_EN_RO BIT4 /* Enable Relaxed Ordering*/ - -#define PXDCSR_MAX_PLD_SZ_OFFS 5 /* Maximum Payload Size*/ -#define PXDCSR_MAX_PLD_SZ_MASK (0x7 << PXDCSR_MAX_PLD_SZ_OFFS) -#define PXDCSR_MAX_PLD_SZ_128B (0x0 << PXDCSR_MAX_PLD_SZ_OFFS) -#define PXDCSR_EN_NS BIT11 /* Enable No Snoop*/ - -#define PXDCSR_MAX_RD_RQ_SZ_OFFS 12 /* Maximum Read Request Size*/ -#define PXDCSR_MAX_RD_RQ_SZ_MASK (0x7 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_128B (0x0 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_256B (0x1 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_512B (0x2 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_1KB (0x3 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_2KB (0x4 << PXDCSR_MAX_RD_RQ_SZ_OFFS) -#define PXDCSR_MAX_RD_RQ_SZ_4KB (0x5 << PXDCSR_MAX_RD_RQ_SZ_OFFS) - -#define PXDCSR_COR_ERR_DET BIT16 /* Correctable Error Detected*/ -#define PXDCSR_NF_ERR_DET BIT17 /* Non-Fatal Error Detected.*/ -#define PXDCSR_F_ERR_DET BIT18 /* Fatal Error Detected.*/ -#define PXDCSR_UR_DET BIT19 /* Unsupported Request Detected */ -#define PXDCSR_AUX_PWR_DET BIT20 /* Reserved*/ - -#define PXDCSR_TRANS_PEND_OFFS 21 /* Transactions Pending*/ -#define PXDCSR_TRANS_PEND_MASK BIT21 -#define PXDCSR_TRANS_PEND_NOT_COMPLETED (0x1 << PXDCSR_TRANS_PEND_OFFS) - - -/* PCI Express Link Capabilities Register*/ -/*PEX_LINK_CAPABILITY_REG (PXLCR)*/ - -#define PXLCR_MAX_LINK_SPD_OFFS 0 /* Maximum Link Speed*/ -#define PXLCR_MAX_LINK_SPD_MASK (0xf << PXLCR_MAX_LINK_SPD_OFFS) - -#define PXLCR_MAX_LNK_WDTH_OFFS 3 /* Maximum Link Width*/ -#define PXLCR_MAX_LNK_WDTH_MASK (0x3f << PXLCR_MAX_LNK_WDTH_OFFS) - -#define PXLCR_ASPM_SUP_OFFS 10 /* Active State Link PM Support*/ -#define PXLCR_ASPM_SUP_MASK (0x3 << PXLCR_ASPM_SUP_OFFS) - -#define PXLCR_L0S_EXT_LAT_OFFS 12 /* L0s Exit Latency*/ -#define PXLCR_L0S_EXT_LAT_MASK (0x7 << PXLCR_L0S_EXT_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_64NS_LESS (0x0 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_64NS_128NS (0x1 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_128NS_256NS (0x2 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_256NS_512NS (0x3 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_512NS_1US (0x4 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_1US_2US (0x5 << PXDCR_EP_L1_ACC_LAT_OFFS) -#define PXLCR_L0S_EXT_LAT_2US_4US (0x6 << PXDCR_EP_L1_ACC_LAT_OFFS) - -#define PXLCR_POR_TNUM_OFFS 24 /* Port Number */ -#define PXLCR_POR_TNUM_MASK (0xff << PXLCR_POR_TNUM_OFFS) - -/* PCI Express Link Control Status Register */ -/*PEX_LINK_CTRL_STAT_REG (PXLCSR)*/ - -#define PXLCSR_ASPM_CNT_OFFS 0 /* Active State Link PM Control */ -#define PXLCSR_ASPM_CNT_MASK (0x3 << PXLCSR_ASPM_CNT_OFFS) -#define PXLCSR_ASPM_CNT_DISABLED (0x0 << PXLCSR_ASPM_CNT_OFFS) -#define PXLCSR_ASPM_CNT_L0S_ENT_SUPP (0x1 << PXLCSR_ASPM_CNT_OFFS) -#define PXLCSR_ASPM_CNT_L1S_ENT_SUPP (0x2 << PXLCSR_ASPM_CNT_OFFS) -#define PXLCSR_ASPM_CNT_L0S_L1S_ENT_SUPP (0x3 << PXLCSR_ASPM_CNT_OFFS) - -#define PXLCSR_RCB_OFFS 3 /* Read Completion Boundary */ -#define PXLCSR_RCB_MASK BIT3 -#define PXLCSR_RCB_64B (0 << PXLCSR_RCB_OFFS) -#define PXLCSR_RCB_128B (1 << PXLCSR_RCB_OFFS) - -#define PXLCSR_LNK_DIS BIT4 /* Link Disable */ -#define PXLCSR_RETRN_LNK BIT5 /* Retrain Link */ -#define PXLCSR_CMN_CLK_CFG BIT6 /* Common Clock Configuration */ -#define PXLCSR_EXTD_SNC BIT7 /* Extended Sync */ - -#define PXLCSR_LNK_SPD_OFFS 16 /* Link Speed */ -#define PXLCSR_LNK_SPD_MASK (0xf << PXLCSR_LNK_SPD_OFFS) - -#define PXLCSR_NEG_LNK_WDTH_OFFS 20 /* Negotiated Link Width */ -#define PXLCSR_NEG_LNK_WDTH_MASK (0x3f << PXLCSR_NEG_LNK_WDTH_OFFS) -#define PXLCSR_NEG_LNK_WDTH_X1 (0x1 << PXLCSR_NEG_LNK_WDTH_OFFS) - -#define PXLCSR_LNK_TRN BIT27 /* Link Training */ - -#define PXLCSR_SLT_CLK_CFG_OFFS 28 /* Slot Clock Configuration */ -#define PXLCSR_SLT_CLK_CFG_MASK BIT28 -#define PXLCSR_SLT_CLK_CFG_INDPNT (0x0 << PXLCSR_SLT_CLK_CFG_OFFS) -#define PXLCSR_SLT_CLK_CFG_REF (0x1 << PXLCSR_SLT_CLK_CFG_OFFS) - -/* PCI Express Advanced Error Report Header Register */ -/*PEX_ADV_ERR_RPRT_HDR_TRGT_REG (PXAERHTR)*/ - -/* PCI Express Uncorrectable Error Status Register*/ -/*PEX_UNCORRECT_ERR_STAT_REG (PXUESR)*/ - -/* PCI Express Uncorrectable Error Mask Register */ -/*PEX_UNCORRECT_ERR_MASK_REG (PXUEMR)*/ - -/* PCI Express Uncorrectable Error Severity Register */ -/*PEX_UNCORRECT_ERR_SERVITY_REG (PXUESR)*/ - -/* PCI Express Correctable Error Status Register */ -/*PEX_CORRECT_ERR_STAT_REG (PXCESR)*/ - -/* PCI Express Correctable Error Mask Register */ -/*PEX_CORRECT_ERR_MASK_REG (PXCEMR)*/ - -/* PCI Express Advanced Error Capability and Control Register*/ -/*PEX_ADV_ERR_CAPABILITY_CTRL_REG (PXAECCR)*/ - -/* PCI Express Header Log First DWORD Register*/ -/*PEX_HDR_LOG_FIRST_DWORD_REG (PXHLFDR)*/ - -/* PCI Express Header Log Second DWORD Register*/ -/*PEX_HDR_LOG_SECOND_DWORD_REG (PXHLSDR)*/ - -/* PCI Express Header Log Third DWORD Register*/ -/*PEX_HDR_LOG_THIRD_DWORD_REG (PXHLTDR)*/ - -/* PCI Express Header Log Fourth DWORD Register*/ -/*PEX_HDR_LOG_FOURTH_DWORD_REG (PXHLFDR)*/ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* #ifndef __INCPEXREGSH */ - - diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c deleted file mode 100644 index 19c871ae4c..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.c +++ /dev/null @@ -1,313 +0,0 @@ -/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "mvPex.h"
-
-//#define MV_DEBUG
-/* defines */
-#ifdef MV_DEBUG
- #define DB(x) x
-#else
- #define DB(x)
-#endif
-
-/* locals */
-typedef struct
-{
- MV_U32 data;
- MV_U32 mask;
-}PEX_HEADER_DATA;
-
-/* local function forwad decleration */
-MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
- MV_U32 regOff);
-MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data);
-void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev);
-
-
-PEX_HEADER_DATA configHdr[16] =
-{
-{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */
-{0x00100007, 0x0000ffff}, /*[status register, command register] */
-{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */
-{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */
-{0x00000000, 0x00000000}, /*[base address 0] */
-{0x00000000, 0x00000000}, /*[base address 1] */
-{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */
-{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */
-{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */
-{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */
-{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */
-{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */
-{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */
-{0x00000000, 0x00000000}, /*[reserved, capability pointer] */
-{0x00000000, 0x00000000}, /*[expansion ROM base address] */
-{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */
-};
-
-
-#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \
- (data & configHdr[offset/4].mask))
-#define HEADER_READ(offset) configHdr[offset/4].data
-
-/*******************************************************************************
-* mvVrtBrgPexInit - Initialize PEX interfaces
-*
-* DESCRIPTION:
-*
-* This function is responsible of intialization of the Pex Interface , It
-* configure the Pex Bars and Windows in the following manner:
-*
-* Assumptions :
-* Bar0 is always internal registers bar
-* Bar1 is always the DRAM bar
-* Bar2 is always the Device bar
-*
-* 1) Sets the Internal registers bar base by obtaining the base from
-* the CPU Interface
-* 2) Sets the DRAM bar base and size by getting the base and size from
-* the CPU Interface when the size is the sum of all enabled DRAM
-* chip selects and the base is the base of CS0 .
-* 3) Sets the Device bar base and size by getting these values from the
-* CPU Interface when the base is the base of the lowest base of the
-* Device chip selects, and the
-*
-*
-* INPUT:
-*
-* pexIf - PEX interface number.
-*
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
-*
-*******************************************************************************/
-MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf)
-{
- /* reset PEX tree to recover previous U-boot/Boot configurations */
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
-
-
- resetPexConfig(pexIf, localBus, 1);
- return MV_OK;
-}
-
-
-MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
- MV_U32 regOff)
-{
-
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
- MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
- MV_U32 val;
- if(bus == localBus)
- {
- if(dev > 1)
- {
-/* on the local device allow only device #0 & #1 */
- return 0xffffffff;
- }
- else
- if (dev == localDev)
- {
- /* read the memory controller registers */
- return mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
- }
- else
- {
- /* access the virtual brg header */
- return HEADER_READ(regOff);
- }
- }
- else
- if(bus == (localBus + 1))
- {
- /* access the device behind the virtual bridge */
- if((dev == localDev) || (dev > 1))
- {
- return 0xffffffff;
- }
- else
- {
- /* access the device behind the virtual bridge, in this case
- * change the bus number to the local bus number in order to
- * generate type 0 config cycle
- */
- mvPexLocalBusNumSet(pexIf, bus);
- mvPexLocalDevNumSet(pexIf, 1);
- val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff);
- mvPexLocalBusNumSet(pexIf, localBus);
- mvPexLocalDevNumSet(pexIf, localDev);
- return val;
- }
- }
- /* for all other devices use the HW function to get the
- * requested registers
- */
- mvPexLocalDevNumSet(pexIf, 1);
- val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
- mvPexLocalDevNumSet(pexIf, localDev);
- return val;
-}
-
-
-MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data)
-{
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
- MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
- MV_STATUS status;
-
- if(bus == localBus)
- {
- if(dev > 1)
- {
- /* on the local device allow only device #0 & #1 */
- return MV_ERROR;
- }
- else
- if (dev == localDev)
- {
- /* read the memory controller registers */
- return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
- }
- else
- {
- /* access the virtual brg header */
- HEADER_WRITE(data, regOff);
- return MV_OK;
- }
- }
- else
- if(bus == (localBus + 1))
- {
- /* access the device behind the virtual bridge */
- if((dev == localDev) || (dev > 1))
- {
- return MV_ERROR;
- }
- else
- {
- /* access the device behind the virtual bridge, in this case
- * change the bus number to the local bus number in order to
- * generate type 0 config cycle
- */
- //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data);
- mvPexLocalBusNumSet(pexIf, bus);
- mvPexLocalDevNumSet(pexIf, 1);
- status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data);
- mvPexLocalBusNumSet(pexIf, localBus);
- mvPexLocalDevNumSet(pexIf, localDev);
- return status;
-
- }
- }
- /* for all other devices use the HW function to get the
- * requested registers
- */
- mvPexLocalDevNumSet(pexIf, 1);
- status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
- mvPexLocalDevNumSet(pexIf, localDev);
- return status;
-}
-
-
-
-
-void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev)
-{
- MV_U32 tData;
- MV_U32 i;
-
- /* restore the PEX configuration to initialization state */
- /* in case PEX P2P call recursive and reset config */
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0);
- if(tData != 0xffffffff)
- {
- /* agent had been found - check whether P2P */
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8);
- if((tData & 0xffff0000) == 0x06040000)
- {/* P2P */
- /* get the sec bus and the subordinate */
- MV_U32 secBus;
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18);
- secBus = ((tData >> 8) & 0xff);
- /* now scan on sec bus */
- for(i = 0;i < 0xff;i++)
- {
- resetPexConfig(pexIf, secBus, i);
- }
- /* now reset this device */
- DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
- mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0);
- DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
- }
- }
-}
-
-
diff --git a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h b/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h deleted file mode 100644 index 82eb72d50e..0000000000 --- a/target/linux/generic/files/crypto/ocf/kirkwood/mvHal/mv_hal/pex/mvVrtBrgPex.h +++ /dev/null @@ -1,82 +0,0 @@ -/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef __INCVRTBRGPEXH
-#define __INCVRTBRGPEXH
-
-
-/* Global Functions prototypes */
-/* mvPexInit - Initialize PEX interfaces*/
-MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf);
-
-/* mvPexConfigRead - Read from configuration space */
-MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func,MV_U32 regOff);
-
-/* mvPexConfigWrite - Write to configuration space */
-MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data);
-
-
-#endif /* #ifndef __INCPEXH */
|