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| author | John Crispin <blogic@openwrt.org> | 2015-12-23 18:24:56 +0000 |
|---|---|---|
| committer | John Crispin <blogic@openwrt.org> | 2015-12-23 18:24:56 +0000 |
| commit | cdc0b0b85b43cd249a09f5cdf099a9851f53f424 (patch) | |
| tree | dd6287bedac1df361129148819033631369304d3 /target/linux/lantiq | |
| parent | db497f9f0cdbb23888183e39feb936b4f1bae1db (diff) | |
| download | master-187ad058-cdc0b0b85b43cd249a09f5cdf099a9851f53f424.tar.gz master-187ad058-cdc0b0b85b43cd249a09f5cdf099a9851f53f424.tar.bz2 master-187ad058-cdc0b0b85b43cd249a09f5cdf099a9851f53f424.zip | |
lantiq: TDW89x0 - increase spi frequency
Use the same max spi frequency as set in u-boot.
According to the datasheets, the Q64-104HIP as well as the Winbond
25Q64FVSIG support spi frequencies up to 50 MHz. During my tests, the
Q64-104HIP couldn't be recognized/initialized if the frequency
was > 40MHz.
Both chips do support fast read as well.
While touching the dts file, I fixed the dtc compiler warnings.
Signed-off-by: Mathias Kresin <openwrt@kresin.me>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47994 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/lantiq')
| -rw-r--r-- | target/linux/lantiq/dts/TDW89X0.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/target/linux/lantiq/dts/TDW89X0.dtsi b/target/linux/lantiq/dts/TDW89X0.dtsi index cd3d6bdbbd..46ff11f547 100644 --- a/target/linux/lantiq/dts/TDW89X0.dtsi +++ b/target/linux/lantiq/dts/TDW89X0.dtsi @@ -16,12 +16,14 @@ interrupt-parent = <&icu0>; interrupts = <22 23 24>; #address-cells = <1>; + #size-cells = <1>; m25p80@0 { #address-cells = <1>; #size-cells = <1>; compatible = "jedec,spi-nor"; - reg = <3>; - spi-max-frequency = <20000000>; + reg = <3 0>; + spi-max-frequency = <33250000>; + m25p,fast-read; partition@0 { reg = <0x0 0x20000>; |