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author | Luka Perkov <luka.perkov@sartura.hr> | 2016-06-23 13:57:21 +0200 |
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committer | GitHub <noreply@github.com> | 2016-06-23 13:57:21 +0200 |
commit | 282b917e47d9ae5017e1e426face9b75cb7aabd0 (patch) | |
tree | 3284ca2d20d9c8d7a4563c6446675c1ecf3feac2 /target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch | |
parent | 34d432b05312de6d9575c559db8209809489096d (diff) | |
parent | 441a9c879ba6562ea9f431cf33bbb0c0400d5fd0 (diff) | |
download | master-187ad058-282b917e47d9ae5017e1e426face9b75cb7aabd0.tar.gz master-187ad058-282b917e47d9ae5017e1e426face9b75cb7aabd0.tar.bz2 master-187ad058-282b917e47d9ae5017e1e426face9b75cb7aabd0.zip |
Merge pull request #11 from wigyori/master
pull req for 4.4.12, ar71xx/mediatek updates, package upgrades
Diffstat (limited to 'target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch')
-rw-r--r-- | target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch b/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch new file mode 100644 index 0000000000..64fb545b24 --- /dev/null +++ b/target/linux/ar71xx/patches-4.4/103-MIPS-ath79-fix-register-address-in-ath79_ddr_wb_flus.patch @@ -0,0 +1,23 @@ +From: Felix Fietkau <nbd@nbd.name> +Date: Wed, 18 May 2016 18:03:31 +0200 +Subject: [PATCH] MIPS: ath79: fix register address in ath79_ddr_wb_flush() + +ath79_ddr_wb_flush_base has the type void __iomem *, so register offsets +need to be a multiple of 4. + +Cc: Alban Bedel <albeu@free.fr> +Fixes: 24b0e3e84fbf ("MIPS: ath79: Improve the DDR controller interface") +Signed-off-by: Felix Fietkau <nbd@nbd.name> +--- + +--- a/arch/mips/ath79/common.c ++++ b/arch/mips/ath79/common.c +@@ -58,7 +58,7 @@ EXPORT_SYMBOL_GPL(ath79_ddr_ctrl_init); + + void ath79_ddr_wb_flush(u32 reg) + { +- void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg; ++ void __iomem *flush_reg = ath79_ddr_wb_flush_base + reg * 4; + + /* Flush the DDR write buffer. */ + __raw_writel(0x1, flush_reg); |