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authorFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
committerFelix Fietkau <nbd@openwrt.org>2015-11-02 18:20:51 +0000
commitf92acf9810cb10decdae02b3e22dee6aae6854d6 (patch)
treeb2fb3f558930fc94dbe0c7b78bee2e58927e2ceb /target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch
parent7b048896c9596b5f65263076ff25a5ca8ac5882b (diff)
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ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60. Signed-off-by: Dmitry Ivanov <dima@ubnt.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47363 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.1/404-mtd-cybertan-trx-parser.patch')
0 files changed, 0 insertions, 0 deletions