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| author | Felix Fietkau <nbd@openwrt.org> | 2015-11-02 18:20:51 +0000 |
|---|---|---|
| committer | Felix Fietkau <nbd@openwrt.org> | 2015-11-02 18:20:51 +0000 |
| commit | f92acf9810cb10decdae02b3e22dee6aae6854d6 (patch) | |
| tree | b2fb3f558930fc94dbe0c7b78bee2e58927e2ceb /target/linux/ar71xx/patches-4.1 | |
| parent | 7b048896c9596b5f65263076ff25a5ca8ac5882b (diff) | |
| download | master-187ad058-f92acf9810cb10decdae02b3e22dee6aae6854d6.tar.gz master-187ad058-f92acf9810cb10decdae02b3e22dee6aae6854d6.tar.bz2 master-187ad058-f92acf9810cb10decdae02b3e22dee6aae6854d6.zip | |
ar71xx: use correct PLL configuration register bitmask for QCA956x SoC.
Incorrect value causes clock inaccuracy as huge as 1/60.
Signed-off-by: Dmitry Ivanov <dima@ubnt.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
git-svn-id: svn://svn.openwrt.org/openwrt/trunk@47363 3c298f89-4303-0410-b956-a3cf2f4a3e73
Diffstat (limited to 'target/linux/ar71xx/patches-4.1')
| -rw-r--r-- | target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch index 761eda4df5..ca92d0ec87 100644 --- a/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch +++ b/target/linux/ar71xx/patches-4.1/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch @@ -529,7 +529,7 @@ +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x3fff ++#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff +#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff + @@ -541,7 +541,7 @@ +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0 +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f +#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5 -+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x3fff ++#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff +#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18 +#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff + |