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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity counter is
port
(
divisor : in integer;
clk : in std_logic;
n_reset : in std_logic;
pulse_out : out std_logic
);
end counter;
architecture rtl of counter is
signal d :
std_logic_vector (31 downto 0);
signal q :
std_logic;
begin
pulse_out <= q;
process (clk, d, q, divisor, n_reset)
begin
if n_reset = '0' then
d <= (others => '0');
q <= '0';
elsif RISING_EDGE(clk) then
if d < divisor then
d <= d + 1;
q <= '0';
else
d <= (others => '0');
q <= '1';
end if;
end if;
end process;
end rtl;
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