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library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
entity ccd is
port
(
n_reset : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end ccd;
architecture rtl of ccd is
component dflipflop is
port (
n_reset : in std_logic;
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
signal d1 :
std_logic;
begin
dff1 :
dflipflop port map (
n_reset => n_reset,
d => d,
clk => clk,
q => d1
);
dff2 :
dflipflop port map (
n_reset => n_reset,
d => d1,
clk => clk,
q => q
);
end rtl;
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