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author | fishsoupisgood <github@madingley.org> | 2018-05-17 09:17:21 +0100 |
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committer | fishsoupisgood <github@madingley.org> | 2018-05-17 09:17:21 +0100 |
commit | 0780df86a9ec88bf8810f7fef1d241030dc1b655 (patch) | |
tree | 616b7af709d554a64de9c6077e34c8d64919c875 /counter.vhd | |
download | rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.tar.gz rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.tar.bz2 rob_spdif-0780df86a9ec88bf8810f7fef1d241030dc1b655.zip |
first version for rob - supports only 44.1kHz
Diffstat (limited to 'counter.vhd')
-rw-r--r-- | counter.vhd | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/counter.vhd b/counter.vhd new file mode 100644 index 0000000..4ae6a2a --- /dev/null +++ b/counter.vhd @@ -0,0 +1,45 @@ + + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +use IEEE.std_logic_unsigned.all; +use IEEE.numeric_std.all; + +entity counter is + port + ( + divisor : in std_logic_vector(15 downto 0) := (others => '0'); + clk : in std_logic; + n_reset : in std_logic; + clk_out : out std_logic + ); +end counter; + + +architecture rtl of counter is + + signal d : + std_logic_vector (15 downto 0); + signal q : + std_logic; +begin + + clk_out <= q; + process (clk, d, q, divisor, n_reset) + begin + if n_reset = '0' then + d <= (others => '0'); + q <= '0'; + elsif RISING_EDGE(clk) then + + if d < divisor then + d <= d + 1; + else + d <= (others => '0'); + q <= not q; + end if; + end if; + end process; + +end rtl; + |