diff options
Diffstat (limited to 'libopencm3/include/libopencm3/sam')
20 files changed, 1501 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/sam/3a/irq.json b/libopencm3/include/libopencm3/sam/3a/irq.json new file mode 100644 index 0000000..c3d8c10 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3a/irq.json @@ -0,0 +1,52 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc_sdramc", + "sdramc", + "pioa", + "piob", + "pioc", + "piod", + "pioe", + "piof", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi0", + "spi1", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "tc6", + "tc7", + "tc8", + "pwm", + "adc", + "dacc", + "dmac", + "uotghs", + "trng", + "reserved0", + "can0", + "can1" + ], + "partname_humanreadable": "Atmel SAM3A series", + "partname_doxygen": "SAM3A", + "includeguard": "LIBOPENCM3_SAM3A_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3a/memorymap.h b/libopencm3/include/libopencm3/sam/3a/memorymap.h new file mode 100644 index 0000000..90d97c6 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3a/memorymap.h @@ -0,0 +1,77 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3A_MEMORYMAP_H +#define SAM3A_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3A peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI0_BASE (0x40008000U) +#define SPI1_BASE (0x4000C000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TC3_BASE (0x40084000U) +#define TC4_BASE (0x40084040U) +#define TC5_BASE (0x40084080U) +#define TC6_BASE (0x40088000U) +#define TC7_BASE (0x40088040U) +#define TC8_BASE (0x40088080U) +#define TWI0_BASE (0x4008C000U) +#define TWI1_BASE (0x40090000U) +#define PWM_BASE (0x40094000U) +#define USART0_BASE (0x40098000U) +#define USART1_BASE (0x4009C000U) +#define USART2_BASE (0x400A0000U) +#define USART3_BASE (0x400A4000U) +#define UOTGHS_BASE (0x400AC000U) +#define CAN0_BASE (0x400B4000U) +#define CAN1_BASE (0x400B8000U) +#define TRNG_BASE (0x400BC000U) +#define ADC_BASE (0x400C0000U) +#define DMAC_BASE (0x400C4000U) +#define DACC_BASE (0x400C8000U) + +/* --- SAM3A system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define SDRAM_BASE (0x400E0200U) +#define MATRIX_BASE (0x400E0400U) +#define PMC_BASE (0x400E0600U) +#define UART_BASE (0x400E0800U) +#define CHIPID_BASE (0x400E0940U) +#define EEFC0_BASE (0x400E0A00U) +#define EEFC1_BASE (0x400E0C00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define PIOD_BASE (0x400E1400U) +#define PIOE_BASE (0x400E1600U) +#define PIOF_BASE (0x400E1800U) +#define RSTC_BASE (0x400E1A00U) +#define SUPC_BASE (0x400E1A10U) +#define RTT_BASE (0x400E1A30U) +#define WDT_BASE (0x400E1A50U) +#define RTC_BASE (0x400E1A60U) +#define GPBR_BASE (0x400E1A90U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3n/irq.json b/libopencm3/include/libopencm3/sam/3n/irq.json new file mode 100644 index 0000000..9d1d39e --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3n/irq.json @@ -0,0 +1,39 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc", + "reserved0", + "uart0", + "uart1", + "reserved1", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "reserved2", + "reserved3", + "reserved4", + "twi0", + "twi1", + "spi", + "reserved5", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "adc", + "dacc", + "pwm" + ], + "partname_humanreadable": "Atmel SAM3N series", + "partname_doxygen": "SAM3N", + "includeguard": "LIBOPENCM3_SAM3N_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3n/memorymap.h b/libopencm3/include/libopencm3/sam/3n/memorymap.h new file mode 100644 index 0000000..34c193f --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3n/memorymap.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3N_MEMORYMAP_H +#define SAM3N_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3N peripheral space -------------------------------------------- */ + +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40010000U) +#define TC1_BASE (0x40010040U) +#define TC2_BASE (0x40010080U) +#define TC3_BASE (0x40014000U) +#define TC4_BASE (0x40014040U) +#define TC5_BASE (0x40014080U) +#define TWI0_BASE (0x40018000U) +#define TWI1_BASE (0x4001C000U) +#define PWM_BASE (0x40020000U) +#define USART0_BASE (0x40024000U) +#define USART1_BASE (0x40028000U) +#define ADC_BASE (0x40038000U) +#define DACC_BASE (0x4003C000U) + +/* --- SAM3N system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART0_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define UART1_BASE (0x400E0800U) +#define EEFC_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define RSTC_BASE (0x400E1400U) +#define SUPC_BASE (0x400E1410U) +#define RTT_BASE (0x400E1430U) +#define WDT_BASE (0x400E1450U) +#define RTC_BASE (0x400E1460U) +#define GPBR_BASE (0x400E1490U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3s/irq.json b/libopencm3/include/libopencm3/sam/3s/irq.json new file mode 100644 index 0000000..ddf76f6 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3s/irq.json @@ -0,0 +1,42 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc", + "reserved0", + "uart0", + "uart1", + "smc", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "usart2", + "reserved1", + "hsmci", + "twi0", + "twi1", + "spi", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "adc", + "dacc", + "pwm", + "crccu", + "acc", + "udp" + ], + "partname_humanreadable": "Atmel SAM3S series", + "partname_doxygen": "SAM3S", + "includeguard": "LIBOPENCM3_SAM3S_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3s/memorymap.h b/libopencm3/include/libopencm3/sam/3s/memorymap.h new file mode 100644 index 0000000..0ce7200 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3s/memorymap.h @@ -0,0 +1,66 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3S_MEMORYMAP_H +#define SAM3S_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3S peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40010000U) +#define TC1_BASE (0x40010040U) +#define TC2_BASE (0x40010080U) +#define TC3_BASE (0x40014000U) +#define TC4_BASE (0x40014040U) +#define TC5_BASE (0x40014080U) +#define TWI0_BASE (0x40018000U) +#define TWI1_BASE (0x4001C000U) +#define PWM_BASE (0x40020000U) +#define USART0_BASE (0x40024000U) +#define USART1_BASE (0x40028000U) +#define USART2_BASE (0x4002C000U) +#define UDP_BASE (0x40034000U) +#define ADC_BASE (0x40038000U) +#define DACC_BASE (0x4003C000U) +#define ACC_BASE (0x40040000U) +#define CRCCU_BASE (0x40044000U) + +/* --- SAM3S system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART0_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define UART1_BASE (0x400E0800U) +#define EEFC_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define RSTC_BASE (0x400E1400U) +#define SUPC_BASE (0x400E1410U) +#define RTT_BASE (0x400E1430U) +#define WDT_BASE (0x400E1450U) +#define RTC_BASE (0x400E1460U) +#define GPBR_BASE (0x400E1490U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3u/irq.json b/libopencm3/include/libopencm3/sam/3u/irq.json new file mode 100644 index 0000000..c52f183 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3u/irq.json @@ -0,0 +1,37 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc", + "pioa", + "piob", + "pioc", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi", + "ssc", + "tc0", + "tc1", + "tc2", + "pwm", + "adc12b", + "adc", + "dmac", + "udphs" + ], + "partname_humanreadable": "Atmel SAM3U series", + "partname_doxygen": "SAM3U", + "includeguard": "LIBOPENCM3_SAM3U_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3u/memorymap.h b/libopencm3/include/libopencm3/sam/3u/memorymap.h new file mode 100644 index 0000000..edd2f29 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3u/memorymap.h @@ -0,0 +1,63 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3U_MEMORYMAP_H +#define SAM3U_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3U peripheral space -------------------------------------------- */ +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TWI0_BASE (0x40084000U) +#define TWI1_BASE (0x40088000U) +#define PWM_BASE (0x4008C000U) +#define USART0_BASE (0x40090000U) +#define USART1_BASE (0x40094000U) +#define USART2_BASE (0x40098000U) +#define USART3_BASE (0x4009C000U) +#define UDPHS_BASE (0x400A4000U) +#define ADC12B_BASE (0x400A8000U) +#define ADC_BASE (0x400AC000U) +#define DMAC_BASE (0x400B0000U) + +/* --- SAM3U system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define EEFC0_BASE (0x400E0800U) +#define EEFC1_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0C00U) +#define PIOB_BASE (0x400E0E00U) +#define PIOC_BASE (0x400E1000U) +#define RSTC_BASE (0x400E1200U) +#define SUPC_BASE (0x400E1210U) +#define RTT_BASE (0x400E1230U) +#define WDT_BASE (0x400E1250U) +#define RTC_BASE (0x400E1260U) +#define GPBR_BASE (0x400E1290U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/3x/irq.json b/libopencm3/include/libopencm3/sam/3x/irq.json new file mode 100644 index 0000000..c53d63c --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3x/irq.json @@ -0,0 +1,52 @@ +{ + "irqs": [ + "supc", + "rstc", + "rtc", + "rtt", + "wdt", + "pmc", + "eefc0", + "eefc1", + "uart", + "smc_sdramc", + "sdramc", + "pioa", + "piob", + "pioc", + "piod", + "pioe", + "piof", + "usart0", + "usart1", + "usart2", + "usart3", + "hsmci", + "twi0", + "twi1", + "spi0", + "spi1", + "ssc", + "tc0", + "tc1", + "tc2", + "tc3", + "tc4", + "tc5", + "tc6", + "tc7", + "tc8", + "pwm", + "adc", + "dacc", + "dmac", + "uotghs", + "trng", + "emac", + "can0", + "can1" + ], + "partname_humanreadable": "Atmel SAM3X series", + "partname_doxygen": "SAM3X", + "includeguard": "LIBOPENCM3_SAM3X_NVIC_H" +}
\ No newline at end of file diff --git a/libopencm3/include/libopencm3/sam/3x/memorymap.h b/libopencm3/include/libopencm3/sam/3x/memorymap.h new file mode 100644 index 0000000..dea04bb --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3x/memorymap.h @@ -0,0 +1,78 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_MEMORYMAP_H +#define SAM3X_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3X peripheral space -------------------------------------------- */ + +#define HSMCI_BASE (0x40000000U) +#define SSC_BASE (0x40004000U) +#define SPI0_BASE (0x40008000U) +#define SPI1_BASE (0x4000C000U) +#define TC0_BASE (0x40080000U) +#define TC1_BASE (0x40080040U) +#define TC2_BASE (0x40080080U) +#define TC3_BASE (0x40084000U) +#define TC4_BASE (0x40084040U) +#define TC5_BASE (0x40084080U) +#define TC6_BASE (0x40088000U) +#define TC7_BASE (0x40088040U) +#define TC8_BASE (0x40088080U) +#define TWI0_BASE (0x4008C000U) +#define TWI1_BASE (0x40090000U) +#define PWM_BASE (0x40094000U) +#define USART0_BASE (0x40098000U) +#define USART1_BASE (0x4009C000U) +#define USART2_BASE (0x400A0000U) +#define USART3_BASE (0x400A4000U) +#define UOTGHS_BASE (0x400AC000U) +#define EMAC_BASE (0x400B0000U) +#define CAN0_BASE (0x400B4000U) +#define CAN1_BASE (0x400B8000U) +#define TRNG_BASE (0x400BC000U) +#define ADC_BASE (0x400C0000U) +#define DMAC_BASE (0x400C4000U) +#define DACC_BASE (0x400C8000U) + +/* --- SAM3X system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define SDRAM_BASE (0x400E0200U) +#define MATRIX_BASE (0x400E0400U) +#define PMC_BASE (0x400E0600U) +#define UART_BASE (0x400E0800U) +#define CHIPID_BASE (0x400E0940U) +#define EEFC0_BASE (0x400E0A00U) +#define EEFC1_BASE (0x400E0C00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define PIOD_BASE (0x400E1400U) +#define PIOE_BASE (0x400E1600U) +#define PIOF_BASE (0x400E1800U) +#define RSTC_BASE (0x400E1A00U) +#define SUPC_BASE (0x400E1A10U) +#define RTT_BASE (0x400E1A30U) +#define WDT_BASE (0x400E1A50U) +#define RTC_BASE (0x400E1A60U) +#define GPBR_BASE (0x400E1A90U) + +#endif diff --git a/libopencm3/include/libopencm3/sam/eefc.h b/libopencm3/include/libopencm3/sam/eefc.h new file mode 100644 index 0000000..eb6d4d0 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/eefc.h @@ -0,0 +1,83 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_EEFC_H +#define SAM3X_EEFC_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Convenience macros ------------------------------------------------ */ +#define EEFC EEFC_BASE +#define EEFC0 EEFC0_BASE +#define EEFC1 EEFC1_BASE + +/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */ +#define EEFC_FMR(port) MMIO32((port) + 0x00) +#define EEFC_FCR(port) MMIO32((port) + 0x04) +#define EEFC_FSR(port) MMIO32((port) + 0x08) +#define EEFC_FRR(port) MMIO32((port) + 0x0C) +/* 0x0010 - Reserved */ + + +/* EEFC Flash Mode Register (EEFC_FMR) */ +/* Bit [31:25] - Reserved */ +#define EEFC_FMR_FAM (0x01 << 24) +/* Bit [23:12] - Reserved */ +#define EEFC_FMR_FWS_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define EEFC_FMR_FRDY (0x01 << 0) + +/* EEFC Flash Command Register (EEFC_FCR) */ +#define EEFC_FCR_FKEY (0x5A << 24) +#define EEFC_FCR_FARG_MASK (0xFFFF << 8) +#define EEFC_FCR_FCMD_MASK (0xFF << 0) +#define EEFC_FCR_FCMD_GETD (0x00 << 0) +#define EEFC_FCR_FCMD_WP (0x01 << 0) +#define EEFC_FCR_FCMD_WPL (0x02 << 0) +#define EEFC_FCR_FCMD_EWP (0x03 << 0) +#define EEFC_FCR_FCMD_EWPL (0x04 << 0) +#define EEFC_FCR_FCMD_EA (0x05 << 0) +#define EEFC_FCR_FCMD_SLB (0x08 << 0) +#define EEFC_FCR_FCMD_CLB (0x09 << 0) +#define EEFC_FCR_FCMD_GLB (0x0A << 0) +#define EEFC_FCR_FCMD_SGPB (0x0B << 0) +#define EEFC_FCR_FCMD_CGPB (0x0C << 0) +#define EEFC_FCR_FCMD_GGPB (0x0D << 0) +#define EEFC_FCR_FCMD_STUI (0x0E << 0) +#define EEFC_FCR_FCMD_SPUI (0x0F << 0) + +/* EEFC Flash Status Register (EEFC_FSR) */ +/* Bit [31:3] - Reserved */ +#define EEFC_FSR_FLOCKE (0x01 << 2) +#define EEFC_FSR_FCMDE (0x01 << 1) +#define EEFC_FSR_FRDY (0x01 << 0) + +static inline void eefc_set_latency(uint8_t wait) +{ +#if defined(SAM3A) || defined(SAM3U) || defined(SAM3X) + EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8); + EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8); +#elif defined(SAM3N) || defined(SAM3S) + EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8); +#endif +} + +#endif + diff --git a/libopencm3/include/libopencm3/sam/gpio.h b/libopencm3/include/libopencm3/sam/gpio.h new file mode 100644 index 0000000..20fd9ad --- /dev/null +++ b/libopencm3/include/libopencm3/sam/gpio.h @@ -0,0 +1,51 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_GPIO_H +#define SAM3X_GPIO_H + +#include <libopencm3/sam/pio.h> + +/* flags may be or'd together, but only contain one of + * GPOUTPUT, PERIPHA and PERIPHB */ +enum gpio_flags { + GPIO_FLAG_GPINPUT = 0, + GPIO_FLAG_GPOUTPUT = 1, + GPIO_FLAG_PERIPHA = 2, + GPIO_FLAG_PERIPHB = 3, + GPIO_FLAG_OPEN_DRAIN = 4, + GPIO_FLAG_PULL_UP = 8, +}; + +void gpio_init(uint32_t gpioport, uint32_t pins, enum gpio_flags flags); + +static inline void gpio_set(uint32_t gpioport, uint32_t gpios) +{ + PIO_SODR(gpioport) = gpios; +} + +static inline void gpio_clear(uint32_t gpioport, uint32_t gpios) +{ + PIO_CODR(gpioport) = gpios; +} + +void gpio_toggle(uint32_t gpioport, uint32_t gpios); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/memorymap.h b/libopencm3/include/libopencm3/sam/memorymap.h new file mode 100644 index 0000000..eb1b85b --- /dev/null +++ b/libopencm3/include/libopencm3/sam/memorymap.h @@ -0,0 +1,39 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * Copyright (C) 2014 Felix Held <felix-libopencm3@felixheld.de> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM_MEMORYMAP_H +#define SAM_MEMORYMAP_H + +#if defined(SAM3A) +# include <libopencm3/sam/3a/memorymap.h> +#elif defined(SAM3N) +# include <libopencm3/sam/3n/memorymap.h> +#elif defined(SAM3S) +# include <libopencm3/sam/3s/memorymap.h> +#elif defined(SAM3U) +# include <libopencm3/sam/3u/memorymap.h> +#elif defined(SAM3X) +# include <libopencm3/sam/3x/memorymap.h> +#else +# error "Processor family not defined." +#endif + +#endif + diff --git a/libopencm3/include/libopencm3/sam/pio.h b/libopencm3/include/libopencm3/sam/pio.h new file mode 100644 index 0000000..3288718 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pio.h @@ -0,0 +1,96 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM_PIO_H +#define SAM_PIO_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Convenience macros ------------------------------------------------ */ + +/* GPIO port base addresses (for convenience) */ +#define PIOA PIOA_BASE +#define PIOB PIOB_BASE +#define PIOC PIOC_BASE +#define PIOD PIOD_BASE +#define PIOE PIOE_BASE +#define PIOF PIOF_BASE +#define PIOG PIOG_BASE +#define PIOH PIOH_BASE + +/* --- PIO registers ----------------------------------------------------- */ + +#define PIO_PER(port) MMIO32((port) + 0x0000) +#define PIO_PDR(port) MMIO32((port) + 0x0004) +#define PIO_PSR(port) MMIO32((port) + 0x0008) +/* 0x000C - Reserved */ +#define PIO_OER(port) MMIO32((port) + 0x0010) +#define PIO_ODR(port) MMIO32((port) + 0x0014) +#define PIO_OSR(port) MMIO32((port) + 0x0018) +/* 0x001C - Reserved */ +#define PIO_IFER(port) MMIO32((port) + 0x0020) +#define PIO_IFDR(port) MMIO32((port) + 0x0024) +#define PIO_IFSR(port) MMIO32((port) + 0x0028) +/* 0x002C - Reserved */ +#define PIO_SODR(port) MMIO32((port) + 0x0030) +#define PIO_CODR(port) MMIO32((port) + 0x0034) +#define PIO_ODSR(port) MMIO32((port) + 0x0038) +#define PIO_PDSR(port) MMIO32((port) + 0x003C) +#define PIO_IER(port) MMIO32((port) + 0x0040) +#define PIO_IDR(port) MMIO32((port) + 0x0044) +#define PIO_IMR(port) MMIO32((port) + 0x0048) +#define PIO_ISR(port) MMIO32((port) + 0x004C) +#define PIO_MDER(port) MMIO32((port) + 0x0050) +#define PIO_MDDR(port) MMIO32((port) + 0x0054) +#define PIO_MDSR(port) MMIO32((port) + 0x0058) +/* 0x005C - Reserved */ +#define PIO_PUDR(port) MMIO32((port) + 0x0060) +#define PIO_PUER(port) MMIO32((port) + 0x0064) +#define PIO_PUSR(port) MMIO32((port) + 0x0068) +/* 0x006C - Reserved */ +#define PIO_ABSR(port) MMIO32((port) + 0x0070) +/* 0x0074-0x007C - Reserved */ +#define PIO_SCIFSR(port) MMIO32((port) + 0x0080) +#define PIO_DIFSR(port) MMIO32((port) + 0x0084) +#define PIO_IFDGSR(port) MMIO32((port) + 0x0088) +#define PIO_SCDR(port) MMIO32((port) + 0x008C) +/* 0x0090-0x009C - Reserved */ +#define PIO_OWER(port) MMIO32((port) + 0x00A0) +#define PIO_OWDR(port) MMIO32((port) + 0x00A4) +#define PIO_OWSR(port) MMIO32((port) + 0x00A8) +/* 0x00AC - Reserved */ +#define PIO_AIMER(port) MMIO32((port) + 0x00B0) +#define PIO_AIMDR(port) MMIO32((port) + 0x00B4) +#define PIO_AIMMR(port) MMIO32((port) + 0x00B8) +/* 0x00BC - Reserved */ +#define PIO_ESR(port) MMIO32((port) + 0x00C0) +#define PIO_LSR(port) MMIO32((port) + 0x00C4) +#define PIO_ELSR(port) MMIO32((port) + 0x00C8) +/* 0x00CC - Reserved */ +#define PIO_FELLSR(port) MMIO32((port) + 0x00D0) +#define PIO_REHLSR(port) MMIO32((port) + 0x00D4) +#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8) +/* 0x00DC - Reserved */ +#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0) +#define PIO_WPMR(port) MMIO32((port) + 0x00E4) +#define PIO_WPSR(port) MMIO32((port) + 0x00E8) +/* 0x00EC-0x0144 - Reserved */ + +#endif diff --git a/libopencm3/include/libopencm3/sam/pmc.h b/libopencm3/include/libopencm3/sam/pmc.h new file mode 100644 index 0000000..ab90148 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pmc.h @@ -0,0 +1,146 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_PMC_H +#define SAM3X_PMC_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Power Management Controller (PMC) registers ----------------------- */ + +#define PMC_SCER MMIO32(PMC_BASE + 0x0000) +#define PMC_SCDR MMIO32(PMC_BASE + 0x0004) +#define PMC_SCSR MMIO32(PMC_BASE + 0x0008) +/* 0x000C - Reserved */ +#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010) +#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014) +#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018) +#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C) +#define CKGR_MOR MMIO32(PMC_BASE + 0x0020) +#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024) +#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028) +/* 0x002C - Reserved */ +#define PMC_MCKR MMIO32(PMC_BASE + 0x0030) +/* 0x0034 - Reserved */ +#define PMC_USB MMIO32(PMC_BASE + 0x0038) +/* 0x003C - Reserved */ +#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040) +#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044) +#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048) +/* 0x004C-0x005C - Reserved */ +#define PMC_IER MMIO32(PMC_BASE + 0x0060) +#define PMC_IDR MMIO32(PMC_BASE + 0x0064) +#define PMC_SR MMIO32(PMC_BASE + 0x0068) +#define PMC_IMR MMIO32(PMC_BASE + 0x006C) +#define PMC_FSMR MMIO32(PMC_BASE + 0x0070) +#define PMC_FSPR MMIO32(PMC_BASE + 0x0074) +#define PMC_FOCR MMIO32(PMC_BASE + 0x0078) +/* 0x007C-0x00E0 - Reserved */ +#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4) +#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8) +/* 0x00EC-0x00FC - Reserved */ +#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100) +#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104) +#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108) +#define PMC_PCR MMIO32(PMC_BASE + 0x010C) + +/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */ +/* Bit [31:22] - Reserved */ +#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20) +/* Bit [19:17] - Reserved */ +#define CKGR_CKGR_UPLLEN (0x01 << 16) +/* Bit [15:0] - Reserved */ + +/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */ +/* Bit [31:26] - Reserved */ +#define CKGR_MOR_CFDEN (0x01 << 25) +#define CKGR_MOR_MOSCSEL (0x01 << 24) +#define CKGR_MOR_KEY (0x37 << 16) +#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8) +/* Bit 7 - Reserved */ +#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4) +#define CKGR_MOR_MOSCRCEN (0x01 << 3) +/* Bit 2 - Reserved */ +#define CKGR_MOR_MOSCXTBY (0x01 << 1) +#define CKGR_MOR_MOSCXTEN (0x01 << 0) + +/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */ +#define CKGR_PLLAR_ONE (0x01 << 29) +#define CKGR_PLLAR_MULA_MASK (0x7FF << 16) +#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8) +#define CKGR_PLLAR_DIVA_MASK (0xFF << 0) + +/* PMC Master Clock Register (PMC_MCKR) */ +/* Bit [31:14] - Reserved */ +#define PMC_MCKR_UPLLDIV2 (0x01 << 13) +#define PMC_MCKR_PLLADIV2 (0x01 << 12) +/* Bit [11:7] - Reserved */ +#define PMC_MCKR_PRES_MASK (0x07 << 4) +/* Bit [3:2] - Reserved */ +#define PMC_MCKR_CSS_MASK (0x03 << 0) +#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0) +#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0) +#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0) +#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0) + +/* PMC USB Clock Register (PMC_USB) */ +/* Bit [31:12] - Reserved */ +#define PMC_USB_USBDIV_MASK (0x0F << 8) +/* Bit [7:1] - Reserved */ +#define PMC_USB_USBS (0x01 << 0) + +/* PMC Status Register (PMC_SR) */ +/* Bits [31:21] - Reserved */ +#define PMC_SR_FOS (0x01 << 20) +#define PMC_SR_CFDS (0x01 << 19) +#define PMC_SR_CFDEV (0x01 << 18) +#define PMC_SR_MOSCRCS (0x01 << 17) +#define PMC_SR_MOSCSELS (0x01 << 16) +/* Bits [15:11] - Reserved */ +#define PMC_SR_PCKRDY2 (0x01 << 10) +#define PMC_SR_PCKRDY1 (0x01 << 9) +#define PMC_SR_PCKRDY0 (0x01 << 8) +#define PMC_SR_OSCSELS (0x01 << 7) +#define PMC_SR_LOCKU (0x01 << 6) +/* Bits [5:4] - Reserved */ +#define PMC_SR_MCKRDY (0x01 << 3) +/* Bit [2] - Reserved */ +#define PMC_SR_LOCKA (0x01 << 1) +#define PMC_SR_MOSCXTS (0x01 << 0) + +extern uint32_t pmc_mck_frequency; + +enum mck_src { + MCK_SRC_SLOW = 0, + MCK_SRC_MAIN = 1, + MCK_SRC_PLLA = 2, + MCK_SRC_UPLL = 3, +}; + +void pmc_mck_set_source(enum mck_src src); +void pmc_xtal_enable(bool en, uint8_t startup_time); +void pmc_plla_config(uint8_t mul, uint8_t div); +void pmc_peripheral_clock_enable(uint8_t pid); +void pmc_peripheral_clock_disable(uint8_t pid); +void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void); +void pmc_clock_setup_in_rc_4mhz_out_84mhz(void); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/pwm.h b/libopencm3/include/libopencm3/sam/pwm.h new file mode 100644 index 0000000..fabb8b1 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/pwm.h @@ -0,0 +1,109 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_PWM_H +#define SAM3X_PWM_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Pulse Width Modulation (PWM) registers ----------------------- */ + +#define PWM_CLK MMIO32(PWM_BASE + 0x0000) +#define PWM_ENA MMIO32(PWM_BASE + 0x0004) +#define PWM_DIS MMIO32(PWM_BASE + 0x0008) +#define PWM_SR MMIO32(PWM_BASE + 0x000C) +#define PWM_IER1 MMIO32(PWM_BASE + 0x0010) +#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014) +#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018) +#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C) +#define PWM_SCM MMIO32(PWM_BASE + 0x0020) +/* 0x0024 - Reserved */ +#define PWM_SCUC MMIO32(PWM_BASE + 0x0028) +#define PWM_SCUP MMIO32(PWM_BASE + 0x002C) +#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030) +#define PWM_IER2 MMIO32(PWM_BASE + 0x0034) +#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038) +#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C) +#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040) +#define PWM_OOV MMIO32(PWM_BASE + 0x0044) +#define PWM_OS MMIO32(PWM_BASE + 0x0048) +#define PWM_OSS MMIO32(PWM_BASE + 0x004C) +#define PWM_OSC MMIO32(PWM_BASE + 0x0050) +#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054) +#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058) +#define PWM_FMR MMIO32(PWM_BASE + 0x005C) +#define PWM_FSR MMIO32(PWM_BASE + 0x0060) +#define PWM_FCR MMIO32(PWM_BASE + 0x0064) +#define PWM_FPV MMIO32(PWM_BASE + 0x0068) +#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C) +#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070) +/* 0x0074:0x0078 - Reserved */ +#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C) +#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080) +/* 0x0084:0x00AC - Reserved */ +#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0) +/* 0x00B4:0x00E0 - Reserved */ +#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4) +#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8) +/* 0x00EC:0x00FC - Reserved */ +/* 0x0100:0x012C - Reserved */ +#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x)) +#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x)) +#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x)) +#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x)) +/* 0x01B0:0x01FC - Reserved */ +#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x)) +#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x)) +#if defined(SAM3X) +# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) +# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) +# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) +# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x)) +# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x)) +# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x)) +#elif defined(SAM3N) +# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x)) +# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x)) +# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x)) +#else +# error "Processor family not defined." +#endif + +static inline void pwm_set_period(int ch, uint32_t period) +{ + PWM_CPRD(ch) = period; +} + +static inline void pwm_set_duty(int ch, uint32_t duty) +{ + PWM_CDTY(ch) = duty; +} + +static inline void pwm_enable(int ch) +{ + PWM_ENA = 1 << ch; +} + +static inline void pwm_disable(int ch) +{ + PWM_DIS = 1 << ch; +} + +#endif diff --git a/libopencm3/include/libopencm3/sam/tc.h b/libopencm3/include/libopencm3/sam/tc.h new file mode 100644 index 0000000..864cc4a --- /dev/null +++ b/libopencm3/include/libopencm3/sam/tc.h @@ -0,0 +1,52 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_TC_H +#define SAM3X_TC_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Timer Counter (TC) registers -------------------------------------- */ + +#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x)) +#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x)) +#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x)) +/* 0x0C + 0x40*channel - Reserved */ +#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x)) +#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x)) +#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x)) +#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x)) +#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x)) +#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x)) +#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x)) +#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x)) +#define TC_BCR MMIO32(TC_BASE + 0xC0) +#define TC_BMR MMIO32(TC_BASE + 0xC4) +#define TC_QIER MMIO32(TC_BASE + 0xC8) +#define TC_QIDR MMIO32(TC_BASE + 0xCC) +#define TC_QIMR MMIO32(TC_BASE + 0xD0) +#define TC_QISR MMIO32(TC_BASE + 0xD4) +#define TC_FMR MMIO32(TC_BASE + 0xD8) +/* 0x00DC:0x00E0 - Undocumented */ +#define TC_WPMR MMIO32(TC_BASE + 0xE4) +/* 0x00E8:0x00F8 - Undocumented */ +/* 0x00FC - Reserved */ + +#endif diff --git a/libopencm3/include/libopencm3/sam/uart.h b/libopencm3/include/libopencm3/sam/uart.h new file mode 100644 index 0000000..becfcb5 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/uart.h @@ -0,0 +1,85 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_UART_H +#define SAM3X_UART_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */ +#define UART_CR MMIO32(UART_BASE + 0x0000) +#define UART_MR MMIO32(UART_BASE + 0x0004) +#define UART_IER MMIO32(UART_BASE + 0x0008) +#define UART_IDR MMIO32(UART_BASE + 0x000C) +#define UART_IMR MMIO32(UART_BASE + 0x0010) +#define UART_SR MMIO32(UART_BASE + 0x0014) +#define UART_RHR MMIO32(UART_BASE + 0x0018) +#define UART_THR MMIO32(UART_BASE + 0x001C) +#define UART_BRGR MMIO32(UART_BASE + 0x0020) +/* 0x0024:0x003C - Reserved */ +/* 0x004C:0x00FC - Reserved */ +/* 0x0100:0x0124 - PDC Area */ + + +/* UART Control Register (UART_CR) */ +/* Bits [31:9] - Reserved */ +#define UART_CR_RSTSTA (0x01 << 8) +#define UART_CR_TXDIS (0x01 << 7) +#define UART_CR_TXEN (0x01 << 6) +#define UART_CR_RXDIS (0x01 << 5) +#define UART_CR_RXEN (0x01 << 4) +#define UART_CR_RSTTX (0x01 << 3) +#define UART_CR_RSTRX (0x01 << 2) +/* Bit [1:0] - Reserved */ + +/* UART Mode Register (UART_MR) */ +/* Bits [31:16] - Reserved */ +#define UART_MR_CHMODE_MASK (0x03 << 14) +#define UART_MR_CHMODE_NORMAL (0x00 << 14) +#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14) +#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) +#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) +/* Bits [13:12] - Reserved */ +#define UART_MR_PAR_MASK (0x07 << 9) +#define UART_MR_PAR_EVEN (0x00 << 9) +#define UART_MR_PAR_ODD (0x01 << 9) +#define UART_MR_PAR_SPACE (0x02 << 9) +#define UART_MR_PAR_MARK (0x03 << 9) +#define UART_MR_PAR_NO (0x04 << 9) +/* Bits [8:0] - Reserved */ + +/* UART Status Register (UART_SR) */ +/* Bits [31:13] - Reserved */ +#define UART_SR_RXBUFF (0x01 << 12) +#define UART_SR_TXBUFF (0x01 << 11) +/* Bit [10] - Reserved */ +#define UART_SR_TXEMPTY (0x01 << 9) +/* Bit [8] - Reserved */ +#define UART_SR_PARE (0x01 << 7) +#define UART_SR_FRAME (0x01 << 6) +#define UART_SR_OVRE (0x01 << 5) +#define UART_SR_ENDTX (0x01 << 4) +#define UART_SR_ENDRX (0x01 << 3) +/* Bit [2] - Reserved */ +#define UART_SR_TXRDY (0x01 << 1) +#define UART_SR_RXRDY (0x01 << 0) + +#endif + diff --git a/libopencm3/include/libopencm3/sam/usart.h b/libopencm3/include/libopencm3/sam/usart.h new file mode 100644 index 0000000..757e93d --- /dev/null +++ b/libopencm3/include/libopencm3/sam/usart.h @@ -0,0 +1,217 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_USART_H +#define SAM3X_USART_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + +#define USART0 USART0_BASE +#define USART1 USART1_BASE +#define USART2 USART2_BASE +#define USART3 USART3_BASE + +/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +#define USART_CR(x) MMIO32((x) + 0x0000) +#define USART_MR(x) MMIO32((x) + 0x0004) +#define USART_IER(x) MMIO32((x) + 0x0008) +#define USART_IDR(x) MMIO32((x) + 0x000C) +#define USART_IMR(x) MMIO32((x) + 0x0010) +#define USART_CSR(x) MMIO32((x) + 0x0014) +#define USART_RHR(x) MMIO32((x) + 0x0018) +#define USART_THR(x) MMIO32((x) + 0x001C) +#define USART_BRGR(x) MMIO32((x) + 0x0020) +#define USART_RTOR(x) MMIO32((x) + 0x0024) +#define USART_TTGR(x) MMIO32((x) + 0x0028) +/* 0x002C:0x003C - Reserved */ +#define USART_FIDI(x) MMIO32((x) + 0x0040) +#define USART_NER(x) MMIO32((x) + 0x0044) +#define USART_NER(x) MMIO32((x) + 0x0044) +/* 0x0048 - Reserved */ +#define USART_IF(x) MMIO32((x) + 0x004C) +#define USART_MAN(x) MMIO32((x) + 0x0050) +#define USART_LINMR(x) MMIO32((x) + 0x0054) +#define USART_LINIR(x) MMIO32((x) + 0x0058) +/* 0x005C:0x00E0 - Reserved */ +#define USART_WPMR(x) MMIO32((x) + 0x00E4) +#define USART_WPSR(x) MMIO32((x) + 0x00E8) +/* 0x00EC:0x00F8 - Reserved */ +#define USART_VERSION(x) MMIO32((x) + 0x00FC) +/* 0x0100:0x0124 - PDC Area */ + + +/* USART Control Register (USART_CR) */ +/* Bits [31:22] - Reserved */ +#define USART_CR_LINWKUP (0x01 << 21) +#define USART_CR_LINABT (0x01 << 20) +#define USART_CR_RTSDIS (0x01 << 19) +#define USART_CR_RCS (0x01 << 19) +#define USART_CR_RTSEN (0x01 << 18) +#define USART_CR_FCS (0x01 << 18) +/* Bits [17:16] - Reserved */ +#define USART_CR_RETTO (0x01 << 15) +#define USART_CR_RSTNACK (0x01 << 14) +#define USART_CR_RSTIT (0x01 << 13) +#define USART_CR_SENDA (0x01 << 12) +#define USART_CR_STTTO (0x01 << 11) +#define USART_CR_STPBRK (0x01 << 10) +#define USART_CR_STTBRK (0x01 << 9) +#define USART_CR_RSTSTA (0x01 << 8) +#define USART_CR_TXDIS (0x01 << 7) +#define USART_CR_TXEN (0x01 << 6) +#define USART_CR_RXDIS (0x01 << 5) +#define USART_CR_RXEN (0x01 << 4) +#define USART_CR_RSTTX (0x01 << 3) +#define USART_CR_RSTRX (0x01 << 2) +/* Bits [1:0] - Reserved */ + +/* USART Mode Register (USART_MR) */ +#define USART_MR_ONEBIT (0x01 << 31) +#define USART_MR_MODSYNC (0x01 << 30) +#define USART_MR_MAN (0x01 << 29) +#define USART_MR_FILTER (0x01 << 28) +/* Bit [27] - Reserved */ +#define USART_MR_MAX_ITERATION_MASK (0x07 << 24) +#define USART_MR_INVDATA (0x01 << 23) +#define USART_MR_VAR_SYNC (0x01 << 22) +#define USART_MR_DSNACK (0x01 << 21) +#define USART_MR_INACK (0x01 << 20) +#define USART_MR_OVER (0x01 << 19) +#define USART_MR_CLKO (0x01 << 18) +#define USART_MR_MODE9 (0x01 << 17) +#define USART_MR_MSBF (0x01 << 16) +#define USART_MR_CPOL (0x01 << 16) +#define USART_MR_CHMODE_MASK (0x03 << 14) +#define USART_MR_CHMODE_NORMAL (0x00 << 14) +#define USART_MR_CHMODE_AUTOMATIC (0x01 << 14) +#define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14) +#define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14) +#define USART_MR_NBSTOP_MASK (0x03 << 12) +#define USART_MR_NBSTOP_1_BIT (0x00 << 12) +#define USART_MR_NBSTOP_1_5_BIT (0x01 << 12) +#define USART_MR_NBSTOP_2_BIT (0x02 << 12) +/* Bits [13:12] - Reserved */ +#define USART_MR_PAR_MASK (0x07 << 9) +#define USART_MR_PAR_EVEN (0x00 << 9) +#define USART_MR_PAR_ODD (0x01 << 9) +#define USART_MR_PAR_SPACE (0x02 << 9) +#define USART_MR_PAR_MARK (0x03 << 9) +#define USART_MR_PAR_NO (0x04 << 9) +/* Bits [8:0] - Reserved */ +#define USART_MR_SYNC (0x01 << 8) +#define USART_MR_CPHA (0x01 << 8) +#define USART_MR_CHRL_MASK (0x03 << 6) +#define USART_MR_CHRL_5BIT (0x00 << 6) +#define USART_MR_CHRL_6BIT (0x01 << 6) +#define USART_MR_CHRL_7BIT (0x02 << 6) +#define USART_MR_CHRL_8BIT (0x03 << 6) +#define USART_MR_USCLKS_MASK (0x03 << 4) +#define USART_MR_USCLKS_MCK (0x00 << 4) +#define USART_MR_USCLKS_DIV (0x01 << 4) +#define USART_MR_USCLKS_SCK (0x03 << 4) +#define USART_MR_MODE_MASK (0x0F << 0) +#define USART_MR_MODE_NORMAL (0x00 << 0) +#define USART_MR_MODE_RS485 (0x01 << 0) +#define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0) +#define USART_MR_MODE_ISO7816_T_0 (0x03 << 0) +#define USART_MR_MODE_ISO7816_T_1 (0x04 << 0) +#define USART_MR_MODE_IRDA (0x06 << 0) +#define USART_MR_MODE_LIN_MASTER (0x0A << 0) +#define USART_MR_MODE_LIN_SLAVE (0x0B << 0) +#define USART_MR_MODE_SPI_MASTER (0x0E << 0) +#define USART_MR_MODE_SPI_SLAVE (0x0F << 0) + +/* USART Status Register (USART_CSR) */ +/* Bits [31:30] - Reserved */ +#define USART_CSR_LINSNRE (0x01 << 29) +#define USART_CSR_LINCE (0x01 << 28) +#define USART_CSR_LINIPE (0x01 << 27) +#define USART_CSR_LINSFE (0x01 << 26) +#define USART_CSR_LINBE (0x01 << 25) +#define USART_CSR_MANERR (0x01 << 24) +#define USART_CSR_CTS (0x01 << 23) +#define USART_CSR_LINBLS (0x01 << 23) +/* Bits [22:20] - Reserved */ +#define USART_CSR_CTSIC (0x01 << 19) +/* Bits [18:16] - Reserved */ +#define USART_CSR_LINTC (0x01 << 15) +#define USART_CSR_LINID (0x01 << 14) +#define USART_CSR_NACK (0x01 << 13) +#define USART_CSR_LINBK (0x01 << 13) +#define USART_CSR_RXBUFF (0x01 << 12) +#define USART_CSR_TXBUFE (0x01 << 11) +/* Bit [10] - Reserved */ +#define USART_CSR_TXEMPTY (0x01 << 9) +/* Bit [8] - Reserved */ +#define USART_CSR_PARE (0x01 << 7) +#define USART_CSR_FRAME (0x01 << 6) +#define USART_CSR_OVRE (0x01 << 5) +#define USART_CSR_ENDTX (0x01 << 4) +#define USART_CSR_ENDRX (0x01 << 3) +/* Bit [2] - Reserved */ +#define USART_CSR_TXRDY (0x01 << 1) +#define USART_CSR_RXRDY (0x01 << 0) + +enum usart_stopbits { + USART_STOPBITS_1, + USART_STOPBITS_1_5, + USART_STOPBITS_2, +}; + +enum usart_parity { + USART_PARITY_EVEN, + USART_PARITY_ODD, + USART_PARITY_SPACE, + USART_PARITY_MARK, + USART_PARITY_NONE, + USART_PARITY_MULTIDROP, +}; + +enum usart_mode { + USART_MODE_DISABLED, + USART_MODE_RX, + USART_MODE_TX, + USART_MODE_TX_RX, +}; + +enum usart_flowcontrol { + USART_FLOWCONTROL_NONE, + USART_FLOWCONTROL_RTS_CTS, +}; + +void usart_set_baudrate(uint32_t usart, uint32_t baud); +void usart_set_databits(uint32_t usart, int bits); +void usart_set_stopbits(uint32_t usart, enum usart_stopbits); +void usart_set_parity(uint32_t usart, enum usart_parity); +void usart_set_mode(uint32_t usart, enum usart_mode); +void usart_set_flow_control(uint32_t usart, enum usart_flowcontrol); +void usart_enable(uint32_t usart); +void usart_disable(uint32_t usart); +void usart_send(uint32_t usart, uint16_t data); +uint16_t usart_recv(uint32_t usart); +void usart_wait_send_ready(uint32_t usart); +void usart_wait_recv_ready(uint32_t usart); +void usart_send_blocking(uint32_t usart, uint16_t data); +uint16_t usart_recv_blocking(uint32_t usart); +void usart_enable_rx_interrupt(uint32_t usart); +void usart_disable_rx_interrupt(uint32_t usart); + +#endif + diff --git a/libopencm3/include/libopencm3/sam/wdt.h b/libopencm3/include/libopencm3/sam/wdt.h new file mode 100644 index 0000000..566ac95 --- /dev/null +++ b/libopencm3/include/libopencm3/sam/wdt.h @@ -0,0 +1,57 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3X_WDT_H +#define SAM3X_WDT_H + +#include <libopencm3/cm3/common.h> +#include <libopencm3/sam/memorymap.h> + + +/* --- WDT registers ----------------------------------------------------- */ + +#define WDT_CR MMIO32(WDT_BASE + 0x00) +#define WDT_MR MMIO32(WDT_BASE + 0x04) +#define WDT_SR MMIO32(WDT_BASE + 0x08) + +/* --- WDT_CR values ------------------------------------------------------ */ + +#define WDT_CR_KEY (0xA5 << 24) +/* Bits [23:1]: Reserved. */ +#define WDT_CR_WDRSTT (1 << 0) + +/* --- WDT_MR values ------------------------------------------------------ */ + +/* Bits [31:32]: Reserved. */ +#define WDT_MR_WDIDLEHLT (1 << 29) +#define WDT_MR_WDDBGHLT (1 << 28) +#define WDT_MR_WDD_MASK (0xFFF << 16) +#define WDT_MR_WDDIS (1 << 15) +#define WDT_MR_WDRPROC (1 << 14) +#define WDT_MR_WDRSTEN (1 << 13) +#define WDT_MR_WDFIEN (1 << 12) +#define WDT_MR_WDV_MASK (0xFFF << 0) + +/* --- WDT_SR values ------------------------------------------------------ */ + +/* Bits [31:2]: Reserved. */ +#define WDT_SR_WDERR (1 << 1) +#define WDT_SR_WDUNF (1 << 0) + +#endif |