diff options
Diffstat (limited to 'libopencm3/include/libopencm3/sam/3n/memorymap.h')
| -rw-r--r-- | libopencm3/include/libopencm3/sam/3n/memorymap.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/sam/3n/memorymap.h b/libopencm3/include/libopencm3/sam/3n/memorymap.h new file mode 100644 index 0000000..34c193f --- /dev/null +++ b/libopencm3/include/libopencm3/sam/3n/memorymap.h @@ -0,0 +1,60 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef SAM3N_MEMORYMAP_H +#define SAM3N_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- SAM3N peripheral space -------------------------------------------- */ + +#define SPI_BASE (0x40008000U) +#define TC0_BASE (0x40010000U) +#define TC1_BASE (0x40010040U) +#define TC2_BASE (0x40010080U) +#define TC3_BASE (0x40014000U) +#define TC4_BASE (0x40014040U) +#define TC5_BASE (0x40014080U) +#define TWI0_BASE (0x40018000U) +#define TWI1_BASE (0x4001C000U) +#define PWM_BASE (0x40020000U) +#define USART0_BASE (0x40024000U) +#define USART1_BASE (0x40028000U) +#define ADC_BASE (0x40038000U) +#define DACC_BASE (0x4003C000U) + +/* --- SAM3N system controller space ------------------------------------- */ +#define SMC_BASE (0x400E0000U) +#define MATRIX_BASE (0x400E0200U) +#define PMC_BASE (0x400E0400U) +#define UART0_BASE (0x400E0600U) +#define CHIPID_BASE (0x400E0740U) +#define UART1_BASE (0x400E0800U) +#define EEFC_BASE (0x400E0A00U) +#define PIOA_BASE (0x400E0E00U) +#define PIOB_BASE (0x400E1000U) +#define PIOC_BASE (0x400E1200U) +#define RSTC_BASE (0x400E1400U) +#define SUPC_BASE (0x400E1410U) +#define RTT_BASE (0x400E1430U) +#define WDT_BASE (0x400E1450U) +#define RTC_BASE (0x400E1460U) +#define GPBR_BASE (0x400E1490U) + +#endif |