diff options
Diffstat (limited to 'libopencm3/include/libopencm3/lm3s')
-rw-r--r-- | libopencm3/include/libopencm3/lm3s/doc-lm3s.h | 32 | ||||
-rw-r--r-- | libopencm3/include/libopencm3/lm3s/gpio.h | 99 | ||||
-rw-r--r-- | libopencm3/include/libopencm3/lm3s/irq.json | 126 | ||||
-rw-r--r-- | libopencm3/include/libopencm3/lm3s/memorymap.h | 47 | ||||
-rw-r--r-- | libopencm3/include/libopencm3/lm3s/systemcontrol.h | 81 |
5 files changed, 385 insertions, 0 deletions
diff --git a/libopencm3/include/libopencm3/lm3s/doc-lm3s.h b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h new file mode 100644 index 0000000..1a4ecb8 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/doc-lm3s.h @@ -0,0 +1,32 @@ +/** @mainpage libopencm3 LM3S + +@version 1.0.0 + +@date 14 September 2012 + +API documentation for TI Stellaris LM3S Cortex M3 series. + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3Sxx LM3S +Libraries for TI Stellaris LM3S series. + +@version 1.0.0 + +@date 7 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + +/** @defgroup LM3Sxx_defines LM3S Defines + +@brief Defined Constants and Types for the LM3S series + +@version 1.0.0 + +@date 14 September 2012 + +LGPL License Terms @ref lgpl_license +*/ + diff --git a/libopencm3/include/libopencm3/lm3s/gpio.h b/libopencm3/include/libopencm3/lm3s/gpio.h new file mode 100644 index 0000000..8b12078 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/gpio.h @@ -0,0 +1,99 @@ +/** @defgroup gpio_defines General Purpose I/O Defines + +@brief <b>Defined Constants and Types for the LM3S General Purpose I/O</b> + +@ingroup LM3Sxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin <gareth@blacksphere.co.nz> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license + */ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LM3S_GPIO_H +#define LM3S_GPIO_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> +#include <libopencm3/lm3s/memorymap.h> + +/* --- Convenience macros -------------------------------------------------- */ + +/* GPIO port base addresses (for convenience) */ +#define GPIOA GPIOA_APB_BASE +#define GPIOB GPIOB_APB_BASE +#define GPIOC GPIOC_APB_BASE +#define GPIOD GPIOD_APB_BASE +#define GPIOE GPIOE_APB_BASE +#define GPIOF GPIOF_APB_BASE +#define GPIOG GPIOG_APB_BASE +#define GPIOH GPIOH_APB_BASE + +/* GPIO number definitions (for convenience) */ +#define GPIO0 (1 << 0) +#define GPIO1 (1 << 1) +#define GPIO2 (1 << 2) +#define GPIO3 (1 << 3) +#define GPIO4 (1 << 4) +#define GPIO5 (1 << 5) +#define GPIO6 (1 << 6) +#define GPIO7 (1 << 7) + +/* --- GPIO registers ------------------------------------------------------ */ + +#define GPIO_DATA(port) (&MMIO32(port + 0x000)) +#define GPIO_DIR(port) MMIO32(port + 0x400) +#define GPIO_IS(port) MMIO32(port + 0x404) +#define GPIO_IBE(port) MMIO32(port + 0x408) +#define GPIO_IEV(port) MMIO32(port + 0x40c) +#define GPIO_IM(port) MMIO32(port + 0x410) +#define GPIO_RIS(port) MMIO32(port + 0x414) +#define GPIO_MIS(port) MMIO32(port + 0x418) +#define GPIO_ICR(port) MMIO32(port + 0x41c) +#define GPIO_AFSEL(port) MMIO32(port + 0x420) +#define GPIO_DR2R(port) MMIO32(port + 0x500) +#define GPIO_DR4R(port) MMIO32(port + 0x504) +#define GPIO_DR8R(port) MMIO32(port + 0x508) +#define GPIO_ODR(port) MMIO32(port + 0x50c) +#define GPIO_PUR(port) MMIO32(port + 0x510) +#define GPIO_PDR(port) MMIO32(port + 0x514) +#define GPIO_SLR(port) MMIO32(port + 0x518) +#define GPIO_DEN(port) MMIO32(port + 0x51c) +#define GPIO_LOCK(port) MMIO32(port + 0x520) +#define GPIO_CR(port) MMIO32(port + 0x524) +#define GPIO_AMSEL(port) MMIO32(port + 0x528) + +BEGIN_DECLS + +void gpio_set(uint32_t gpioport, uint8_t gpios); +void gpio_clear(uint32_t gpioport, uint8_t gpios); + +END_DECLS + +/**@}*/ + +#endif + diff --git a/libopencm3/include/libopencm3/lm3s/irq.json b/libopencm3/include/libopencm3/lm3s/irq.json new file mode 100644 index 0000000..0d8dcfc --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/irq.json @@ -0,0 +1,126 @@ +{ + "_comment": [ + "Although this says LM3S, the interrupt table applies to the", + "LM4F as well Some interrupt vectores marked as reserved in LM3S are", + "used in LM4F, and some vectors in LM3S are marked reserved for LM4F.", + "However, the common vectors are identical, and we can safely use the", + "same interrupt table. Reserved vectors will never be triggered, so", + "having them is perfectly safe." + ], + "irqs": { + "0": "GPIOA", + "1": "GPIOB", + "2": "GPIOC", + "3": "GPIOD", + "4": "GPIOE", + "5": "UART0", + "6": "UART1", + "7": "SSI0", + "8": "I2C0", + "9": "PWM0_FAULT", + "10": "PWM0_0", + "11": "PWM0_1", + "12": "PWM0_2", + "13": "QEI0", + "14": "ADC0SS0", + "15": "ADC0SS1", + "16": "ADC0SS2", + "17": "ADC0SS3", + "18": "WATCHDOG", + "19": "TIMER0A", + "20": "TIMER0B", + "21": "TIMER1A", + "22": "TIMER1B", + "23": "TIMER2A", + "24": "TIMER2B", + "25": "COMP0", + "26": "COMP1", + "27": "COMP2", + "28": "SYSCTL", + "29": "FLASH", + "30": "GPIOF", + "31": "GPIOG", + "32": "GPIOH", + "33": "UART2", + "34": "SSI1", + "35": "TIMER3A", + "36": "TIMER3B", + "37": "I2C1", + "38": "QEI1", + "39": "CAN0", + "40": "CAN1", + "41": "CAN2", + "42": "ETH", + "43": "HIBERNATE", + "44": "USB0", + "45": "PWM0_3", + "46": "UDMA", + "47": "UDMAERR", + "48": "ADC1SS0", + "49": "ADC1SS1", + "50": "ADC1SS2", + "51": "ADC1SS3", + "52": "I2S0", + "53": "EPI0", + "54": "GPIOJ", + "55": "GPIOK", + "56": "GPIOL", + "57": "SSI2", + "58": "SSI3", + "59": "UART3", + "60": "UART4", + "61": "UART5", + "62": "UART6", + "63": "UART7", + "68": "I2C2", + "69": "I2C3", + "70": "TIMER4A", + "71": "TIMER4B", + "92": "TIMER5A", + "93": "TIMER5B", + "94": "WTIMER0A", + "95": "WTIMER0B", + "96": "WTIMER1A", + "97": "WTIMER1B", + "98": "WTIMER2A", + "99": "WTIMER2B", + "100": "WTIMER3A", + "101": "WTIMER3B", + "102": "WTIMER4A", + "103": "WTIMER4B", + "104": "WTIMER5A", + "105": "WTIMER5B", + "106": "SYSEXC", + "107": "PECI0", + "108": "LPC0", + "109": "I2C4", + "110": "I2C5", + "111": "GPIOM", + "112": "GPION", + "114": "FAN0", + "116": "GPIOP0", + "117": "GPIOP1", + "118": "GPIOP2", + "119": "GPIOP3", + "120": "GPIOP4", + "121": "GPIOP5", + "122": "GPIOP6", + "123": "GPIOP7", + "124": "GPIOQ0", + "125": "GPIOQ1", + "126": "GPIOQ2", + "127": "GPIOQ3", + "128": "GPIOQ4", + "129": "GPIOQ5", + "130": "GPIOQ6", + "131": "GPIOQ7", + "134": "PWM1_0", + "135": "PWM1_1", + "136": "PWM1_2", + "137": "PWM1_3", + "138": "PWM1_FAULT" + }, + "partname_humanreadable": "LM3S series", + "partname_doxygen": "LM3S", + "includeguard": "LIBOPENCM3_LM3S_NVIC_H" +} diff --git a/libopencm3/include/libopencm3/lm3s/memorymap.h b/libopencm3/include/libopencm3/lm3s/memorymap.h new file mode 100644 index 0000000..df5d6e3 --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/memorymap.h @@ -0,0 +1,47 @@ +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LM3S_MEMORYMAP_H +#define LM3S_MEMORYMAP_H + +#include <libopencm3/cm3/common.h> + +/* --- LM3S specific peripheral definitions ----------------------------- */ + +#define GPIOA_APB_BASE (0x40004000U) +#define GPIOB_APB_BASE (0x40005000U) +#define GPIOC_APB_BASE (0x40006000U) +#define GPIOD_APB_BASE (0x40007000U) +#define GPIOE_APB_BASE (0x40024000U) +#define GPIOF_APB_BASE (0x40025000U) +#define GPIOG_APB_BASE (0x40026000U) +#define GPIOH_APB_BASE (0x40027000U) + +#define GPIOA_BASE (0x40058000U) +#define GPIOB_BASE (0x40059000U) +#define GPIOC_BASE (0x4005A000U) +#define GPIOD_BASE (0x4005B000U) +#define GPIOE_BASE (0x4005C000U) +#define GPIOF_BASE (0x4005D000U) +#define GPIOG_BASE (0x4005E000U) +#define GPIOH_BASE (0x4005F000U) + +#define SYSTEMCONTROL_BASE (0x400FE000U) + +#endif diff --git a/libopencm3/include/libopencm3/lm3s/systemcontrol.h b/libopencm3/include/libopencm3/lm3s/systemcontrol.h new file mode 100644 index 0000000..dd02f0f --- /dev/null +++ b/libopencm3/include/libopencm3/lm3s/systemcontrol.h @@ -0,0 +1,81 @@ +/** @defgroup systemcontrol_defines System Control + +@brief <b>Defined Constants and Types for the LM3S System Control</b> + +@ingroup LM3Sxx_defines + +@version 1.0.0 + +@author @htmlonly © @endhtmlonly 2011 +Gareth McMullin <gareth@blacksphere.co.nz> + +@date 10 March 2013 + +LGPL License Terms @ref lgpl_license +*/ + +/* + * This file is part of the libopencm3 project. + * + * Copyright (C) 2011 Gareth McMullin <gareth@blacksphere.co.nz> + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef LM3S_SYSTEMCONTROL_H +#define LM3S_SYSTEMCONTROL_H + +/**@{*/ + +#include <libopencm3/cm3/common.h> + +#define SYSTEMCONTROL_DID0 MMIO32(SYSTEMCONTROL_BASE + 0x000) +#define SYSTEMCONTROL_DID1 MMIO32(SYSTEMCONTROL_BASE + 0x004) +#define SYSTEMCONTROL_DC0 MMIO32(SYSTEMCONTROL_BASE + 0x008) +#define SYSTEMCONTROL_DC1 MMIO32(SYSTEMCONTROL_BASE + 0x010) +#define SYSTEMCONTROL_DC2 MMIO32(SYSTEMCONTROL_BASE + 0x014) +#define SYSTEMCONTROL_DC3 MMIO32(SYSTEMCONTROL_BASE + 0x018) +#define SYSTEMCONTROL_DC4 MMIO32(SYSTEMCONTROL_BASE + 0x01C) +#define SYSTEMCONTROL_DC5 MMIO32(SYSTEMCONTROL_BASE + 0x020) +#define SYSTEMCONTROL_DC6 MMIO32(SYSTEMCONTROL_BASE + 0x024) +#define SYSTEMCONTROL_DC7 MMIO32(SYSTEMCONTROL_BASE + 0x028) +#define SYSTEMCONTROL_PBORCTL MMIO32(SYSTEMCONTROL_BASE + 0x030) +#define SYSTEMCONTROL_LDORCTL MMIO32(SYSTEMCONTROL_BASE + 0x034) +#define SYSTEMCONTROL_SRCR0 MMIO32(SYSTEMCONTROL_BASE + 0x040) +#define SYSTEMCONTROL_SRCR1 MMIO32(SYSTEMCONTROL_BASE + 0x044) +#define SYSTEMCONTROL_SRCR2 MMIO32(SYSTEMCONTROL_BASE + 0x048) +#define SYSTEMCONTROL_RIS MMIO32(SYSTEMCONTROL_BASE + 0x050) +#define SYSTEMCONTROL_IMC MMIO32(SYSTEMCONTROL_BASE + 0x054) +#define SYSTEMCONTROL_MISC MMIO32(SYSTEMCONTROL_BASE + 0x058) +#define SYSTEMCONTROL_RESC MMIO32(SYSTEMCONTROL_BASE + 0x05C) +#define SYSTEMCONTROL_RCC MMIO32(SYSTEMCONTROL_BASE + 0x060) +#define SYSTEMCONTROL_PLLCFG MMIO32(SYSTEMCONTROL_BASE + 0x064) +#define SYSTEMCONTROL_GPIOHBCTL MMIO32(SYSTEMCONTROL_BASE + 0x06C) +#define SYSTEMCONTROL_RCC2 MMIO32(SYSTEMCONTROL_BASE + 0x070) +#define SYSTEMCONTROL_MOSCCTL MMIO32(SYSTEMCONTROL_BASE + 0x07C) +#define SYSTEMCONTROL_RCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x100) +#define SYSTEMCONTROL_RCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x104) +#define SYSTEMCONTROL_RCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x108) +#define SYSTEMCONTROL_SCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x110) +#define SYSTEMCONTROL_SCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x114) +#define SYSTEMCONTROL_SCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x118) +#define SYSTEMCONTROL_DCGC0 MMIO32(SYSTEMCONTROL_BASE + 0x120) +#define SYSTEMCONTROL_DCGC1 MMIO32(SYSTEMCONTROL_BASE + 0x124) +#define SYSTEMCONTROL_DCGC2 MMIO32(SYSTEMCONTROL_BASE + 0x128) +#define SYSTEMCONTROL_DSLPCLKCFG MMIO32(SYSTEMCONTROL_BASE + 0x144) + +/**@}*/ + +#endif + |