diff options
Diffstat (limited to 'arch/arm/mach-ixp2000')
26 files changed, 3821 insertions, 0 deletions
diff --git a/arch/arm/mach-ixp2000/Kconfig b/arch/arm/mach-ixp2000/Kconfig new file mode 100644 index 00000000..08d2707f --- /dev/null +++ b/arch/arm/mach-ixp2000/Kconfig @@ -0,0 +1,72 @@ + +if ARCH_IXP2000 + +config ARCH_SUPPORTS_BIG_ENDIAN + bool + default y + +menu "Intel IXP2400/2800 Implementation Options" + +comment "IXP2400/2800 Platforms" + +config ARCH_ENP2611 + bool "Support Radisys ENP-2611" + help + Say 'Y' here if you want your kernel to support the Radisys + ENP2611 PCI network processing card. For more information on + this card, see <file:Documentation/arm/IXP2000>. + +config ARCH_IXDP2400 + bool "Support Intel IXDP2400" + help + Say 'Y' here if you want your kernel to support the Intel + IXDP2400 reference platform. For more information on + this platform, see <file:Documentation/arm/IXP2000>. + +config ARCH_IXDP2800 + bool "Support Intel IXDP2800" + help + Say 'Y' here if you want your kernel to support the Intel + IXDP2800 reference platform. For more information on + this platform, see <file:Documentation/arm/IXP2000>. + +config ARCH_IXDP2X00 + bool + depends on ARCH_IXDP2400 || ARCH_IXDP2800 + default y + +config ARCH_IXDP2401 + bool "Support Intel IXDP2401" + help + Say 'Y' here if you want your kernel to support the Intel + IXDP2401 reference platform. For more information on + this platform, see <file:Documentation/arm/IXP2000>. + +config ARCH_IXDP2801 + bool "Support Intel IXDP2801 and IXDP28x5" + help + Say 'Y' here if you want your kernel to support the Intel + IXDP2801/2805/2855 reference platforms. For more information on + this platform, see <file:Documentation/arm/IXP2000>. + +config MACH_IXDP28X5 + bool + depends on ARCH_IXDP2801 + default y + +config ARCH_IXDP2X01 + bool + depends on ARCH_IXDP2401 || ARCH_IXDP2801 + default y + +config IXP2000_SUPPORT_BROKEN_PCI_IO + bool "Support broken PCI I/O on older IXP2000s" + default y + help + Say 'N' here if you only intend to run your kernel on an + IXP2000 B0 or later model and do not need the PCI I/O + byteswap workaround. Say 'Y' otherwise. + +endmenu + +endif diff --git a/arch/arm/mach-ixp2000/Makefile b/arch/arm/mach-ixp2000/Makefile new file mode 100644 index 00000000..1e6139d4 --- /dev/null +++ b/arch/arm/mach-ixp2000/Makefile @@ -0,0 +1,14 @@ +# +# Makefile for the linux kernel. +# +obj-y := core.o pci.o +obj-m := +obj-n := +obj- := + +obj-$(CONFIG_ARCH_ENP2611) += enp2611.o +obj-$(CONFIG_ARCH_IXDP2400) += ixdp2400.o +obj-$(CONFIG_ARCH_IXDP2800) += ixdp2800.o +obj-$(CONFIG_ARCH_IXDP2X00) += ixdp2x00.o +obj-$(CONFIG_ARCH_IXDP2X01) += ixdp2x01.o + diff --git a/arch/arm/mach-ixp2000/Makefile.boot b/arch/arm/mach-ixp2000/Makefile.boot new file mode 100644 index 00000000..d84c5807 --- /dev/null +++ b/arch/arm/mach-ixp2000/Makefile.boot @@ -0,0 +1,3 @@ + zreladdr-y := 0x00008000 +params_phys-y := 0x00000100 + diff --git a/arch/arm/mach-ixp2000/core.c b/arch/arm/mach-ixp2000/core.c new file mode 100644 index 00000000..4068166c --- /dev/null +++ b/arch/arm/mach-ixp2000/core.c @@ -0,0 +1,516 @@ +/* + * arch/arm/mach-ixp2000/core.c + * + * Common routines used by all IXP2400/2800 based platforms. + * + * Author: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2004 (C) MontaVista Software, Inc. + * + * Based on work Copyright (C) 2002-2003 Intel Corporation + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/spinlock.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/irq.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/bitops.h> +#include <linux/serial_8250.h> +#include <linux/mm.h> + +#include <asm/types.h> +#include <asm/setup.h> +#include <asm/memory.h> +#include <mach/hardware.h> +#include <asm/irq.h> +#include <asm/system.h> +#include <asm/tlbflush.h> +#include <asm/pgtable.h> + +#include <asm/mach/map.h> +#include <asm/mach/time.h> +#include <asm/mach/irq.h> + +#include <mach/gpio.h> + +static DEFINE_SPINLOCK(ixp2000_slowport_lock); +static unsigned long ixp2000_slowport_irq_flags; + +/************************************************************************* + * Slowport access routines + *************************************************************************/ +void ixp2000_acquire_slowport(struct slowport_cfg *new_cfg, struct slowport_cfg *old_cfg) +{ + spin_lock_irqsave(&ixp2000_slowport_lock, ixp2000_slowport_irq_flags); + + old_cfg->CCR = *IXP2000_SLOWPORT_CCR; + old_cfg->WTC = *IXP2000_SLOWPORT_WTC2; + old_cfg->RTC = *IXP2000_SLOWPORT_RTC2; + old_cfg->PCR = *IXP2000_SLOWPORT_PCR; + old_cfg->ADC = *IXP2000_SLOWPORT_ADC; + + ixp2000_reg_write(IXP2000_SLOWPORT_CCR, new_cfg->CCR); + ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, new_cfg->WTC); + ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, new_cfg->RTC); + ixp2000_reg_write(IXP2000_SLOWPORT_PCR, new_cfg->PCR); + ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, new_cfg->ADC); +} + +void ixp2000_release_slowport(struct slowport_cfg *old_cfg) +{ + ixp2000_reg_write(IXP2000_SLOWPORT_CCR, old_cfg->CCR); + ixp2000_reg_write(IXP2000_SLOWPORT_WTC2, old_cfg->WTC); + ixp2000_reg_write(IXP2000_SLOWPORT_RTC2, old_cfg->RTC); + ixp2000_reg_write(IXP2000_SLOWPORT_PCR, old_cfg->PCR); + ixp2000_reg_wrb(IXP2000_SLOWPORT_ADC, old_cfg->ADC); + + spin_unlock_irqrestore(&ixp2000_slowport_lock, + ixp2000_slowport_irq_flags); +} + +/************************************************************************* + * Chip specific mappings shared by all IXP2000 systems + *************************************************************************/ +static struct map_desc ixp2000_io_desc[] __initdata = { + { + .virtual = IXP2000_CAP_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_CAP_PHYS_BASE), + .length = IXP2000_CAP_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_INTCTL_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_INTCTL_PHYS_BASE), + .length = IXP2000_INTCTL_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_PCI_CREG_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_PCI_CREG_PHYS_BASE), + .length = IXP2000_PCI_CREG_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_PCI_CSR_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_PCI_CSR_PHYS_BASE), + .length = IXP2000_PCI_CSR_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_MSF_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_MSF_PHYS_BASE), + .length = IXP2000_MSF_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_SCRATCH_RING_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_SCRATCH_RING_PHYS_BASE), + .length = IXP2000_SCRATCH_RING_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_SRAM0_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_SRAM0_PHYS_BASE), + .length = IXP2000_SRAM0_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_PCI_IO_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_PCI_IO_PHYS_BASE), + .length = IXP2000_PCI_IO_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_PCI_CFG0_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_PCI_CFG0_PHYS_BASE), + .length = IXP2000_PCI_CFG0_SIZE, + .type = MT_DEVICE, + }, { + .virtual = IXP2000_PCI_CFG1_VIRT_BASE, + .pfn = __phys_to_pfn(IXP2000_PCI_CFG1_PHYS_BASE), + .length = IXP2000_PCI_CFG1_SIZE, + .type = MT_DEVICE, + } +}; + +void __init ixp2000_map_io(void) +{ + iotable_init(ixp2000_io_desc, ARRAY_SIZE(ixp2000_io_desc)); + + /* Set slowport to 8-bit mode. */ + ixp2000_reg_wrb(IXP2000_SLOWPORT_FRM, 1); +} + + +/************************************************************************* + * Serial port support for IXP2000 + *************************************************************************/ +static struct plat_serial8250_port ixp2000_serial_port[] = { + { + .mapbase = IXP2000_UART_PHYS_BASE, + .membase = (char *)(IXP2000_UART_VIRT_BASE + 3), + .irq = IRQ_IXP2000_UART, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM, + .regshift = 2, + .uartclk = 50000000, + }, + { }, +}; + +static struct resource ixp2000_uart_resource = { + .start = IXP2000_UART_PHYS_BASE, + .end = IXP2000_UART_PHYS_BASE + 0x1f, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixp2000_serial_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = ixp2000_serial_port, + }, + .num_resources = 1, + .resource = &ixp2000_uart_resource, +}; + +void __init ixp2000_uart_init(void) +{ + platform_device_register(&ixp2000_serial_device); +} + + +/************************************************************************* + * Timer-tick functions for IXP2000 + *************************************************************************/ +static unsigned ticks_per_jiffy; +static unsigned ticks_per_usec; +static unsigned next_jiffy_time; +static volatile unsigned long *missing_jiffy_timer_csr; + +unsigned long ixp2000_gettimeoffset (void) +{ + unsigned long offset; + + offset = next_jiffy_time - *missing_jiffy_timer_csr; + + return offset / ticks_per_usec; +} + +static irqreturn_t ixp2000_timer_interrupt(int irq, void *dev_id) +{ + /* clear timer 1 */ + ixp2000_reg_wrb(IXP2000_T1_CLR, 1); + + while ((signed long)(next_jiffy_time - *missing_jiffy_timer_csr) + >= ticks_per_jiffy) { + timer_tick(); + next_jiffy_time -= ticks_per_jiffy; + } + + return IRQ_HANDLED; +} + +static struct irqaction ixp2000_timer_irq = { + .name = "IXP2000 Timer Tick", + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL, + .handler = ixp2000_timer_interrupt, +}; + +void __init ixp2000_init_time(unsigned long tick_rate) +{ + ticks_per_jiffy = (tick_rate + HZ/2) / HZ; + ticks_per_usec = tick_rate / 1000000; + + /* + * We use timer 1 as our timer interrupt. + */ + ixp2000_reg_write(IXP2000_T1_CLR, 0); + ixp2000_reg_write(IXP2000_T1_CLD, ticks_per_jiffy - 1); + ixp2000_reg_write(IXP2000_T1_CTL, (1 << 7)); + + /* + * We use a second timer as a monotonic counter for tracking + * missed jiffies. The IXP2000 has four timers, but if we're + * on an A-step IXP2800, timer 2 and 3 don't work, so on those + * chips we use timer 4. Timer 4 is the only timer that can + * be used for the watchdog, so we use timer 2 if we're on a + * non-buggy chip. + */ + if ((*IXP2000_PRODUCT_ID & 0x001ffef0) == 0x00000000) { + printk(KERN_INFO "Enabling IXP2800 erratum #25 workaround\n"); + + ixp2000_reg_write(IXP2000_T4_CLR, 0); + ixp2000_reg_write(IXP2000_T4_CLD, -1); + ixp2000_reg_wrb(IXP2000_T4_CTL, (1 << 7)); + missing_jiffy_timer_csr = IXP2000_T4_CSR; + } else { + ixp2000_reg_write(IXP2000_T2_CLR, 0); + ixp2000_reg_write(IXP2000_T2_CLD, -1); + ixp2000_reg_wrb(IXP2000_T2_CTL, (1 << 7)); + missing_jiffy_timer_csr = IXP2000_T2_CSR; + } + next_jiffy_time = 0xffffffff; + + /* register for interrupt */ + setup_irq(IRQ_IXP2000_TIMER1, &ixp2000_timer_irq); +} + +/************************************************************************* + * GPIO helpers + *************************************************************************/ +static unsigned long GPIO_IRQ_falling_edge; +static unsigned long GPIO_IRQ_rising_edge; +static unsigned long GPIO_IRQ_level_low; +static unsigned long GPIO_IRQ_level_high; + +static void update_gpio_int_csrs(void) +{ + ixp2000_reg_write(IXP2000_GPIO_FEDR, GPIO_IRQ_falling_edge); + ixp2000_reg_write(IXP2000_GPIO_REDR, GPIO_IRQ_rising_edge); + ixp2000_reg_write(IXP2000_GPIO_LSLR, GPIO_IRQ_level_low); + ixp2000_reg_wrb(IXP2000_GPIO_LSHR, GPIO_IRQ_level_high); +} + +void gpio_line_config(int line, int direction) +{ + unsigned long flags; + + local_irq_save(flags); + if (direction == GPIO_OUT) { + /* if it's an output, it ain't an interrupt anymore */ + GPIO_IRQ_falling_edge &= ~(1 << line); + GPIO_IRQ_rising_edge &= ~(1 << line); + GPIO_IRQ_level_low &= ~(1 << line); + GPIO_IRQ_level_high &= ~(1 << line); + update_gpio_int_csrs(); + + ixp2000_reg_wrb(IXP2000_GPIO_PDSR, 1 << line); + } else if (direction == GPIO_IN) { + ixp2000_reg_wrb(IXP2000_GPIO_PDCR, 1 << line); + } + local_irq_restore(flags); +} +EXPORT_SYMBOL(gpio_line_config); + + +/************************************************************************* + * IRQ handling IXP2000 + *************************************************************************/ +static void ixp2000_GPIO_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int i; + unsigned long status = *IXP2000_GPIO_INST; + + for (i = 0; i <= 7; i++) { + if (status & (1<<i)) { + generic_handle_irq(i + IRQ_IXP2000_GPIO0); + } + } +} + +static int ixp2000_GPIO_irq_type(struct irq_data *d, unsigned int type) +{ + int line = d->irq - IRQ_IXP2000_GPIO0; + + /* + * First, configure this GPIO line as an input. + */ + ixp2000_reg_write(IXP2000_GPIO_PDCR, 1 << line); + + /* + * Then, set the proper trigger type. + */ + if (type & IRQ_TYPE_EDGE_FALLING) + GPIO_IRQ_falling_edge |= 1 << line; + else + GPIO_IRQ_falling_edge &= ~(1 << line); + if (type & IRQ_TYPE_EDGE_RISING) + GPIO_IRQ_rising_edge |= 1 << line; + else + GPIO_IRQ_rising_edge &= ~(1 << line); + if (type & IRQ_TYPE_LEVEL_LOW) + GPIO_IRQ_level_low |= 1 << line; + else + GPIO_IRQ_level_low &= ~(1 << line); + if (type & IRQ_TYPE_LEVEL_HIGH) + GPIO_IRQ_level_high |= 1 << line; + else + GPIO_IRQ_level_high &= ~(1 << line); + update_gpio_int_csrs(); + + return 0; +} + +static void ixp2000_GPIO_irq_mask_ack(struct irq_data *d) +{ + unsigned int irq = d->irq; + + ixp2000_reg_write(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); + + ixp2000_reg_write(IXP2000_GPIO_EDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); + ixp2000_reg_write(IXP2000_GPIO_LDSR, (1 << (irq - IRQ_IXP2000_GPIO0))); + ixp2000_reg_wrb(IXP2000_GPIO_INST, (1 << (irq - IRQ_IXP2000_GPIO0))); +} + +static void ixp2000_GPIO_irq_mask(struct irq_data *d) +{ + unsigned int irq = d->irq; + + ixp2000_reg_wrb(IXP2000_GPIO_INCR, (1 << (irq - IRQ_IXP2000_GPIO0))); +} + +static void ixp2000_GPIO_irq_unmask(struct irq_data *d) +{ + unsigned int irq = d->irq; + + ixp2000_reg_write(IXP2000_GPIO_INSR, (1 << (irq - IRQ_IXP2000_GPIO0))); +} + +static struct irq_chip ixp2000_GPIO_irq_chip = { + .irq_ack = ixp2000_GPIO_irq_mask_ack, + .irq_mask = ixp2000_GPIO_irq_mask, + .irq_unmask = ixp2000_GPIO_irq_unmask, + .irq_set_type = ixp2000_GPIO_irq_type, +}; + +static void ixp2000_pci_irq_mask(struct irq_data *d) +{ + unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; + if (d->irq == IRQ_IXP2000_PCIA) + ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 26))); + else if (d->irq == IRQ_IXP2000_PCIB) + ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, (temp & ~(1 << 27))); +} + +static void ixp2000_pci_irq_unmask(struct irq_data *d) +{ + unsigned long temp = *IXP2000_PCI_XSCALE_INT_ENABLE; + if (d->irq == IRQ_IXP2000_PCIA) + ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 26))); + else if (d->irq == IRQ_IXP2000_PCIB) + ixp2000_reg_write(IXP2000_PCI_XSCALE_INT_ENABLE, (temp | (1 << 27))); +} + +/* + * Error interrupts. These are used extensively by the microengine drivers + */ +static void ixp2000_err_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + int i; + unsigned long status = *IXP2000_IRQ_ERR_STATUS; + + for(i = 31; i >= 0; i--) { + if(status & (1 << i)) { + generic_handle_irq(IRQ_IXP2000_DRAM0_MIN_ERR + i); + } + } +} + +static void ixp2000_err_irq_mask(struct irq_data *d) +{ + ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_CLR, + (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); +} + +static void ixp2000_err_irq_unmask(struct irq_data *d) +{ + ixp2000_reg_write(IXP2000_IRQ_ERR_ENABLE_SET, + (1 << (d->irq - IRQ_IXP2000_DRAM0_MIN_ERR))); +} + +static struct irq_chip ixp2000_err_irq_chip = { + .irq_ack = ixp2000_err_irq_mask, + .irq_mask = ixp2000_err_irq_mask, + .irq_unmask = ixp2000_err_irq_unmask +}; + +static struct irq_chip ixp2000_pci_irq_chip = { + .irq_ack = ixp2000_pci_irq_mask, + .irq_mask = ixp2000_pci_irq_mask, + .irq_unmask = ixp2000_pci_irq_unmask +}; + +static void ixp2000_irq_mask(struct irq_data *d) +{ + ixp2000_reg_wrb(IXP2000_IRQ_ENABLE_CLR, (1 << d->irq)); +} + +static void ixp2000_irq_unmask(struct irq_data *d) +{ + ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << d->irq)); +} + +static struct irq_chip ixp2000_irq_chip = { + .irq_ack = ixp2000_irq_mask, + .irq_mask = ixp2000_irq_mask, + .irq_unmask = ixp2000_irq_unmask +}; + +void __init ixp2000_init_irq(void) +{ + int irq; + + /* + * Mask all sources + */ + ixp2000_reg_write(IXP2000_IRQ_ENABLE_CLR, 0xffffffff); + ixp2000_reg_write(IXP2000_FIQ_ENABLE_CLR, 0xffffffff); + + /* clear all GPIO edge/level detects */ + ixp2000_reg_write(IXP2000_GPIO_REDR, 0); + ixp2000_reg_write(IXP2000_GPIO_FEDR, 0); + ixp2000_reg_write(IXP2000_GPIO_LSHR, 0); + ixp2000_reg_write(IXP2000_GPIO_LSLR, 0); + ixp2000_reg_write(IXP2000_GPIO_INCR, -1); + + /* clear PCI interrupt sources */ + ixp2000_reg_wrb(IXP2000_PCI_XSCALE_INT_ENABLE, 0); + + /* + * Certain bits in the IRQ status register of the + * IXP2000 are reserved. Instead of trying to map + * things non 1:1 from bit position to IRQ number, + * we mark the reserved IRQs as invalid. This makes + * our mask/unmask code much simpler. + */ + for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { + if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { + irq_set_chip_and_handler(irq, &ixp2000_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } else set_irq_flags(irq, 0); + } + + for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { + if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & + IXP2000_VALID_ERR_IRQ_MASK) { + irq_set_chip_and_handler(irq, &ixp2000_err_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + else + set_irq_flags(irq, 0); + } + irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); + + for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { + irq_set_chip_and_handler(irq, &ixp2000_GPIO_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); + + /* + * Enable PCI irqs. The actual PCI[AB] decoding is done in + * entry-macro.S, so we don't need a chained handler for the + * PCI interrupt source. + */ + ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); + for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { + irq_set_chip_and_handler(irq, &ixp2000_pci_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } +} + diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c new file mode 100644 index 00000000..88663ab1 --- /dev/null +++ b/arch/arm/mach-ixp2000/enp2611.c @@ -0,0 +1,263 @@ +/* + * arch/arm/mach-ixp2000/enp2611.c + * + * Radisys ENP-2611 support. + * + * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The + * original version carries the following notices: + * + * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002-2003 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/bitops.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +#include <asm/mach/pci.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> + +/************************************************************************* + * ENP-2611 timer tick configuration + *************************************************************************/ +static void __init enp2611_timer_init(void) +{ + ixp2000_init_time(50 * 1000 * 1000); +} + +static struct sys_timer enp2611_timer = { + .init = enp2611_timer_init, + .offset = ixp2000_gettimeoffset, +}; + + +/************************************************************************* + * ENP-2611 I/O + *************************************************************************/ +static struct map_desc enp2611_io_desc[] __initdata = { + { + .virtual = ENP2611_CALEB_VIRT_BASE, + .pfn = __phys_to_pfn(ENP2611_CALEB_PHYS_BASE), + .length = ENP2611_CALEB_SIZE, + .type = MT_DEVICE, + }, { + .virtual = ENP2611_PM3386_0_VIRT_BASE, + .pfn = __phys_to_pfn(ENP2611_PM3386_0_PHYS_BASE), + .length = ENP2611_PM3386_0_SIZE, + .type = MT_DEVICE, + }, { + .virtual = ENP2611_PM3386_1_VIRT_BASE, + .pfn = __phys_to_pfn(ENP2611_PM3386_1_PHYS_BASE), + .length = ENP2611_PM3386_1_SIZE, + .type = MT_DEVICE, + } +}; + +void __init enp2611_map_io(void) +{ + ixp2000_map_io(); + iotable_init(enp2611_io_desc, ARRAY_SIZE(enp2611_io_desc)); +} + + +/************************************************************************* + * ENP-2611 PCI + *************************************************************************/ +static int enp2611_pci_setup(int nr, struct pci_sys_data *sys) +{ + sys->mem_offset = 0xe0000000; + ixp2000_pci_setup(nr, sys); + return 1; +} + +static void __init enp2611_pci_preinit(void) +{ + ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); + ixp2000_pci_preinit(); + pcibios_setup("firmware"); +} + +static inline int enp2611_pci_valid_device(struct pci_bus *bus, + unsigned int devfn) +{ + /* The 82559 ethernet controller appears at both PCI:1:0:0 and + * PCI:1:2:0, so let's pretend the second one isn't there. + */ + if (bus->number == 0x01 && devfn == 0x10) + return 0; + + return 1; +} + +static int enp2611_pci_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *value) +{ + if (enp2611_pci_valid_device(bus, devfn)) + return ixp2000_pci_read_config(bus, devfn, where, size, value); + + return PCIBIOS_DEVICE_NOT_FOUND; +} + +static int enp2611_pci_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 value) +{ + if (enp2611_pci_valid_device(bus, devfn)) + return ixp2000_pci_write_config(bus, devfn, where, size, value); + + return PCIBIOS_DEVICE_NOT_FOUND; +} + +static struct pci_ops enp2611_pci_ops = { + .read = enp2611_pci_read_config, + .write = enp2611_pci_write_config +}; + +static struct pci_bus * __init enp2611_pci_scan_bus(int nr, + struct pci_sys_data *sys) +{ + return pci_scan_bus(sys->busnr, &enp2611_pci_ops, sys); +} + +static int __init enp2611_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq; + + if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 0) { + /* IXP2400. */ + irq = IRQ_IXP2000_PCIA; + } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 1) { + /* 21555 non-transparent bridge. */ + irq = IRQ_IXP2000_PCIB; + } else if (dev->bus->number == 0 && PCI_SLOT(dev->devfn) == 4) { + /* PCI2050B transparent bridge. */ + irq = -1; + } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 0) { + /* 82559 ethernet. */ + irq = IRQ_IXP2000_PCIA; + } else if (dev->bus->number == 1 && PCI_SLOT(dev->devfn) == 1) { + /* SPI-3 option board. */ + irq = IRQ_IXP2000_PCIB; + } else { + printk(KERN_ERR "enp2611_pci_map_irq() called for unknown " + "device PCI:%d:%d:%d\n", dev->bus->number, + PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); + irq = -1; + } + + return irq; +} + +struct hw_pci enp2611_pci __initdata = { + .nr_controllers = 1, + .setup = enp2611_pci_setup, + .preinit = enp2611_pci_preinit, + .scan = enp2611_pci_scan_bus, + .map_irq = enp2611_pci_map_irq, +}; + +int __init enp2611_pci_init(void) +{ + if (machine_is_enp2611()) + pci_common_init(&enp2611_pci); + + return 0; +} + +subsys_initcall(enp2611_pci_init); + + +/************************************************************************* + * ENP-2611 Machine Initialization + *************************************************************************/ +static struct flash_platform_data enp2611_flash_platform_data = { + .map_name = "cfi_probe", + .width = 1, +}; + +static struct ixp2000_flash_data enp2611_flash_data = { + .platform_data = &enp2611_flash_platform_data, + .nr_banks = 1 +}; + +static struct resource enp2611_flash_resource = { + .start = 0xc4000000, + .end = 0xc4000000 + 0x00ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device enp2611_flash = { + .name = "IXP2000-Flash", + .id = 0, + .dev = { + .platform_data = &enp2611_flash_data, + }, + .num_resources = 1, + .resource = &enp2611_flash_resource, +}; + +static struct ixp2000_i2c_pins enp2611_i2c_gpio_pins = { + .sda_pin = ENP2611_GPIO_SDA, + .scl_pin = ENP2611_GPIO_SCL, +}; + +static struct platform_device enp2611_i2c_controller = { + .name = "IXP2000-I2C", + .id = 0, + .dev = { + .platform_data = &enp2611_i2c_gpio_pins + }, + .num_resources = 0 +}; + +static struct platform_device *enp2611_devices[] __initdata = { + &enp2611_flash, + &enp2611_i2c_controller +}; + +static void __init enp2611_init_machine(void) +{ + platform_add_devices(enp2611_devices, ARRAY_SIZE(enp2611_devices)); + ixp2000_uart_init(); +} + + +MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board") + /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ + .boot_params = 0x00000100, + .map_io = enp2611_map_io, + .init_irq = ixp2000_init_irq, + .timer = &enp2611_timer, + .init_machine = enp2611_init_machine, +MACHINE_END + + diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S new file mode 100644 index 00000000..0ef533b2 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S @@ -0,0 +1,25 @@ +/* arch/arm/mach-ixp2000/include/mach/debug-macro.S + * + * Debugging macro include header + * + * Copyright (C) 1994-1999 Russell King + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * +*/ + + .macro addruart, rp, rv + mov \rp, #0x00030000 +#ifdef __ARMEB__ + orr \rp, \rp, #0x00000003 +#endif + orr \rv, \rp, #0xfe000000 @ virtual base + orr \rv, \rv, #0x00f00000 + orr \rp, \rp, #0xc0000000 @ Physical base + .endm + +#define UART_SHIFT 2 +#include <asm/hardware/debug-8250.S> diff --git a/arch/arm/mach-ixp2000/include/mach/enp2611.h b/arch/arm/mach-ixp2000/include/mach/enp2611.h new file mode 100644 index 00000000..9ce36900 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/enp2611.h @@ -0,0 +1,46 @@ +/* + * arch/arm/mach-ixp2000/include/mach/enp2611.h + * + * Register and other defines for Radisys ENP-2611 + * + * Created 2004 by Lennert Buytenhek from the ixdp2x01 code. The + * original version carries the following notices: + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ENP2611_H +#define __ENP2611_H + +#define ENP2611_CALEB_PHYS_BASE 0xc5000000 +#define ENP2611_CALEB_VIRT_BASE 0xfe000000 +#define ENP2611_CALEB_SIZE 0x00100000 + +#define ENP2611_PM3386_0_PHYS_BASE 0xc6000000 +#define ENP2611_PM3386_0_VIRT_BASE 0xfe100000 +#define ENP2611_PM3386_0_SIZE 0x00100000 + +#define ENP2611_PM3386_1_PHYS_BASE 0xc6400000 +#define ENP2611_PM3386_1_VIRT_BASE 0xfe200000 +#define ENP2611_PM3386_1_SIZE 0x00100000 + +#define ENP2611_GPIO_SCL 7 +#define ENP2611_GPIO_SDA 6 + +#define IRQ_ENP2611_THERMAL IRQ_IXP2000_GPIO4 +#define IRQ_ENP2611_OPTION_BOARD IRQ_IXP2000_GPIO3 +#define IRQ_ENP2611_CALEB IRQ_IXP2000_GPIO2 +#define IRQ_ENP2611_PM3386_1 IRQ_IXP2000_GPIO1 +#define IRQ_ENP2611_PM3386_0 IRQ_IXP2000_GPIO0 + + +#endif diff --git a/arch/arm/mach-ixp2000/include/mach/entry-macro.S b/arch/arm/mach-ixp2000/include/mach/entry-macro.S new file mode 100644 index 00000000..5850ffc8 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/entry-macro.S @@ -0,0 +1,60 @@ +/* + * arch/arm/mach-ixp2000/include/mach/entry-macro.S + * + * Low-level IRQ helper macros for IXP2000-based platforms + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ +#include <mach/irqs.h> + + .macro disable_fiq + .endm + + .macro get_irqnr_preamble, base, tmp + .endm + + .macro arch_ret_to_user, tmp1, tmp2 + .endm + + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp + + mov \irqnr, #0x0 @clear out irqnr as default + mov \base, #0xfe000000 + orr \base, \base, #0x00e00000 + orr \base, \base, #0x08 + ldr \irqstat, [\base] @ get interrupts + + cmp \irqstat, #0 + beq 1001f + + clz \irqnr, \irqstat + mov \base, #31 + subs \irqnr, \base, \irqnr + + /* + * We handle PCIA and PCIB here so we don't have an + * extra layer of code just to check these two bits. + */ + cmp \irqnr, #IRQ_IXP2000_PCI + bne 1001f + + mov \base, #0xfe000000 + orr \base, \base, #0x00c00000 + orr \base, \base, #0x00000100 + orr \base, \base, #0x00000058 + ldr \irqstat, [\base] + + mov \tmp, #(1<<26) + tst \irqstat, \tmp + movne \irqnr, #IRQ_IXP2000_PCIA + bne 1001f + + mov \tmp, #(1<<27) + tst \irqstat, \tmp + movne \irqnr, #IRQ_IXP2000_PCIB + +1001: + .endm + diff --git a/arch/arm/mach-ixp2000/include/mach/gpio.h b/arch/arm/mach-ixp2000/include/mach/gpio.h new file mode 100644 index 00000000..4a88d2c3 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/gpio.h @@ -0,0 +1,48 @@ +/* + * arch/arm/mach-ixp2000/include/mach/gpio.h + * + * Copyright (C) 2002 Intel Corporation. + * + * This program is free software, you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +/* + * IXP2000 GPIO in/out, edge/level detection for IRQs: + * IRQs are generated on Falling-edge, Rising-Edge, Level-low, Level-High + * or both Falling-edge and Rising-edge. + * This must be called *before* the corresponding IRQ is registerd. + * Use this instead of directly setting the GPIO registers. + * GPIOs may also be used as GPIOs (e.g. for emulating i2c/smb) + */ +#ifndef __ASM_ARCH_GPIO_H +#define __ASM_ARCH_GPIO_H + +#ifndef __ASSEMBLY__ + +#define GPIO_IN 0 +#define GPIO_OUT 1 + +#define IXP2000_GPIO_LOW 0 +#define IXP2000_GPIO_HIGH 1 + +extern void gpio_line_config(int line, int direction); + +static inline int gpio_line_get(int line) +{ + return (((*IXP2000_GPIO_PLR) >> line) & 1); +} + +static inline void gpio_line_set(int line, int value) +{ + if (value == IXP2000_GPIO_HIGH) { + ixp2000_reg_write(IXP2000_GPIO_POSR, 1 << line); + } else if (value == IXP2000_GPIO_LOW) { + ixp2000_reg_write(IXP2000_GPIO_POCR, 1 << line); + } +} + +#endif /* !__ASSEMBLY__ */ + +#endif /* ASM_ARCH_IXP2000_GPIO_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/hardware.h b/arch/arm/mach-ixp2000/include/mach/hardware.h new file mode 100644 index 00000000..f033de4e --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/hardware.h @@ -0,0 +1,44 @@ +/* + * arch/arm/mach-ixp2000/include/mach/hardware.h + * + * Hardware definitions for IXP2400/2800 based systems + * + * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> + * + * Maintainer: Deepak Saxena <dsaxena@mvista.com> + * + * Copyright (C) 2001-2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_HARDWARE_H__ +#define __ASM_ARCH_HARDWARE_H__ + +/* + * This needs to be platform-specific? + */ +#define PCIBIOS_MIN_IO 0x00000000 +#define PCIBIOS_MIN_MEM 0x00000000 + +#include "ixp2000-regs.h" /* Chipset Registers */ + +#define pcibios_assign_all_busses() 0 + +/* + * Platform helper functions + */ +#include "platform.h" + +/* + * Platform-specific bits + */ +#include "enp2611.h" /* ENP-2611 */ +#include "ixdp2x00.h" /* IXDP2400/2800 */ +#include "ixdp2x01.h" /* IXDP2401/2801 */ + +#endif /* _ASM_ARCH_HARDWARE_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/io.h b/arch/arm/mach-ixp2000/include/mach/io.h new file mode 100644 index 00000000..859e5849 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/io.h @@ -0,0 +1,134 @@ +/* + * arch/arm/mach-ixp2000/include/mach/io.h + * + * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyrgiht (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef __ASM_ARM_ARCH_IO_H +#define __ASM_ARM_ARCH_IO_H + +#include <mach/hardware.h> + +#define IO_SPACE_LIMIT 0xffffffff +#define __mem_pci(a) (a) + +/* + * The A? revisions of the IXP2000s assert byte lanes for PCI I/O + * transactions the other way round (MEM transactions don't have this + * issue), so if we want to support those models, we need to override + * the standard I/O functions. + * + * B0 and later have a bit that can be set to 1 to get the proper + * behavior for I/O transactions, which then allows us to use the + * standard I/O functions. This is what we do if the user does not + * explicitly ask for support for pre-B0. + */ +#ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO +#define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) + +#define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3) +#define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2) + +#define outb(v,p) __raw_writeb((v),alignb(___io(p))) +#define outw(v,p) __raw_writew((v),alignw(___io(p))) +#define outl(v,p) __raw_writel((v),___io(p)) + +#define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; }) +#define inw(p) \ + ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; }) +#define inl(p) \ + ({ unsigned int __v = (__raw_readl(___io(p))); __v; }) + +#define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l) +#define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l) +#define outsl(p,d,l) __raw_writesl(___io(p),d,l) + +#define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l) +#define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l) +#define insl(p,d,l) __raw_readsl(___io(p),d,l) + +#define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE) + +#define ioread8(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readb(alignb(p)); \ + } else { \ + __v = __raw_readb(p); \ + } \ + \ + __v; \ + }) \ + +#define ioread16(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readw(alignw(p)); \ + } else { \ + __v = le16_to_cpu(__raw_readw(p)); \ + } \ + \ + __v; \ + }) + +#define ioread32(p) \ + ({ \ + unsigned int __v; \ + \ + if (__is_io_address(p)) { \ + __v = __raw_readl(p); \ + } else { \ + __v = le32_to_cpu(__raw_readl(p)); \ + } \ + \ + __v; \ + }) + +#define iowrite8(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writeb((v), alignb(p)); \ + } else { \ + __raw_writeb((v), p); \ + } \ + }) + +#define iowrite16(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writew((v), alignw(p)); \ + } else { \ + __raw_writew(cpu_to_le16(v), p); \ + } \ + }) + +#define iowrite32(v,p) \ + ({ \ + if (__is_io_address(p)) { \ + __raw_writel((v), p); \ + } else { \ + __raw_writel(cpu_to_le32(v), p); \ + } \ + }) + +#define ioport_map(port, nr) ___io(port) + +#define ioport_unmap(addr) +#else +#define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE)) +#endif + + +#endif diff --git a/arch/arm/mach-ixp2000/include/mach/irqs.h b/arch/arm/mach-ixp2000/include/mach/irqs.h new file mode 100644 index 00000000..bee96bca --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/irqs.h @@ -0,0 +1,207 @@ +/* + * arch/arm/mach-ixp2000/include/mach/irqs.h + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#ifndef _IRQS_H +#define _IRQS_H + +/* + * Do NOT add #ifdef MACHINE_FOO in here. + * Simpy add your machine IRQs here and increase NR_IRQS if needed to + * hold your machine's IRQ table. + */ + +/* + * Some interrupt numbers go unused b/c the IRQ mask/ummask/status + * register has those bit reserved. We just mark those interrupts + * as invalid and this allows us to do mask/unmask with a single + * shift operation instead of having to map the IRQ number to + * a HW IRQ number. + */ +#define IRQ_IXP2000_SOFT_INT 0 /* soft interrupt */ +#define IRQ_IXP2000_ERRSUM 1 /* OR of all bits in ErrorStatus reg*/ +#define IRQ_IXP2000_UART 2 +#define IRQ_IXP2000_GPIO 3 +#define IRQ_IXP2000_TIMER1 4 +#define IRQ_IXP2000_TIMER2 5 +#define IRQ_IXP2000_TIMER3 6 +#define IRQ_IXP2000_TIMER4 7 +#define IRQ_IXP2000_PMU 8 +#define IRQ_IXP2000_SPF 9 /* Slow port framer IRQ */ +#define IRQ_IXP2000_DMA1 10 +#define IRQ_IXP2000_DMA2 11 +#define IRQ_IXP2000_DMA3 12 +#define IRQ_IXP2000_PCI_DOORBELL 13 +#define IRQ_IXP2000_ME_ATTN 14 +#define IRQ_IXP2000_PCI 15 /* PCI INTA or INTB */ +#define IRQ_IXP2000_THDA0 16 /* thread 0-31A */ +#define IRQ_IXP2000_THDA1 17 /* thread 32-63A, IXP2800 only */ +#define IRQ_IXP2000_THDA2 18 /* thread 64-95A */ +#define IRQ_IXP2000_THDA3 19 /* thread 96-127A, IXP2800 only */ +#define IRQ_IXP2000_THDB0 24 /* thread 0-31B */ +#define IRQ_IXP2000_THDB1 25 /* thread 32-63B, IXP2800 only */ +#define IRQ_IXP2000_THDB2 26 /* thread 64-95B */ +#define IRQ_IXP2000_THDB3 27 /* thread 96-127B, IXP2800 only */ + +/* define generic GPIOs */ +#define IRQ_IXP2000_GPIO0 32 +#define IRQ_IXP2000_GPIO1 33 +#define IRQ_IXP2000_GPIO2 34 +#define IRQ_IXP2000_GPIO3 35 +#define IRQ_IXP2000_GPIO4 36 +#define IRQ_IXP2000_GPIO5 37 +#define IRQ_IXP2000_GPIO6 38 +#define IRQ_IXP2000_GPIO7 39 + +/* split off the 2 PCI sources */ +#define IRQ_IXP2000_PCIA 40 +#define IRQ_IXP2000_PCIB 41 + +/* Int sources from IRQ_ERROR_STATUS */ +#define IRQ_IXP2000_DRAM0_MIN_ERR 42 +#define IRQ_IXP2000_DRAM0_MAJ_ERR 43 +#define IRQ_IXP2000_DRAM1_MIN_ERR 44 +#define IRQ_IXP2000_DRAM1_MAJ_ERR 45 +#define IRQ_IXP2000_DRAM2_MIN_ERR 46 +#define IRQ_IXP2000_DRAM2_MAJ_ERR 47 +/* 48-57 reserved */ +#define IRQ_IXP2000_SRAM0_ERR 58 +#define IRQ_IXP2000_SRAM1_ERR 59 +#define IRQ_IXP2000_SRAM2_ERR 60 +#define IRQ_IXP2000_SRAM3_ERR 61 +/* 62-65 reserved */ +#define IRQ_IXP2000_MEDIA_ERR 66 +#define IRQ_IXP2000_PCI_ERR 67 +#define IRQ_IXP2000_SP_INT 68 + +#define NR_IXP2000_IRQS 69 + +#define IXP2000_BOARD_IRQ(x) (NR_IXP2000_IRQS + (x)) + +#define IXP2000_BOARD_IRQ_MASK(irq) (1 << (irq - NR_IXP2000_IRQS)) + +#define IXP2000_ERR_IRQ_MASK(irq) ( 1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) +#define IXP2000_VALID_ERR_IRQ_MASK (\ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM0_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM1_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MIN_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_DRAM2_MAJ_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM0_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM1_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM2_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SRAM3_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_MEDIA_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_PCI_ERR) | \ + IXP2000_ERR_IRQ_MASK(IRQ_IXP2000_SP_INT) ) + +/* + * This allows for all the on-chip sources plus up to 32 CPLD based + * IRQs. Should be more than enough. + */ +#define IXP2000_BOARD_IRQS 32 +#define NR_IRQS (NR_IXP2000_IRQS + IXP2000_BOARD_IRQS) + + +/* + * IXDP2400 specific IRQs + */ +#define IRQ_IXDP2400_INGRESS_NPU IXP2000_BOARD_IRQ(0) +#define IRQ_IXDP2400_ENET IXP2000_BOARD_IRQ(1) +#define IRQ_IXDP2400_MEDIA_PCI IXP2000_BOARD_IRQ(2) +#define IRQ_IXDP2400_MEDIA_SP IXP2000_BOARD_IRQ(3) +#define IRQ_IXDP2400_SF_PCI IXP2000_BOARD_IRQ(4) +#define IRQ_IXDP2400_SF_SP IXP2000_BOARD_IRQ(5) +#define IRQ_IXDP2400_PMC IXP2000_BOARD_IRQ(6) +#define IRQ_IXDP2400_TVM IXP2000_BOARD_IRQ(7) + +#define NR_IXDP2400_IRQS ((IRQ_IXDP2400_TVM)+1) +#define IXDP2400_NR_IRQS NR_IXDP2400_IRQS - NR_IXP2000_IRQS + +/* IXDP2800 specific IRQs */ +#define IRQ_IXDP2800_EGRESS_ENET IXP2000_BOARD_IRQ(0) +#define IRQ_IXDP2800_INGRESS_NPU IXP2000_BOARD_IRQ(1) +#define IRQ_IXDP2800_PMC IXP2000_BOARD_IRQ(2) +#define IRQ_IXDP2800_FABRIC_PCI IXP2000_BOARD_IRQ(3) +#define IRQ_IXDP2800_FABRIC IXP2000_BOARD_IRQ(4) +#define IRQ_IXDP2800_MEDIA IXP2000_BOARD_IRQ(5) + +#define NR_IXDP2800_IRQS ((IRQ_IXDP2800_MEDIA)+1) +#define IXDP2800_NR_IRQS NR_IXDP2800_IRQS - NR_IXP2000_IRQS + +/* + * IRQs on both IXDP2x01 boards + */ +#define IRQ_IXDP2X01_SPCI_DB_0 IXP2000_BOARD_IRQ(2) +#define IRQ_IXDP2X01_SPCI_DB_1 IXP2000_BOARD_IRQ(3) +#define IRQ_IXDP2X01_SPCI_PMC_INTA IXP2000_BOARD_IRQ(4) +#define IRQ_IXDP2X01_SPCI_PMC_INTB IXP2000_BOARD_IRQ(5) +#define IRQ_IXDP2X01_SPCI_PMC_INTC IXP2000_BOARD_IRQ(6) +#define IRQ_IXDP2X01_SPCI_PMC_INTD IXP2000_BOARD_IRQ(7) +#define IRQ_IXDP2X01_SPCI_FIC_INT IXP2000_BOARD_IRQ(8) +#define IRQ_IXDP2X01_IPMI_FROM IXP2000_BOARD_IRQ(16) +#define IRQ_IXDP2X01_125US IXP2000_BOARD_IRQ(17) +#define IRQ_IXDP2X01_DB_0_ADD IXP2000_BOARD_IRQ(18) +#define IRQ_IXDP2X01_DB_1_ADD IXP2000_BOARD_IRQ(19) +#define IRQ_IXDP2X01_UART1 IXP2000_BOARD_IRQ(21) +#define IRQ_IXDP2X01_UART2 IXP2000_BOARD_IRQ(22) +#define IRQ_IXDP2X01_FIC_ADD_INT IXP2000_BOARD_IRQ(24) +#define IRQ_IXDP2X01_CS8900 IXP2000_BOARD_IRQ(25) +#define IRQ_IXDP2X01_BBSRAM IXP2000_BOARD_IRQ(26) + +#define IXDP2X01_VALID_IRQ_MASK ( \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_0) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_DB_1) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTA) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTB) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTC) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_PMC_INTD) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_SPCI_FIC_INT) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_IPMI_FROM) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_125US) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_0_ADD) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_DB_1_ADD) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART1) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_UART2) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_FIC_ADD_INT) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_CS8900) | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2X01_BBSRAM) ) + +/* + * IXDP2401 specific IRQs + */ +#define IRQ_IXDP2401_INTA_82546 IXP2000_BOARD_IRQ(0) +#define IRQ_IXDP2401_INTB_82546 IXP2000_BOARD_IRQ(1) + +#define IXDP2401_VALID_IRQ_MASK ( \ + IXDP2X01_VALID_IRQ_MASK | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTA_82546) |\ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2401_INTB_82546)) + +/* + * IXDP2801-specific IRQs + */ +#define IRQ_IXDP2801_RIV IXP2000_BOARD_IRQ(0) +#define IRQ_IXDP2801_CNFG_MEDIA IXP2000_BOARD_IRQ(27) +#define IRQ_IXDP2801_CLOCK_REF IXP2000_BOARD_IRQ(28) + +#define IXDP2801_VALID_IRQ_MASK ( \ + IXDP2X01_VALID_IRQ_MASK | \ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_RIV) |\ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CNFG_MEDIA) |\ + IXP2000_BOARD_IRQ_MASK(IRQ_IXDP2801_CLOCK_REF)) + +#define NR_IXDP2X01_IRQS ((IRQ_IXDP2801_CLOCK_REF) + 1) + +#endif /*_IRQS_H*/ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h new file mode 100644 index 00000000..5df8479d --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x00.h @@ -0,0 +1,92 @@ +/* + * arch/arm/mach-ixp2000/include/mach/ixdp2x00.h + * + * Register and other defines for IXDP2[48]00 platforms + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _IXDP2X00_H_ +#define _IXDP2X00_H_ + +/* + * On board CPLD memory map + */ +#define IXDP2X00_PHYS_CPLD_BASE 0xc7000000 +#define IXDP2X00_VIRT_CPLD_BASE 0xfe000000 +#define IXDP2X00_CPLD_SIZE 0x00100000 + + +#define IXDP2X00_CPLD_REG(x) \ + (volatile unsigned long *)(IXDP2X00_VIRT_CPLD_BASE | x) + +/* + * IXDP2400 CPLD registers + */ +#define IXDP2400_CPLD_SYSLED IXDP2X00_CPLD_REG(0x0) +#define IXDP2400_CPLD_DISP_DATA IXDP2X00_CPLD_REG(0x4) +#define IXDP2400_CPLD_CLOCK_SPEED IXDP2X00_CPLD_REG(0x8) +#define IXDP2400_CPLD_INT_STAT IXDP2X00_CPLD_REG(0xc) +#define IXDP2400_CPLD_REV IXDP2X00_CPLD_REG(0x10) +#define IXDP2400_CPLD_SYS_CLK_M IXDP2X00_CPLD_REG(0x14) +#define IXDP2400_CPLD_SYS_CLK_N IXDP2X00_CPLD_REG(0x18) +#define IXDP2400_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x48) + +/* + * IXDP2800 CPLD registers + */ +#define IXDP2800_CPLD_INT_STAT IXDP2X00_CPLD_REG(0x0) +#define IXDP2800_CPLD_INT_MASK IXDP2X00_CPLD_REG(0x140) + + +#define IXDP2X00_GPIO_I2C_ENABLE 0x02 +#define IXDP2X00_GPIO_SCL 0x07 +#define IXDP2X00_GPIO_SDA 0x06 + +/* + * PCI devfns for on-board devices. We need these to be able to + * properly translate IRQs and for device removal. + */ +#define IXDP2400_SLAVE_ENET_DEVFN 0x18 /* Bus 1 */ +#define IXDP2400_MASTER_ENET_DEVFN 0x20 /* Bus 1 */ +#define IXDP2400_MEDIA_DEVFN 0x28 /* Bus 1 */ +#define IXDP2400_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ + +#define IXDP2800_SLAVE_ENET_DEVFN 0x20 /* Bus 1 */ +#define IXDP2800_MASTER_ENET_DEVFN 0x18 /* Bus 1 */ +#define IXDP2800_SWITCH_FABRIC_DEVFN 0x30 /* Bus 1 */ + +#define IXDP2X00_P2P_DEVFN 0x20 /* Bus 0 */ +#define IXDP2X00_21555_DEVFN 0x30 /* Bus 0 */ +#define IXDP2X00_SLAVE_NPU_DEVFN 0x28 /* Bus 1 */ +#define IXDP2X00_PMC_DEVFN 0x38 /* Bus 1 */ +#define IXDP2X00_MASTER_NPU_DEVFN 0x38 /* Bus 1 */ + +#ifndef __ASSEMBLY__ +/* + * The master NPU is always PCI master. + */ +static inline unsigned int ixdp2x00_master_npu(void) +{ + return !!ixp2000_is_pcimaster(); +} + +/* + * Helper functions used by ixdp2400 and ixdp2800 specific code + */ +void ixdp2x00_init_irq(volatile unsigned long*, volatile unsigned long *, unsigned long); +void ixdp2x00_slave_pci_postinit(void); +void ixdp2x00_init_machine(void); +void ixdp2x00_map_io(void); + +#endif + +#endif /*_IXDP2X00_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h new file mode 100644 index 00000000..4c1f0408 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/ixdp2x01.h @@ -0,0 +1,57 @@ +/* + * arch/arm/mach-ixp2000/include/mach/ixdp2x01.h + * + * Platform definitions for IXDP2X01 && IXDP2801 systems + * + * Author: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2004 (c) MontaVista Software, Inc. + * + * Based on original code Copyright (c) 2002-2003 Intel Corporation + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#ifndef __IXDP2X01_H__ +#define __IXDP2X01_H__ + +#define IXDP2X01_PHYS_CPLD_BASE 0xc6024000 +#define IXDP2X01_VIRT_CPLD_BASE 0xfe000000 +#define IXDP2X01_CPLD_REGION_SIZE 0x00100000 + +#define IXDP2X01_CPLD_VIRT_REG(reg) (volatile unsigned long*)(IXDP2X01_VIRT_CPLD_BASE | reg) +#define IXDP2X01_CPLD_PHYS_REG(reg) (IXDP2X01_PHYS_CPLD_BASE | reg) + +#define IXDP2X01_UART1_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x40) +#define IXDP2X01_UART1_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x40) + +#define IXDP2X01_UART2_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x60) +#define IXDP2X01_UART2_PHYS_BASE IXDP2X01_CPLD_PHYS_REG(0x60) + +#define IXDP2X01_CS8900_VIRT_BASE IXDP2X01_CPLD_VIRT_REG(0x80) +#define IXDP2X01_CS8900_VIRT_END (IXDP2X01_CS8900_VIRT_BASE + 16) + +#define IXDP2X01_CPLD_RESET_REG IXDP2X01_CPLD_VIRT_REG(0x00) +#define IXDP2X01_INT_MASK_SET_REG IXDP2X01_CPLD_VIRT_REG(0x08) +#define IXDP2X01_INT_STAT_REG IXDP2X01_CPLD_VIRT_REG(0x0C) +#define IXDP2X01_INT_RAW_REG IXDP2X01_CPLD_VIRT_REG(0x10) +#define IXDP2X01_INT_MASK_CLR_REG IXDP2X01_INT_RAW_REG +#define IXDP2X01_INT_SIM_REG IXDP2X01_CPLD_VIRT_REG(0x14) + +#define IXDP2X01_CPLD_FLASH_REG IXDP2X01_CPLD_VIRT_REG(0x20) + +#define IXDP2X01_CPLD_FLASH_INTERN 0x8000 +#define IXDP2X01_CPLD_FLASH_BANK_MASK 0xF +#define IXDP2X01_FLASH_WINDOW_BITS 25 +#define IXDP2X01_FLASH_WINDOW_SIZE (1 << IXDP2X01_FLASH_WINDOW_BITS) +#define IXDP2X01_FLASH_WINDOW_MASK (IXDP2X01_FLASH_WINDOW_SIZE - 1) + +#define IXDP2X01_UART_CLK 1843200 + +#define IXDP2X01_GPIO_I2C_ENABLE 0x02 +#define IXDP2X01_GPIO_SCL 0x07 +#define IXDP2X01_GPIO_SDA 0x06 + +#endif /* __IXDP2x01_H__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h new file mode 100644 index 00000000..822f63f2 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h @@ -0,0 +1,451 @@ +/* + * arch/arm/mach-ixp2000/include/mach/ixp2000-regs.h + * + * Chipset register definitions for IXP2400/2800 based systems. + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef _IXP2000_REGS_H_ +#define _IXP2000_REGS_H_ + +/* + * IXP2000 linux memory map: + * + * virt phys size + * fb000000 db000000 16M PCI CFG1 + * fc000000 da000000 16M PCI CFG0 + * fd000000 d8000000 16M PCI I/O + * fe[0-7]00000 8M per-platform mappings + * fe900000 80000000 1M SRAM #0 (first MB) + * fea00000 cb400000 1M SCRATCH ring get/put + * feb00000 c8000000 1M MSF + * fec00000 df000000 1M PCI CSRs + * fed00000 de000000 1M PCI CREG + * fee00000 d6000000 1M INTCTL + * fef00000 c0000000 1M CAP + */ + +/* + * Static I/O regions. + * + * Most of the registers are clumped in 4K regions spread throughout + * the 0xc0000000 -> 0xc0100000 address range, but we just map in + * the whole range using a single 1 MB section instead of small + * 4K pages. + * + * CAP stands for CSR Access Proxy. + * + * If you change the virtual address of this mapping, please propagate + * the change to arch/arm/kernel/debug.S, which hardcodes the virtual + * address of the UART located in this region. + */ + +#define IXP2000_CAP_PHYS_BASE 0xc0000000 +#define IXP2000_CAP_VIRT_BASE 0xfef00000 +#define IXP2000_CAP_SIZE 0x00100000 + +/* + * Addresses for specific on-chip peripherals. + */ +#define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000 +#define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000 +#define IXP2000_UART_PHYS_BASE 0xc0030000 +#define IXP2000_UART_VIRT_BASE 0xfef30000 +#define IXP2000_TIMER_VIRT_BASE 0xfef20000 +#define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000 +#define IXP2000_GPIO_VIRT_BASE 0xfef10000 + +/* + * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual + * addresses of the INTCTL and PCI_CSR mappings are hardcoded in + * entry-macro.S, so if you ever change these please propagate + * the change. + */ +#define IXP2000_INTCTL_PHYS_BASE 0xd6000000 +#define IXP2000_INTCTL_VIRT_BASE 0xfee00000 +#define IXP2000_INTCTL_SIZE 0x00100000 + +#define IXP2000_PCI_CREG_PHYS_BASE 0xde000000 +#define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000 +#define IXP2000_PCI_CREG_SIZE 0x00100000 + +#define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000 +#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 +#define IXP2000_PCI_CSR_SIZE 0x00100000 + +#define IXP2000_MSF_PHYS_BASE 0xc8000000 +#define IXP2000_MSF_VIRT_BASE 0xfeb00000 +#define IXP2000_MSF_SIZE 0x00100000 + +#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000 +#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000 +#define IXP2000_SCRATCH_RING_SIZE 0x00100000 + +#define IXP2000_SRAM0_PHYS_BASE 0x80000000 +#define IXP2000_SRAM0_VIRT_BASE 0xfe900000 +#define IXP2000_SRAM0_SIZE 0x00100000 + +#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 +#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 +#define IXP2000_PCI_IO_SIZE 0x01000000 + +#define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000 +#define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000 +#define IXP2000_PCI_CFG0_SIZE 0x01000000 + +#define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000 +#define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000 +#define IXP2000_PCI_CFG1_SIZE 0x01000000 + +/* + * Timers + */ +#define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x))) +/* Timer control */ +#define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00) +#define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04) +#define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08) +#define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c) +/* Store initial value */ +#define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10) +#define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14) +#define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18) +#define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c) +/* Read current value */ +#define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20) +#define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24) +#define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28) +#define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c) +/* Clear associated timer interrupt */ +#define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30) +#define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34) +#define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38) +#define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c) +/* Timer watchdog enable for T4 */ +#define IXP2000_TWDE IXP2000_TIMER_REG(0x40) + +#define WDT_ENABLE 0x00000001 +#define TIMER_DIVIDER_256 0x00000008 +#define TIMER_ENABLE 0x00000080 +#define IRQ_MASK_TIMER1 (1 << 4) + +/* + * Interrupt controller registers + */ +#define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x)) +#define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08) +#define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10) +#define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10) +#define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18) +#define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14) +#define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24) +#define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c) +#define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30) +#define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34) +#define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60) +#define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64) +#define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68) +#define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c) +#define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80) +#define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84) +#define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88) +#define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c) +#define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0) +#define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4) +#define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8) +#define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec) +#define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100) +#define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104) +#define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108) +#define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c) +#define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160) +#define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164) +#define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168) +#define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c) +#define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180) +#define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184) +#define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188) +#define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208) +#define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c) + +/* + * Mask of valid IRQs in the 32-bit IRQ register. We use + * this to mark certain IRQs as being invalid. + */ +#define IXP2000_VALID_IRQ_MASK 0x0f0fffff + +/* + * PCI config register access from core + */ +#define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x)) +#define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04) +#define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10) +#define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14) +#define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18) + +/* + * PCI CSRs + */ +#define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x)) + +/* + * PCI outbound interrupts + */ +#define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30) +#define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34) +/* + * PCI communications + */ +#define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50) +#define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54) +#define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58) +#define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C) +#define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60) +#define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64) +#define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70) +#define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74) + +/* + * DMA engines + */ +#define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80) +#define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84) +#define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88) +#define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C) +#define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90) +#define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94) +#define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0) +#define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4) +#define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8) +#define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC) +#define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0) +#define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4) +#define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0) +#define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4) +#define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8) +#define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC) +#define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0) +#define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4) +#define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0) +/* + * Size masks for BARs + */ +#define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC) +#define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100) +/* + * Control and uEngine related + */ +#define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C) +#define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140) +#define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148) +#define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C) +#define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150) +#define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154) +/* + * Inbound PCI interrupt control + */ +#define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158) +#define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C) + +#define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */ +#define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */ +#define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */ + +/* These are from the IRQ register in the PCI ISR register */ +#define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */ +#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ +#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ +#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ +#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */ + +#define IXP2000_PCI_RST_REL (1 << 2) +#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) +#define CFG_PCI_BOOT_HOST (1 << 2) +#define CFG_BOOT_PROM (1 << 1) + +/* + * SlowPort CSRs + * + * The slowport is used to access things like flash, SONET framer control + * ports, slave microprocessors, CPLDs, and others of chip memory mapped + * peripherals. + */ +#define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x)) + +#define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00) +#define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04) +#define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08) +#define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c) +#define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10) +#define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14) +#define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18) +#define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C) +#define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20) +#define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24) +#define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28) + +/* + * CCR values. + * The CCR configures the clock division for the slowport interface. + */ +#define SLOWPORT_CCR_DIV_1 0x00 +#define SLOWPORT_CCR_DIV_2 0x01 +#define SLOWPORT_CCR_DIV_4 0x02 +#define SLOWPORT_CCR_DIV_6 0x03 +#define SLOWPORT_CCR_DIV_8 0x04 +#define SLOWPORT_CCR_DIV_10 0x05 +#define SLOWPORT_CCR_DIV_12 0x06 +#define SLOWPORT_CCR_DIV_14 0x07 +#define SLOWPORT_CCR_DIV_16 0x08 +#define SLOWPORT_CCR_DIV_18 0x09 +#define SLOWPORT_CCR_DIV_20 0x0a +#define SLOWPORT_CCR_DIV_22 0x0b +#define SLOWPORT_CCR_DIV_24 0x0c +#define SLOWPORT_CCR_DIV_26 0x0d +#define SLOWPORT_CCR_DIV_28 0x0e +#define SLOWPORT_CCR_DIV_30 0x0f + +/* + * PCR values. PCR configure the mode of the interface. + */ +#define SLOWPORT_MODE_FLASH 0x00 +#define SLOWPORT_MODE_LUCENT 0x01 +#define SLOWPORT_MODE_PMC_SIERRA 0x02 +#define SLOWPORT_MODE_INTEL_UP 0x03 +#define SLOWPORT_MODE_MOTOROLA_UP 0x04 + +/* + * ADC values. Defines data and address bus widths. + */ +#define SLOWPORT_ADDR_WIDTH_8 0x00 +#define SLOWPORT_ADDR_WIDTH_16 0x01 +#define SLOWPORT_ADDR_WIDTH_24 0x02 +#define SLOWPORT_ADDR_WIDTH_32 0x03 +#define SLOWPORT_DATA_WIDTH_8 0x00 +#define SLOWPORT_DATA_WIDTH_16 0x10 +#define SLOWPORT_DATA_WIDTH_24 0x20 +#define SLOWPORT_DATA_WIDTH_32 0x30 + +/* + * Masks and shifts for various fields in the WTC and RTC registers. + */ +#define SLOWPORT_WRTC_MASK_HD 0x0003 +#define SLOWPORT_WRTC_MASK_PW 0x003c +#define SLOWPORT_WRTC_MASK_SU 0x03c0 + +#define SLOWPORT_WRTC_SHIFT_HD 0x00 +#define SLOWPORT_WRTC_SHIFT_SU 0x02 +#define SLOWPORT_WRTC_SHFIT_PW 0x06 + + +/* + * GPIO registers & GPIO interface. + */ +#define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x))) +#define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00) +#define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04) +#define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08) +#define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c) +#define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10) +#define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14) +#define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18) +#define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c) +#define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20) +#define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24) +#define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28) +#define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c) +#define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30) +#define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34) +#define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38) +#define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c) +#define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40) + +/* + * "Global" registers...whatever that's supposed to mean. + */ +#define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00) +#define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x)) + +#define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000 +#define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000 +#define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00 +#define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200 +#define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100 +#define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000 +#define IXP2000_MAJ_REV_MASK 0x000000F0 +#define IXP2000_MIN_REV_MASK 0x0000000F +#define IXP2000_PROD_ID_MASK 0xFFFFFFFF + +#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00) +#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) +#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) +#define IXP2000_RESET0 GLOBAL_REG(0x0c) +#define IXP2000_RESET1 GLOBAL_REG(0x10) +#define IXP2000_CCR GLOBAL_REG(0x14) +#define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18) + +#define RSTALL (1 << 16) +#define WDT_RESET_ENABLE 0x01000000 + + +/* + * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF + * units, but the registers that differ between the two don't overlap, + * so we can have one register list for both. + */ +#define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x))) +#define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000) +#define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004) +#define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008) +#define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c) +#define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010) +#define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014) +#define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018) +#define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024) +#define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028) +#define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c) +#define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040) +#define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044) +#define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048) +#define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048) +#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050) +#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054) +#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058) +#define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060) +#define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064) +#define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068) +#define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070) +#define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070) +#define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080) +#define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084) +#define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088) +#define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c) +#define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090) +#define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094) +#define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098) +#define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c) +#define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0) +#define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4) +#define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8) +#define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000) +#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400) + + +#endif /* _IXP2000_H_ */ diff --git a/arch/arm/mach-ixp2000/include/mach/memory.h b/arch/arm/mach-ixp2000/include/mach/memory.h new file mode 100644 index 00000000..5f0c4fd4 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/memory.h @@ -0,0 +1,31 @@ +/* + * arch/arm/mach-ixp2000/include/mach/memory.h + * + * Copyright (c) 2002 Intel Corp. + * Copyright (c) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_ARCH_MEMORY_H +#define __ASM_ARCH_MEMORY_H + +#define PLAT_PHYS_OFFSET UL(0x00000000) + +#include <mach/ixp2000-regs.h> + +#define IXP2000_PCI_SDRAM_OFFSET (*IXP2000_PCI_SDRAM_BAR & 0xfffffff0) + +#define __phys_to_bus(x) ((x) + (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) +#define __bus_to_phys(x) ((x) - (IXP2000_PCI_SDRAM_OFFSET - PHYS_OFFSET)) + +#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v)) +#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b)) +#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p)) +#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b)) + +#endif + diff --git a/arch/arm/mach-ixp2000/include/mach/platform.h b/arch/arm/mach-ixp2000/include/mach/platform.h new file mode 100644 index 00000000..42182c79 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/platform.h @@ -0,0 +1,152 @@ +/* + * arch/arm/mach-ixp2000/include/mach/platform.h + * + * Various bits of code used by platform-level code. + * + * Author: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2004 (c) MontaVista Software, Inc. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + + +#ifndef __ASSEMBLY__ + +static inline unsigned long ixp2000_reg_read(volatile void *reg) +{ + return *((volatile unsigned long *)reg); +} + +static inline void ixp2000_reg_write(volatile void *reg, unsigned long val) +{ + *((volatile unsigned long *)reg) = val; +} + +/* + * On the IXP2400, we can't use XCB=000 due to chip bugs. We use + * XCB=101 instead, but that makes all I/O accesses bufferable. This + * is not a problem in general, but we do have to be slightly more + * careful because I/O writes are no longer automatically flushed out + * of the write buffer. + * + * In cases where we want to make sure that a write has been flushed + * out of the write buffer before we proceed, for example when masking + * a device interrupt before re-enabling IRQs in CPSR, we can use this + * function, ixp2000_reg_wrb, which performs a write, a readback, and + * issues a dummy instruction dependent on the value of the readback + * (mov rX, rX) to make sure that the readback has completed before we + * continue. + */ +static inline void ixp2000_reg_wrb(volatile void *reg, unsigned long val) +{ + unsigned long dummy; + + *((volatile unsigned long *)reg) = val; + + dummy = *((volatile unsigned long *)reg); + __asm__ __volatile__("mov %0, %0" : "+r" (dummy)); +} + +/* + * Boards may multiplex different devices on the 2nd channel of + * the slowport interface that each need different configuration + * settings. For example, the IXDP2400 uses channel 2 on the interface + * to access the CPLD, the switch fabric card, and the media card. Each + * one needs a different mode so drivers must save/restore the mode + * before and after each operation. + * + * acquire_slowport(&your_config); + * ... + * do slowport operations + * ... + * release_slowport(); + * + * Note that while you have the slowport, you are holding a spinlock, + * so your code should be written as if you explicitly acquired a lock. + * + * The configuration only affects device 2 on the slowport, so the + * MTD map driver does not acquire/release the slowport. + */ +struct slowport_cfg { + unsigned long CCR; /* Clock divide */ + unsigned long WTC; /* Write Timing Control */ + unsigned long RTC; /* Read Timing Control */ + unsigned long PCR; /* Protocol Control Register */ + unsigned long ADC; /* Address/Data Width Control */ +}; + + +void ixp2000_acquire_slowport(struct slowport_cfg *, struct slowport_cfg *); +void ixp2000_release_slowport(struct slowport_cfg *); + +/* + * IXP2400 A0/A1 and IXP2800 A0/A1/A2 have broken slowport that requires + * tweaking of addresses in the MTD driver. + */ +static inline unsigned ixp2000_has_broken_slowport(void) +{ + unsigned long id = *IXP2000_PRODUCT_ID; + unsigned long id_prod = id & (IXP2000_MAJ_PROD_TYPE_MASK | + IXP2000_MIN_PROD_TYPE_MASK); + return (((id_prod == + /* fixed in IXP2400-B0 */ + (IXP2000_MAJ_PROD_TYPE_IXP2000 | + IXP2000_MIN_PROD_TYPE_IXP2400)) && + ((id & IXP2000_MAJ_REV_MASK) == 0)) || + ((id_prod == + /* fixed in IXP2800-B0 */ + (IXP2000_MAJ_PROD_TYPE_IXP2000 | + IXP2000_MIN_PROD_TYPE_IXP2800)) && + ((id & IXP2000_MAJ_REV_MASK) == 0)) || + ((id_prod == + /* fixed in IXP2850-B0 */ + (IXP2000_MAJ_PROD_TYPE_IXP2000 | + IXP2000_MIN_PROD_TYPE_IXP2850)) && + ((id & IXP2000_MAJ_REV_MASK) == 0))); +} + +static inline unsigned int ixp2000_has_flash(void) +{ + return ((*IXP2000_STRAP_OPTIONS) & (CFG_BOOT_PROM)); +} + +static inline unsigned int ixp2000_is_pcimaster(void) +{ + return ((*IXP2000_STRAP_OPTIONS) & (CFG_PCI_BOOT_HOST)); +} + +void ixp2000_map_io(void); +void ixp2000_uart_init(void); +void ixp2000_init_irq(void); +void ixp2000_init_time(unsigned long); +unsigned long ixp2000_gettimeoffset(void); + +struct pci_sys_data; + +u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where); +void ixp2000_pci_preinit(void); +int ixp2000_pci_setup(int, struct pci_sys_data*); +struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*); +int ixp2000_pci_read_config(struct pci_bus*, unsigned int, int, int, u32 *); +int ixp2000_pci_write_config(struct pci_bus*, unsigned int, int, int, u32); + +/* + * Several of the IXP2000 systems have banked flash so we need to extend the + * flash_platform_data structure with some private pointers + */ +struct ixp2000_flash_data { + struct flash_platform_data *platform_data; + int nr_banks; + unsigned long (*bank_setup)(unsigned long); +}; + +struct ixp2000_i2c_pins { + unsigned long sda_pin; + unsigned long scl_pin; +}; + + +#endif /* !__ASSEMBLY__ */ diff --git a/arch/arm/mach-ixp2000/include/mach/system.h b/arch/arm/mach-ixp2000/include/mach/system.h new file mode 100644 index 00000000..de370992 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/system.h @@ -0,0 +1,49 @@ +/* + * arch/arm/mach-ixp2000/include/mach/system.h + * + * Copyright (C) 2002 Intel Corp. + * Copyricht (C) 2003-2005 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include <mach/hardware.h> +#include <asm/mach-types.h> + +static inline void arch_idle(void) +{ + cpu_do_idle(); +} + +static inline void arch_reset(char mode, const char *cmd) +{ + local_irq_disable(); + + /* + * Reset flash banking register so that we are pointing at + * RedBoot bank. + */ + if (machine_is_ixdp2401()) { + ixp2000_reg_write(IXDP2X01_CPLD_FLASH_REG, + ((0 >> IXDP2X01_FLASH_WINDOW_BITS) + | IXDP2X01_CPLD_FLASH_INTERN)); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0xffffffff); + } + + /* + * On IXDP2801 we need to write this magic sequence to the CPLD + * to cause a complete reset of the CPU and all external devices + * and move the flash bank register back to 0. + */ + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) { + unsigned long reset_reg = *IXDP2X01_CPLD_RESET_REG; + + reset_reg = 0x55AA0000 | (reset_reg & 0x0000FFFF); + ixp2000_reg_write(IXDP2X01_CPLD_RESET_REG, reset_reg); + ixp2000_reg_wrb(IXDP2X01_CPLD_RESET_REG, 0x80000000); + } + + ixp2000_reg_wrb(IXP2000_RESET0, RSTALL); +} diff --git a/arch/arm/mach-ixp2000/include/mach/timex.h b/arch/arm/mach-ixp2000/include/mach/timex.h new file mode 100644 index 00000000..835e659f --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/timex.h @@ -0,0 +1,13 @@ +/* + * arch/arm/mach-ixp2000/include/mach/timex.h + * + * IXP2000 architecture timex specifications + */ + + +/* + * Default clock is 50MHz APB, but platform code can override this + */ +#define CLOCK_TICK_RATE 50000000 + + diff --git a/arch/arm/mach-ixp2000/include/mach/uncompress.h b/arch/arm/mach-ixp2000/include/mach/uncompress.h new file mode 100644 index 00000000..ce363087 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/uncompress.h @@ -0,0 +1,47 @@ +/* + * arch/arm/mach-ixp2000/include/mach/uncompress.h + * + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2002 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#include <linux/serial_reg.h> + +#define UART_BASE 0xc0030000 + +#define PHYS(x) ((volatile unsigned long *)(UART_BASE + x)) + +#define UARTDR PHYS(0x00) /* Transmit reg dlab=0 */ +#define UARTDLL PHYS(0x00) /* Divisor Latch reg dlab=1*/ +#define UARTDLM PHYS(0x04) /* Divisor Latch reg dlab=1*/ +#define UARTIER PHYS(0x04) /* Interrupt enable reg */ +#define UARTFCR PHYS(0x08) /* FIFO control reg dlab =0*/ +#define UARTLCR PHYS(0x0c) /* Control reg */ +#define UARTSR PHYS(0x14) /* Status reg */ + + +static inline void putc(int c) +{ + int j = 0x1000; + + while (--j && !(*UARTSR & UART_LSR_THRE)) + barrier(); + + *UARTDR = c; +} + +static inline void flush(void) +{ +} + +#define arch_decomp_setup() +#define arch_decomp_wdog() diff --git a/arch/arm/mach-ixp2000/include/mach/vmalloc.h b/arch/arm/mach-ixp2000/include/mach/vmalloc.h new file mode 100644 index 00000000..61c8dae2 --- /dev/null +++ b/arch/arm/mach-ixp2000/include/mach/vmalloc.h @@ -0,0 +1,20 @@ +/* + * arch/arm/mach-ixp2000/include/mach/vmalloc.h + * + * Author: Naeem Afzal <naeem.m.afzal@intel.com> + * + * Copyright 2002 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Just any arbitrary offset to the start of the vmalloc VM area: the + * current 8MB value just means that there will be a 8MB "hole" after the + * physical memory until the kernel virtual memory starts. That means that + * any out-of-bounds memory accesses will hopefully be caught. + * The vmalloc() routines leaves a hole of 4kB between each vmalloced + * area for the same reason. ;) + */ +#define VMALLOC_END 0xfb000000UL diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c new file mode 100644 index 00000000..dfffc1e8 --- /dev/null +++ b/arch/arm/mach-ixp2000/ixdp2400.c @@ -0,0 +1,179 @@ +/* + * arch/arm/mach-ixp2000/ixdp2400.c + * + * IXDP2400 platform support + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/bitops.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +#include <asm/mach/pci.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach/flash.h> +#include <asm/mach/arch.h> + +/************************************************************************* + * IXDP2400 timer tick + *************************************************************************/ +static void __init ixdp2400_timer_init(void) +{ + int numerator, denominator; + int denom_array[] = {2, 4, 8, 16, 1, 2, 4, 8}; + + numerator = (*(IXDP2400_CPLD_SYS_CLK_M) & 0xFF) *2; + denominator = denom_array[(*(IXDP2400_CPLD_SYS_CLK_N) & 0x7)]; + + ixp2000_init_time(((3125000 * numerator) / (denominator)) / 2); +} + +static struct sys_timer ixdp2400_timer = { + .init = ixdp2400_timer_init, + .offset = ixp2000_gettimeoffset, +}; + +/************************************************************************* + * IXDP2400 PCI + *************************************************************************/ +void __init ixdp2400_pci_preinit(void) +{ + ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00100000); + ixp2000_pci_preinit(); + pcibios_setup("firmware"); +} + +int ixdp2400_pci_setup(int nr, struct pci_sys_data *sys) +{ + sys->mem_offset = 0xe0000000; + + ixp2000_pci_setup(nr, sys); + + return 1; +} + +static int __init ixdp2400_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (ixdp2x00_master_npu()) { + + /* + * Root bus devices. Slave NPU is only one with interrupt. + * Everything else, we just return -1 b/c nothing else + * on the root bus has interrupts. + */ + if(!dev->bus->self) { + if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) + return IRQ_IXDP2400_INGRESS_NPU; + + return -1; + } + + /* + * Bridge behind the PMC slot. + * NOTE: Only INTA from the PMC slot is routed. VERY BAD. + */ + if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && + dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && + !dev->bus->parent->self->bus->parent) + return IRQ_IXDP2400_PMC; + + /* + * Device behind the first bridge + */ + if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { + switch(dev->devfn) { + case IXDP2400_MASTER_ENET_DEVFN: + return IRQ_IXDP2400_ENET; + + case IXDP2400_MEDIA_DEVFN: + return IRQ_IXDP2400_MEDIA_PCI; + + case IXDP2400_SWITCH_FABRIC_DEVFN: + return IRQ_IXDP2400_SF_PCI; + + case IXDP2X00_PMC_DEVFN: + return IRQ_IXDP2400_PMC; + } + } + + return -1; + } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ +} + + +static void ixdp2400_pci_postinit(void) +{ + struct pci_dev *dev; + + if (ixdp2x00_master_npu()) { + dev = pci_get_bus_and_slot(1, IXDP2400_SLAVE_ENET_DEVFN); + pci_remove_bus_device(dev); + pci_dev_put(dev); + } else { + dev = pci_get_bus_and_slot(1, IXDP2400_MASTER_ENET_DEVFN); + pci_remove_bus_device(dev); + pci_dev_put(dev); + + ixdp2x00_slave_pci_postinit(); + } +} + +static struct hw_pci ixdp2400_pci __initdata = { + .nr_controllers = 1, + .setup = ixdp2400_pci_setup, + .preinit = ixdp2400_pci_preinit, + .postinit = ixdp2400_pci_postinit, + .scan = ixp2000_pci_scan_bus, + .map_irq = ixdp2400_pci_map_irq, +}; + +int __init ixdp2400_pci_init(void) +{ + if (machine_is_ixdp2400()) + pci_common_init(&ixdp2400_pci); + + return 0; +} + +subsys_initcall(ixdp2400_pci_init); + +void __init ixdp2400_init_irq(void) +{ + ixdp2x00_init_irq(IXDP2400_CPLD_INT_STAT, IXDP2400_CPLD_INT_MASK, IXDP2400_NR_IRQS); +} + +MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .boot_params = 0x00000100, + .map_io = ixdp2x00_map_io, + .init_irq = ixdp2400_init_irq, + .timer = &ixdp2400_timer, + .init_machine = ixdp2x00_init_machine, +MACHINE_END + diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c new file mode 100644 index 00000000..cd4c9bcf --- /dev/null +++ b/arch/arm/mach-ixp2000/ixdp2800.c @@ -0,0 +1,294 @@ +/* + * arch/arm/mach-ixp2000/ixdp2800.c + * + * IXDP2800 platform support + * + * Original Author: Jeffrey Daly <jeffrey.daly@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/device.h> +#include <linux/bitops.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +#include <asm/mach/pci.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach/flash.h> +#include <asm/mach/arch.h> + +/************************************************************************* + * IXDP2800 timer tick + *************************************************************************/ + +static void __init ixdp2800_timer_init(void) +{ + ixp2000_init_time(50000000); +} + +static struct sys_timer ixdp2800_timer = { + .init = ixdp2800_timer_init, + .offset = ixp2000_gettimeoffset, +}; + +/************************************************************************* + * IXDP2800 PCI + *************************************************************************/ +static void __init ixdp2800_slave_disable_pci_master(void) +{ + *IXP2000_PCI_CMDSTAT &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); +} + +static void __init ixdp2800_master_wait_for_slave(void) +{ + volatile u32 *addr; + + printk(KERN_INFO "IXDP2800: waiting for slave NPU to configure " + "its BAR sizes\n"); + + addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, + PCI_BASE_ADDRESS_1); + do { + *addr = 0xffffffff; + cpu_relax(); + } while (*addr != 0xfe000008); + + addr = ixp2000_pci_config_addr(0, IXDP2X00_SLAVE_NPU_DEVFN, + PCI_BASE_ADDRESS_2); + do { + *addr = 0xffffffff; + cpu_relax(); + } while (*addr != 0xc0000008); + + /* + * Configure the slave's SDRAM BAR by hand. + */ + *addr = 0x40000008; +} + +static void __init ixdp2800_slave_wait_for_master_enable(void) +{ + printk(KERN_INFO "IXDP2800: waiting for master NPU to enable us\n"); + + while ((*IXP2000_PCI_CMDSTAT & PCI_COMMAND_MASTER) == 0) + cpu_relax(); +} + +void __init ixdp2800_pci_preinit(void) +{ + printk("ixdp2x00_pci_preinit called\n"); + + *IXP2000_PCI_ADDR_EXT = 0x0001e000; + + if (!ixdp2x00_master_npu()) + ixdp2800_slave_disable_pci_master(); + + *IXP2000_PCI_SRAM_BASE_ADDR_MASK = (0x2000000 - 1) & ~0x3ffff; + *IXP2000_PCI_DRAM_BASE_ADDR_MASK = (0x40000000 - 1) & ~0xfffff; + + ixp2000_pci_preinit(); + + if (ixdp2x00_master_npu()) { + /* + * Wait until the slave set its SRAM/SDRAM BAR sizes + * correctly before we proceed to scan and enumerate + * the bus. + */ + ixdp2800_master_wait_for_slave(); + + /* + * We configure the SDRAM BARs by hand because they + * are 1G and fall outside of the regular allocated + * PCI address space. + */ + *IXP2000_PCI_SDRAM_BAR = 0x00000008; + } else { + /* + * Wait for the master to complete scanning the bus + * and assigning resources before we proceed to scan + * the bus ourselves. Set pci=firmware to honor the + * master's resource assignment. + */ + ixdp2800_slave_wait_for_master_enable(); + pcibios_setup("firmware"); + } +} + +/* + * We assign the SDRAM BARs for the two IXP2800 CPUs by hand, outside + * of the regular PCI window, because there's only 512M of outbound PCI + * memory window on each IXP, while we need 1G for each of the BARs. + */ +static void __devinit ixp2800_pci_fixup(struct pci_dev *dev) +{ + if (machine_is_ixdp2800()) { + dev->resource[2].start = 0; + dev->resource[2].end = 0; + dev->resource[2].flags = 0; + } +} +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IXP2800, ixp2800_pci_fixup); + +static int __init ixdp2800_pci_setup(int nr, struct pci_sys_data *sys) +{ + sys->mem_offset = 0x00000000; + + ixp2000_pci_setup(nr, sys); + + return 1; +} + +static int __init ixdp2800_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + if (ixdp2x00_master_npu()) { + + /* + * Root bus devices. Slave NPU is only one with interrupt. + * Everything else, we just return -1 which is invalid. + */ + if(!dev->bus->self) { + if(dev->devfn == IXDP2X00_SLAVE_NPU_DEVFN ) + return IRQ_IXDP2800_INGRESS_NPU; + + return -1; + } + + /* + * Bridge behind the PMC slot. + */ + if(dev->bus->self->devfn == IXDP2X00_PMC_DEVFN && + dev->bus->parent->self->devfn == IXDP2X00_P2P_DEVFN && + !dev->bus->parent->self->bus->parent) + return IRQ_IXDP2800_PMC; + + /* + * Device behind the first bridge + */ + if(dev->bus->self->devfn == IXDP2X00_P2P_DEVFN) { + switch(dev->devfn) { + case IXDP2X00_PMC_DEVFN: + return IRQ_IXDP2800_PMC; + + case IXDP2800_MASTER_ENET_DEVFN: + return IRQ_IXDP2800_EGRESS_ENET; + + case IXDP2800_SWITCH_FABRIC_DEVFN: + return IRQ_IXDP2800_FABRIC; + } + } + + return -1; + } else return IRQ_IXP2000_PCIB; /* Slave NIC interrupt */ +} + +static void __init ixdp2800_master_enable_slave(void) +{ + volatile u32 *addr; + + printk(KERN_INFO "IXDP2800: enabling slave NPU\n"); + + addr = (volatile u32 *)ixp2000_pci_config_addr(0, + IXDP2X00_SLAVE_NPU_DEVFN, + PCI_COMMAND); + + *addr |= PCI_COMMAND_MASTER; +} + +static void __init ixdp2800_master_wait_for_slave_bus_scan(void) +{ + volatile u32 *addr; + + printk(KERN_INFO "IXDP2800: waiting for slave to finish bus scan\n"); + + addr = (volatile u32 *)ixp2000_pci_config_addr(0, + IXDP2X00_SLAVE_NPU_DEVFN, + PCI_COMMAND); + while ((*addr & PCI_COMMAND_MEMORY) == 0) + cpu_relax(); +} + +static void __init ixdp2800_slave_signal_bus_scan_completion(void) +{ + printk(KERN_INFO "IXDP2800: bus scan done, signaling master\n"); + *IXP2000_PCI_CMDSTAT |= PCI_COMMAND_MEMORY; +} + +static void __init ixdp2800_pci_postinit(void) +{ + if (!ixdp2x00_master_npu()) { + ixdp2x00_slave_pci_postinit(); + ixdp2800_slave_signal_bus_scan_completion(); + } +} + +struct __initdata hw_pci ixdp2800_pci __initdata = { + .nr_controllers = 1, + .setup = ixdp2800_pci_setup, + .preinit = ixdp2800_pci_preinit, + .postinit = ixdp2800_pci_postinit, + .scan = ixp2000_pci_scan_bus, + .map_irq = ixdp2800_pci_map_irq, +}; + +int __init ixdp2800_pci_init(void) +{ + if (machine_is_ixdp2800()) { + struct pci_dev *dev; + + pci_common_init(&ixdp2800_pci); + if (ixdp2x00_master_npu()) { + dev = pci_get_bus_and_slot(1, IXDP2800_SLAVE_ENET_DEVFN); + pci_remove_bus_device(dev); + pci_dev_put(dev); + + ixdp2800_master_enable_slave(); + ixdp2800_master_wait_for_slave_bus_scan(); + } else { + dev = pci_get_bus_and_slot(1, IXDP2800_MASTER_ENET_DEVFN); + pci_remove_bus_device(dev); + pci_dev_put(dev); + } + } + + return 0; +} + +subsys_initcall(ixdp2800_pci_init); + +void __init ixdp2800_init_irq(void) +{ + ixdp2x00_init_irq(IXDP2800_CPLD_INT_STAT, IXDP2800_CPLD_INT_MASK, IXDP2800_NR_IRQS); +} + +MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .boot_params = 0x00000100, + .map_io = ixdp2x00_map_io, + .init_irq = ixdp2800_init_irq, + .timer = &ixdp2800_timer, + .init_machine = ixdp2x00_init_machine, +MACHINE_END + diff --git a/arch/arm/mach-ixp2000/ixdp2x00.c b/arch/arm/mach-ixp2000/ixdp2x00.c new file mode 100644 index 00000000..235638f8 --- /dev/null +++ b/arch/arm/mach-ixp2000/ixdp2x00.c @@ -0,0 +1,307 @@ +/* + * arch/arm/mach-ixp2000/ixdp2x00.c + * + * Code common to IXDP2400 and IXDP2800 platforms. + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/platform_device.h> +#include <linux/bitops.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +#include <asm/mach/pci.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach/flash.h> +#include <asm/mach/arch.h> + +#include <mach/gpio.h> + + +/************************************************************************* + * IXDP2x00 IRQ Initialization + *************************************************************************/ +static volatile unsigned long *board_irq_mask; +static volatile unsigned long *board_irq_stat; +static unsigned long board_irq_count; + +#ifdef CONFIG_ARCH_IXDP2400 +/* + * Slowport configuration for accessing CPLD registers on IXDP2x00 + */ +static struct slowport_cfg slowport_cpld_cfg = { + .CCR = SLOWPORT_CCR_DIV_2, + .WTC = 0x00000070, + .RTC = 0x00000070, + .PCR = SLOWPORT_MODE_FLASH, + .ADC = SLOWPORT_ADDR_WIDTH_24 | SLOWPORT_DATA_WIDTH_8 +}; +#endif + +static void ixdp2x00_irq_mask(struct irq_data *d) +{ + unsigned long dummy; + static struct slowport_cfg old_cfg; + + /* + * This is ugly in common code but really don't know + * of a better way to handle it. :( + */ +#ifdef CONFIG_ARCH_IXDP2400 + if (machine_is_ixdp2400()) + ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); +#endif + + dummy = *board_irq_mask; + dummy |= IXP2000_BOARD_IRQ_MASK(d->irq); + ixp2000_reg_wrb(board_irq_mask, dummy); + +#ifdef CONFIG_ARCH_IXDP2400 + if (machine_is_ixdp2400()) + ixp2000_release_slowport(&old_cfg); +#endif +} + +static void ixdp2x00_irq_unmask(struct irq_data *d) +{ + unsigned long dummy; + static struct slowport_cfg old_cfg; + +#ifdef CONFIG_ARCH_IXDP2400 + if (machine_is_ixdp2400()) + ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); +#endif + + dummy = *board_irq_mask; + dummy &= ~IXP2000_BOARD_IRQ_MASK(d->irq); + ixp2000_reg_wrb(board_irq_mask, dummy); + + if (machine_is_ixdp2400()) + ixp2000_release_slowport(&old_cfg); +} + +static void ixdp2x00_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + volatile u32 ex_interrupt = 0; + static struct slowport_cfg old_cfg; + int i; + + desc->irq_data.chip->irq_mask(&desc->irq_data); + +#ifdef CONFIG_ARCH_IXDP2400 + if (machine_is_ixdp2400()) + ixp2000_acquire_slowport(&slowport_cpld_cfg, &old_cfg); +#endif + ex_interrupt = *board_irq_stat & 0xff; + if (machine_is_ixdp2400()) + ixp2000_release_slowport(&old_cfg); + + if(!ex_interrupt) { + printk(KERN_ERR "Spurious IXDP2x00 CPLD interrupt!\n"); + return; + } + + for(i = 0; i < board_irq_count; i++) { + if(ex_interrupt & (1 << i)) { + int cpld_irq = IXP2000_BOARD_IRQ(0) + i; + generic_handle_irq(cpld_irq); + } + } + + desc->irq_data.chip->irq_unmask(&desc->irq_data); +} + +static struct irq_chip ixdp2x00_cpld_irq_chip = { + .irq_ack = ixdp2x00_irq_mask, + .irq_mask = ixdp2x00_irq_mask, + .irq_unmask = ixdp2x00_irq_unmask +}; + +void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigned long *mask_reg, unsigned long nr_of_irqs) +{ + unsigned int irq; + + ixp2000_init_irq(); + + if (!ixdp2x00_master_npu()) + return; + + board_irq_stat = stat_reg; + board_irq_mask = mask_reg; + board_irq_count = nr_of_irqs; + + *board_irq_mask = 0xffffffff; + + for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { + irq_set_chip_and_handler(irq, &ixdp2x00_cpld_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } + + /* Hook into PCI interrupt */ + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); +} + +/************************************************************************* + * IXDP2x00 memory map + *************************************************************************/ +static struct map_desc ixdp2x00_io_desc __initdata = { + .virtual = IXDP2X00_VIRT_CPLD_BASE, + .pfn = __phys_to_pfn(IXDP2X00_PHYS_CPLD_BASE), + .length = IXDP2X00_CPLD_SIZE, + .type = MT_DEVICE +}; + +void __init ixdp2x00_map_io(void) +{ + ixp2000_map_io(); + + iotable_init(&ixdp2x00_io_desc, 1); +} + +/************************************************************************* + * IXDP2x00-common PCI init + * + * The IXDP2[48]00 has a horrid PCI bus layout. Basically the board + * contains two NPUs (ingress and egress) connected over PCI, both running + * instances of the kernel. So far so good. Peers on the PCI bus running + * Linux is a common design in telecom systems. The problem is that instead + * of all the devices being controlled by a single host, different + * devices are controlled by different NPUs on the same bus, leading to + * multiple hosts on the bus. The exact bus layout looks like: + * + * Bus 0 + * Master NPU <-------------------+-------------------> Slave NPU + * | + * | + * P2P + * | + * + * Bus 1 | + * <--+------+---------+---------+------+--> + * | | | | | + * | | | | | + * ... Dev PMC Media Eth0 Eth1 ... + * + * The master controls all but Eth1, which is controlled by the + * slave. What this means is that the both the master and the slave + * have to scan the bus, but only one of them can enumerate the bus. + * In addition, after the bus is scanned, each kernel must remove + * the device(s) it does not control from the PCI dev list otherwise + * a driver on each NPU will try to manage it and we will have horrible + * conflicts. Oh..and the slave NPU needs to see the master NPU + * for Intel's drivers to work properly. Closed source drivers... + * + * The way we deal with this is fairly simple but ugly: + * + * 1) Let master scan and enumerate the bus completely. + * 2) Master deletes Eth1 from device list. + * 3) Slave scans bus and then deletes all but Eth1 (Eth0 on slave) + * from device list. + * 4) Find HW designers and LART them. + * + * The boards also do not do normal PCI IRQ routing, or any sort of + * sensical swizzling, so we just need to check where on the bus a + * device sits and figure out to which CPLD pin the interrupt is routed. + * See ixdp2[48]00.c files. + * + *************************************************************************/ +void ixdp2x00_slave_pci_postinit(void) +{ + struct pci_dev *dev; + + /* + * Remove PMC device is there is one + */ + if((dev = pci_get_bus_and_slot(1, IXDP2X00_PMC_DEVFN))) { + pci_remove_bus_device(dev); + pci_dev_put(dev); + } + + dev = pci_get_bus_and_slot(0, IXDP2X00_21555_DEVFN); + pci_remove_bus_device(dev); + pci_dev_put(dev); +} + +/************************************************************************** + * IXDP2x00 Machine Setup + *************************************************************************/ +static struct flash_platform_data ixdp2x00_platform_data = { + .map_name = "cfi_probe", + .width = 1, +}; + +static struct ixp2000_flash_data ixdp2x00_flash_data = { + .platform_data = &ixdp2x00_platform_data, + .nr_banks = 1 +}; + +static struct resource ixdp2x00_flash_resource = { + .start = 0xc4000000, + .end = 0xc4000000 + 0x00ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixdp2x00_flash = { + .name = "IXP2000-Flash", + .id = 0, + .dev = { + .platform_data = &ixdp2x00_flash_data, + }, + .num_resources = 1, + .resource = &ixdp2x00_flash_resource, +}; + +static struct ixp2000_i2c_pins ixdp2x00_i2c_gpio_pins = { + .sda_pin = IXDP2X00_GPIO_SDA, + .scl_pin = IXDP2X00_GPIO_SCL, +}; + +static struct platform_device ixdp2x00_i2c_controller = { + .name = "IXP2000-I2C", + .id = 0, + .dev = { + .platform_data = &ixdp2x00_i2c_gpio_pins, + }, + .num_resources = 0 +}; + +static struct platform_device *ixdp2x00_devices[] __initdata = { + &ixdp2x00_flash, + &ixdp2x00_i2c_controller +}; + +void __init ixdp2x00_init_machine(void) +{ + gpio_line_set(IXDP2X00_GPIO_I2C_ENABLE, 1); + gpio_line_config(IXDP2X00_GPIO_I2C_ENABLE, GPIO_OUT); + + platform_add_devices(ixdp2x00_devices, ARRAY_SIZE(ixdp2x00_devices)); + ixp2000_uart_init(); +} + diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c new file mode 100644 index 00000000..84835b20 --- /dev/null +++ b/arch/arm/mach-ixp2000/ixdp2x01.c @@ -0,0 +1,451 @@ +/* + * arch/arm/mach-ixp2000/ixdp2x01.c + * + * Code common to Intel IXDP2401 and IXDP2801 platforms + * + * Original Author: Andrzej Mialkowski <andrzej.mialkowski@intel.com> + * Maintainer: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright (C) 2002-2003 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/mm.h> +#include <linux/sched.h> +#include <linux/interrupt.h> +#include <linux/bitops.h> +#include <linux/pci.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/serial.h> +#include <linux/tty.h> +#include <linux/serial_core.h> +#include <linux/platform_device.h> +#include <linux/serial_8250.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/pgtable.h> +#include <asm/page.h> +#include <asm/system.h> +#include <mach/hardware.h> +#include <asm/mach-types.h> + +#include <asm/mach/pci.h> +#include <asm/mach/map.h> +#include <asm/mach/irq.h> +#include <asm/mach/time.h> +#include <asm/mach/arch.h> +#include <asm/mach/flash.h> + +/************************************************************************* + * IXDP2x01 IRQ Handling + *************************************************************************/ +static void ixdp2x01_irq_mask(struct irq_data *d) +{ + ixp2000_reg_wrb(IXDP2X01_INT_MASK_SET_REG, + IXP2000_BOARD_IRQ_MASK(d->irq)); +} + +static void ixdp2x01_irq_unmask(struct irq_data *d) +{ + ixp2000_reg_write(IXDP2X01_INT_MASK_CLR_REG, + IXP2000_BOARD_IRQ_MASK(d->irq)); +} + +static u32 valid_irq_mask; + +static void ixdp2x01_irq_handler(unsigned int irq, struct irq_desc *desc) +{ + u32 ex_interrupt; + int i; + + desc->irq_data.chip->irq_mask(&desc->irq_data); + + ex_interrupt = *IXDP2X01_INT_STAT_REG & valid_irq_mask; + + if (!ex_interrupt) { + printk(KERN_ERR "Spurious IXDP2X01 CPLD interrupt!\n"); + return; + } + + for (i = 0; i < IXP2000_BOARD_IRQS; i++) { + if (ex_interrupt & (1 << i)) { + int cpld_irq = IXP2000_BOARD_IRQ(0) + i; + generic_handle_irq(cpld_irq); + } + } + + desc->irq_data.chip->irq_unmask(&desc->irq_data); +} + +static struct irq_chip ixdp2x01_irq_chip = { + .irq_mask = ixdp2x01_irq_mask, + .irq_ack = ixdp2x01_irq_mask, + .irq_unmask = ixdp2x01_irq_unmask +}; + +/* + * We only do anything if we are the master NPU on the board. + * The slave NPU only has the ethernet chip going directly to + * the PCIB interrupt input. + */ +void __init ixdp2x01_init_irq(void) +{ + int irq = 0; + + /* initialize chip specific interrupts */ + ixp2000_init_irq(); + + if (machine_is_ixdp2401()) + valid_irq_mask = IXDP2401_VALID_IRQ_MASK; + else + valid_irq_mask = IXDP2801_VALID_IRQ_MASK; + + /* Mask all interrupts from CPLD, disable simulation */ + ixp2000_reg_write(IXDP2X01_INT_MASK_SET_REG, 0xffffffff); + ixp2000_reg_wrb(IXDP2X01_INT_SIM_REG, 0); + + for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { + if (irq & valid_irq_mask) { + irq_set_chip_and_handler(irq, &ixdp2x01_irq_chip, + handle_level_irq); + set_irq_flags(irq, IRQF_VALID); + } else { + set_irq_flags(irq, 0); + } + } + + /* Hook into PCI interrupts */ + irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); +} + + +/************************************************************************* + * IXDP2x01 memory map + *************************************************************************/ +static struct map_desc ixdp2x01_io_desc __initdata = { + .virtual = IXDP2X01_VIRT_CPLD_BASE, + .pfn = __phys_to_pfn(IXDP2X01_PHYS_CPLD_BASE), + .length = IXDP2X01_CPLD_REGION_SIZE, + .type = MT_DEVICE +}; + +static void __init ixdp2x01_map_io(void) +{ + ixp2000_map_io(); + iotable_init(&ixdp2x01_io_desc, 1); +} + + +/************************************************************************* + * IXDP2x01 serial ports + *************************************************************************/ +static struct plat_serial8250_port ixdp2x01_serial_port1[] = { + { + .mapbase = (unsigned long)IXDP2X01_UART1_PHYS_BASE, + .membase = (char *)IXDP2X01_UART1_VIRT_BASE, + .irq = IRQ_IXDP2X01_UART1, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM32, + .regshift = 2, + .uartclk = IXDP2X01_UART_CLK, + }, + { } +}; + +static struct resource ixdp2x01_uart_resource1 = { + .start = IXDP2X01_UART1_PHYS_BASE, + .end = IXDP2X01_UART1_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixdp2x01_serial_device1 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM1, + .dev = { + .platform_data = ixdp2x01_serial_port1, + }, + .num_resources = 1, + .resource = &ixdp2x01_uart_resource1, +}; + +static struct plat_serial8250_port ixdp2x01_serial_port2[] = { + { + .mapbase = (unsigned long)IXDP2X01_UART2_PHYS_BASE, + .membase = (char *)IXDP2X01_UART2_VIRT_BASE, + .irq = IRQ_IXDP2X01_UART2, + .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, + .iotype = UPIO_MEM32, + .regshift = 2, + .uartclk = IXDP2X01_UART_CLK, + }, + { } +}; + +static struct resource ixdp2x01_uart_resource2 = { + .start = IXDP2X01_UART2_PHYS_BASE, + .end = IXDP2X01_UART2_PHYS_BASE + 0xffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixdp2x01_serial_device2 = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM2, + .dev = { + .platform_data = ixdp2x01_serial_port2, + }, + .num_resources = 1, + .resource = &ixdp2x01_uart_resource2, +}; + +static void ixdp2x01_uart_init(void) +{ + platform_device_register(&ixdp2x01_serial_device1); + platform_device_register(&ixdp2x01_serial_device2); +} + + +/************************************************************************* + * IXDP2x01 timer tick configuration + *************************************************************************/ +static unsigned int ixdp2x01_clock; + +static int __init ixdp2x01_clock_setup(char *str) +{ + ixdp2x01_clock = simple_strtoul(str, NULL, 10); + + return 1; +} + +__setup("ixdp2x01_clock=", ixdp2x01_clock_setup); + +static void __init ixdp2x01_timer_init(void) +{ + if (!ixdp2x01_clock) + ixdp2x01_clock = 50000000; + + ixp2000_init_time(ixdp2x01_clock); +} + +static struct sys_timer ixdp2x01_timer = { + .init = ixdp2x01_timer_init, + .offset = ixp2000_gettimeoffset, +}; + +/************************************************************************* + * IXDP2x01 PCI + *************************************************************************/ +void __init ixdp2x01_pci_preinit(void) +{ + ixp2000_reg_write(IXP2000_PCI_ADDR_EXT, 0x00000000); + ixp2000_pci_preinit(); + pcibios_setup("firmware"); +} + +#define DEVPIN(dev, pin) ((pin) | ((dev) << 3)) + +static int __init ixdp2x01_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) +{ + u8 bus = dev->bus->number; + u32 devpin = DEVPIN(PCI_SLOT(dev->devfn), pin); + struct pci_bus *tmp_bus = dev->bus; + + /* Primary bus, no interrupts here */ + if (bus == 0) { + return -1; + } + + /* Lookup first leaf in bus tree */ + while ((tmp_bus->parent != NULL) && (tmp_bus->parent->parent != NULL)) { + tmp_bus = tmp_bus->parent; + } + + /* Select between known bridges */ + switch (tmp_bus->self->devfn | (tmp_bus->self->bus->number << 8)) { + /* Device is located after first MB bridge */ + case 0x0008: + if (tmp_bus == dev->bus) { + /* Device is located directly after first MB bridge */ + switch (devpin) { + case DEVPIN(1, 1): /* Onboard 82546 ch 0 */ + if (machine_is_ixdp2401()) + return IRQ_IXDP2401_INTA_82546; + return -1; + case DEVPIN(1, 2): /* Onboard 82546 ch 1 */ + if (machine_is_ixdp2401()) + return IRQ_IXDP2401_INTB_82546; + return -1; + case DEVPIN(0, 1): /* PMC INTA# */ + return IRQ_IXDP2X01_SPCI_PMC_INTA; + case DEVPIN(0, 2): /* PMC INTB# */ + return IRQ_IXDP2X01_SPCI_PMC_INTB; + case DEVPIN(0, 3): /* PMC INTC# */ + return IRQ_IXDP2X01_SPCI_PMC_INTC; + case DEVPIN(0, 4): /* PMC INTD# */ + return IRQ_IXDP2X01_SPCI_PMC_INTD; + } + } + break; + case 0x0010: + if (tmp_bus == dev->bus) { + /* Device is located directly after second MB bridge */ + /* Secondary bus of second bridge */ + switch (devpin) { + case DEVPIN(0, 1): /* DB#0 */ + return IRQ_IXDP2X01_SPCI_DB_0; + case DEVPIN(1, 1): /* DB#1 */ + return IRQ_IXDP2X01_SPCI_DB_1; + } + } else { + /* Device is located indirectly after second MB bridge */ + /* Not supported now */ + } + break; + } + + return -1; +} + + +static int ixdp2x01_pci_setup(int nr, struct pci_sys_data *sys) +{ + sys->mem_offset = 0xe0000000; + + if (machine_is_ixdp2801() || machine_is_ixdp28x5()) + sys->mem_offset -= ((*IXP2000_PCI_ADDR_EXT & 0xE000) << 16); + + return ixp2000_pci_setup(nr, sys); +} + +struct hw_pci ixdp2x01_pci __initdata = { + .nr_controllers = 1, + .setup = ixdp2x01_pci_setup, + .preinit = ixdp2x01_pci_preinit, + .scan = ixp2000_pci_scan_bus, + .map_irq = ixdp2x01_pci_map_irq, +}; + +int __init ixdp2x01_pci_init(void) +{ + if (machine_is_ixdp2401() || machine_is_ixdp2801() ||\ + machine_is_ixdp28x5()) + pci_common_init(&ixdp2x01_pci); + + return 0; +} + +subsys_initcall(ixdp2x01_pci_init); + +/************************************************************************* + * IXDP2x01 Machine Initialization + *************************************************************************/ +static struct flash_platform_data ixdp2x01_flash_platform_data = { + .map_name = "cfi_probe", + .width = 1, +}; + +static unsigned long ixdp2x01_flash_bank_setup(unsigned long ofs) +{ + ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, + ((ofs >> IXDP2X01_FLASH_WINDOW_BITS) | IXDP2X01_CPLD_FLASH_INTERN)); + return (ofs & IXDP2X01_FLASH_WINDOW_MASK); +} + +static struct ixp2000_flash_data ixdp2x01_flash_data = { + .platform_data = &ixdp2x01_flash_platform_data, + .bank_setup = ixdp2x01_flash_bank_setup +}; + +static struct resource ixdp2x01_flash_resource = { + .start = 0xc4000000, + .end = 0xc4000000 + 0x01ffffff, + .flags = IORESOURCE_MEM, +}; + +static struct platform_device ixdp2x01_flash = { + .name = "IXP2000-Flash", + .id = 0, + .dev = { + .platform_data = &ixdp2x01_flash_data, + }, + .num_resources = 1, + .resource = &ixdp2x01_flash_resource, +}; + +static struct ixp2000_i2c_pins ixdp2x01_i2c_gpio_pins = { + .sda_pin = IXDP2X01_GPIO_SDA, + .scl_pin = IXDP2X01_GPIO_SCL, +}; + +static struct platform_device ixdp2x01_i2c_controller = { + .name = "IXP2000-I2C", + .id = 0, + .dev = { + .platform_data = &ixdp2x01_i2c_gpio_pins, + }, + .num_resources = 0 +}; + +static struct platform_device *ixdp2x01_devices[] __initdata = { + &ixdp2x01_flash, + &ixdp2x01_i2c_controller +}; + +static void __init ixdp2x01_init_machine(void) +{ + ixp2000_reg_wrb(IXDP2X01_CPLD_FLASH_REG, + (IXDP2X01_CPLD_FLASH_BANK_MASK | IXDP2X01_CPLD_FLASH_INTERN)); + + ixdp2x01_flash_data.nr_banks = + ((*IXDP2X01_CPLD_FLASH_REG & IXDP2X01_CPLD_FLASH_BANK_MASK) + 1); + + platform_add_devices(ixdp2x01_devices, ARRAY_SIZE(ixdp2x01_devices)); + ixp2000_uart_init(); + ixdp2x01_uart_init(); +} + + +#ifdef CONFIG_ARCH_IXDP2401 +MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .boot_params = 0x00000100, + .map_io = ixdp2x01_map_io, + .init_irq = ixdp2x01_init_irq, + .timer = &ixdp2x01_timer, + .init_machine = ixdp2x01_init_machine, +MACHINE_END +#endif + +#ifdef CONFIG_ARCH_IXDP2801 +MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .boot_params = 0x00000100, + .map_io = ixdp2x01_map_io, + .init_irq = ixdp2x01_init_irq, + .timer = &ixdp2x01_timer, + .init_machine = ixdp2x01_init_machine, +MACHINE_END + +/* + * IXDP28x5 is basically an IXDP2801 with a different CPU but Intel + * changed the machine ID in the bootloader + */ +MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") + /* Maintainer: MontaVista Software, Inc. */ + .boot_params = 0x00000100, + .map_io = ixdp2x01_map_io, + .init_irq = ixdp2x01_init_irq, + .timer = &ixdp2x01_timer, + .init_machine = ixdp2x01_init_machine, +MACHINE_END +#endif + + diff --git a/arch/arm/mach-ixp2000/pci.c b/arch/arm/mach-ixp2000/pci.c new file mode 100644 index 00000000..f797c5f5 --- /dev/null +++ b/arch/arm/mach-ixp2000/pci.c @@ -0,0 +1,246 @@ +/* + * arch/arm/mach-ixp2000/pci.c + * + * PCI routines for IXDP2400/IXDP2800 boards + * + * Original Author: Naeem Afzal <naeem.m.afzal@intel.com> + * Maintained by: Deepak Saxena <dsaxena@plexity.net> + * + * Copyright 2002 Intel Corp. + * Copyright (C) 2003-2004 MontaVista Software, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include <linux/sched.h> +#include <linux/kernel.h> +#include <linux/pci.h> +#include <linux/interrupt.h> +#include <linux/mm.h> +#include <linux/init.h> +#include <linux/ioport.h> +#include <linux/delay.h> +#include <linux/io.h> + +#include <asm/irq.h> +#include <asm/system.h> +#include <mach/hardware.h> + +#include <asm/mach/pci.h> + +static volatile int pci_master_aborts = 0; + +static int clear_master_aborts(void); + +u32 * +ixp2000_pci_config_addr(unsigned int bus_nr, unsigned int devfn, int where) +{ + u32 *paddress; + + if (PCI_SLOT(devfn) > 7) + return 0; + + /* Must be dword aligned */ + where &= ~3; + + /* + * For top bus, generate type 0, else type 1 + */ + if (!bus_nr) { + /* only bits[23:16] are used for IDSEL */ + paddress = (u32 *) (IXP2000_PCI_CFG0_VIRT_BASE + | (1 << (PCI_SLOT(devfn) + 16)) + | (PCI_FUNC(devfn) << 8) | where); + } else { + paddress = (u32 *) (IXP2000_PCI_CFG1_VIRT_BASE + | (bus_nr << 16) + | (PCI_SLOT(devfn) << 11) + | (PCI_FUNC(devfn) << 8) | where); + } + + return paddress; +} + +/* + * Mask table, bits to mask for quantity of size 1, 2 or 4 bytes. + * 0 and 3 are not valid indexes... + */ +static u32 bytemask[] = { + /*0*/ 0, + /*1*/ 0xff, + /*2*/ 0xffff, + /*3*/ 0, + /*4*/ 0xffffffff, +}; + + +int ixp2000_pci_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *value) +{ + u32 n; + u32 *addr; + + n = where % 4; + + addr = ixp2000_pci_config_addr(bus->number, devfn, where); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + + pci_master_aborts = 0; + *value = (*addr >> (8*n)) & bytemask[size]; + if (pci_master_aborts) { + pci_master_aborts = 0; + *value = 0xffffffff; + return PCIBIOS_DEVICE_NOT_FOUND; + } + + return PCIBIOS_SUCCESSFUL; +} + +/* + * We don't do error checks by calling clear_master_aborts() b/c the + * assumption is that the caller did a read first to make sure a device + * exists. + */ +int ixp2000_pci_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 value) +{ + u32 mask; + u32 *addr; + u32 temp; + + mask = ~(bytemask[size] << ((where % 0x4) * 8)); + addr = ixp2000_pci_config_addr(bus->number, devfn, where); + if (!addr) + return PCIBIOS_DEVICE_NOT_FOUND; + temp = (u32) (value) << ((where % 0x4) * 8); + *addr = (*addr & mask) | temp; + + clear_master_aborts(); + + return PCIBIOS_SUCCESSFUL; +} + + +static struct pci_ops ixp2000_pci_ops = { + .read = ixp2000_pci_read_config, + .write = ixp2000_pci_write_config +}; + +struct pci_bus *ixp2000_pci_scan_bus(int nr, struct pci_sys_data *sysdata) +{ + return pci_scan_bus(sysdata->busnr, &ixp2000_pci_ops, sysdata); +} + + +int ixp2000_pci_abort_handler(unsigned long addr, unsigned int fsr, struct pt_regs *regs) +{ + + volatile u32 temp; + unsigned long flags; + + pci_master_aborts = 1; + + local_irq_save(flags); + temp = *(IXP2000_PCI_CONTROL); + if (temp & ((1 << 8) | (1 << 5))) { + ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); + } + + temp = *(IXP2000_PCI_CMDSTAT); + if (temp & (1 << 29)) { + while (temp & (1 << 29)) { + ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); + temp = *(IXP2000_PCI_CMDSTAT); + } + } + local_irq_restore(flags); + + /* + * If it was an imprecise abort, then we need to correct the + * return address to be _after_ the instruction. + */ + if (fsr & (1 << 10)) + regs->ARM_pc += 4; + + return 0; +} + +int +clear_master_aborts(void) +{ + volatile u32 temp; + unsigned long flags; + + local_irq_save(flags); + temp = *(IXP2000_PCI_CONTROL); + if (temp & ((1 << 8) | (1 << 5))) { + ixp2000_reg_wrb(IXP2000_PCI_CONTROL, temp); + } + + temp = *(IXP2000_PCI_CMDSTAT); + if (temp & (1 << 29)) { + while (temp & (1 << 29)) { + ixp2000_reg_write(IXP2000_PCI_CMDSTAT, temp); + temp = *(IXP2000_PCI_CMDSTAT); + } + } + local_irq_restore(flags); + + return 0; +} + +void __init +ixp2000_pci_preinit(void) +{ +#ifndef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO + /* + * Configure the PCI unit to properly byteswap I/O transactions, + * and verify that it worked. + */ + ixp2000_reg_write(IXP2000_PCI_CONTROL, + (*IXP2000_PCI_CONTROL | PCI_CONTROL_IEE)); + + if ((*IXP2000_PCI_CONTROL & PCI_CONTROL_IEE) == 0) + panic("IXP2000: PCI I/O is broken on this ixp model, and " + "the needed workaround has not been configured in"); +#endif + + hook_fault_code(16+6, ixp2000_pci_abort_handler, SIGBUS, 0, + "PCI config cycle to non-existent device"); +} + + +/* + * IXP2000 systems often have large resource requirements, so we just + * use our own resource space. + */ +static struct resource ixp2000_pci_mem_space = { + .start = 0xe0000000, + .end = 0xffffffff, + .flags = IORESOURCE_MEM, + .name = "PCI Mem Space" +}; + +static struct resource ixp2000_pci_io_space = { + .start = 0x00010000, + .end = 0x0001ffff, + .flags = IORESOURCE_IO, + .name = "PCI I/O Space" +}; + +int ixp2000_pci_setup(int nr, struct pci_sys_data *sys) +{ + if (nr >= 1) + return 0; + + sys->resource[0] = &ixp2000_pci_io_space; + sys->resource[1] = &ixp2000_pci_mem_space; + sys->resource[2] = NULL; + + return 1; +} + |