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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-0/+79
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-0/+12
| | | | Fixes #3047.
* Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-0/+21
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* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-5/+7
| | | | | | | | | | - FfData now keeps track of the module and underlying cell, if any (so calling emit on FfData created from a cell will replace the existing cell) - FfData implementation is split off to its own .cc file for faster compilation - the "flip FF data sense by inserting inverters in front and after" functionality that zinit uses is moved onto FfData class and beefed up to have dffsr support, to support more use cases
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2440-79/+79
|\ | | | | Fix "make vgtest"
| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* | sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
| | | | | | | | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
|/ | | | | | | | - Root AST_PREFIX nodes are now subject to genblk expansion to allow them to refer to a locally-visible generate block - Part selects on AST_PREFIX member leafs can now refer to generate block items (previously would not resolve and raise an error) - Add source location information to AST_PREFIX nodes
* abc9: make re-entrant (#2993)Eddie Hung2021-09-091-0/+20
| | | | | | | | | * Add testcase * Cleanup some state at end of abc9 * Re-assign abc9_box_id from scratch * Suppress delete unless prep_bypass did something
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-0/+14
| | | | | * Add testcase * holes module to instantiate cells with NEW_ID
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
| | | | | | | | | | | * Add close bracket * Add testcase * Replace cell type/param if in unmap_design * Improve abc9_box error message too * Update comment as per review
* sv: support declaration in generate for initializationZachary Snow2021-08-318-0/+114
| | | | | | | | This is accomplished by generating a unique name for the genvar, renaming references to the genvar only in the loop's initialization, guard, and incrementation, and finally adding a localparam inside the loop body with the original name so that the genvar can be shadowed as expected.
* sv: support declaration in procedural for initializationZachary Snow2021-08-304-0/+56
| | | | | In line with other tools, this adds an extra wrapping block around such for loops to appropriately scope the variable.
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-2/+2
| | | | | | | | | | Previously, opt_clean would reconnect all ports (including FF Q ports) to a "canonical" SigBit chosen by complex rules, but would leave the init attribute on the old wire. This change applies the same canonicalization rules to the init attributes, ensuring that init moves to wherever the Q port moved. Part of another jab at #2920.
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
| | | | | | | | | * deal with active-low tristate * remove empty port * update sim models * add expected lut1 to tests
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-0/+22
| | | | Fixes #2962.
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-141-0/+36
| | | | If all of us are wide, then none of us are!
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-149-1/+228
| | | | This unlocks wide port recognition by default.
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-133-0/+904
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* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-131-0/+205
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* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-122-0/+108
| | | | | | | | | | | | | | | | | - User-defined types must be data types. Using a net type (e.g. wire) is a syntax error. - User-defined types without a net type are always variables (i.e. logic). - Nets and variables can now be explicitly declared using user-defined types: typedef logic [1:0] W; wire W w; typedef logic [1:0] V; var V v; Fixes #2846
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
| | | | | | | | | | These parts keep rereading a Verilog module, then using chparam to test it with various parameter combinations. Since the default parameters are on the large side, this spends a lot of time needlessly elaborating the default parametrization that will then be discarded. Fix it with -deref and manual hierarchy call. Shaves 30s off the test time on my machine.
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-113-1/+55
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* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-112-5/+5
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* Add v2 memory cells.Marcelina Kościelnicka2021-08-118-32/+32
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* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-082-1/+43
| | | | Partial #2920 fix.
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-293-0/+323
| | | | | | | | If width of a case expression was large, explicit patterns could cause the existing logic to take an extremely long time, or exhaust the maximum size of the underlying set. For cases where all of the patterns are fully defined and there are no constants in the case expression, this change uses a simple set to track which patterns have been seen.
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+18
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* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
| | | | Fixes #2061.
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-0/+23
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* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-4/+4
| | | | Fixes #2447.
* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-272-0/+15
| | | | | | | | This adds one simple piece of functionality to opt_expr: when a cell port is connected to a fully-constant signal (as determined by sigmap), the port is reconnected directly to the constant value. This is just enough optimization to fix the "non-constant $meminit input" problem without requiring a full opt_clean or a separate pass.
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-1614-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This doesn't do anything useful yet: the patch just adds support for the syntax to the lexer and parser and adds some tests to check the syntax parses properly. This generates AST nodes, but doesn't yet generate RTLIL. Since our existing hierarchical_identifier parser doesn't allow bit selects (so you can't do something like foo[1].bar[2].baz), I've also not added support for a trailing bit select (the "constant_bit_select" non-terminal in "bind_target_instance" in the spec). If we turn out to need this in future, we'll want to augment hierarchical_identifier and its other users too. Note that you can't easily use the BNF from the spec: bind_directive ::= "bind" bind_target_scope [ : bind_target_instance_list] bind_instantiation ; | "bind" bind_target_instance bind_instantiation ; even if you fix the lookahead problem, because code like this matches both branches in the BNF: bind a b b_i (.*); The problem is that 'a' could either be a module name or a degenerate hierarchical reference. This seems to be a genuine syntactic ambiguity, which the spec resolves (p739) by saying that we have to wait until resolution time (the hierarchy pass) and take whatever is defined, treating 'a' as an instance name if it names both an instance and a module. To keep the parser simple, it currently accepts this invalid syntax: bind a.b : c d e (.*); This is invalid because we're in the first branch of the BNF above, so the "a.b" term should match bind_target_scope: a module or interface identifier, not an arbitrary hierarchical identifier. This will fail in the hierarchy pass (when it's implemented in a future patch).
* sv: fix two struct access bugsZachary Snow2021-07-152-0/+92
| | | | | - preserve signedness of struct members - fix initial width detection of struct members (e.g., in case expressions)
* Add a test for interfaces on modules loaded on-demandRupert Swarbrick2021-07-145-2/+48
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* sv: fix up end label checkingZachary Snow2021-06-166-0/+80
| | | | | | | - disallow [gen]blocks with an end label but not begin label - check validity of module end label - fix memory leak of package name and end label - fix memory leak of module end label
* Add regression test for #2824.Marcelina Kościelnicka2021-06-111-0/+7
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* Merge pull request #2817 from YosysHQ/claire/fixemailsClaire Xen2021-06-097-79/+79
|\ | | | | Fixing old e-mail addresses and deadnames
| * More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
| * More deadname stuffClaire Xenia Wolf2021-06-091-1/+1
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| * Use HTTPS for website links, gatecat emailClaire Xenia Wolf2021-06-091-1/+1
| | | | | | | | | | | | | | | | | | | | git ls-tree -r --name-only HEAD | xargs sed -i -rf ~/fixemails.sed s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+(Shah|gatecat)\s+<(dave|david|gatecat)@(symbioticeda.com|yosyshq.com|ds0.me)>/gatecat <gatecat@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/|http://yosyshq.net/yosys/,https://yosyshq.net/yosys/,g;
| * Fix files with CRLF line endingsClaire Xenia Wolf2021-06-093-73/+73
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| * Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
| | | | | | | | | | | | | | | | s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi; s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi; s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi; s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi; s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
* | verilog: check for module scope identifiers during width detectionZachary Snow2021-06-081-0/+11
| | | | | | | | | | | | | | | | The recent fix for case expression width detection causes the width of the expressions to be queried before they are simplified. Because the logic supporting module scope identifiers only existed in simplify, looking them up would fail during width detection. This moves the logic to a common helper used in both simplify() and detectSignWidthWorker().
* | mem2reg: tolerate out of bounds constant accessesZachary Snow2021-06-083-0/+52
|/ | | | This brings the mem2reg behavior in line with the nomem2reg behavior.
* sv: support tasks and functions within packagesZachary Snow2021-06-012-0/+34
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* memory_map: Improve start_offset handling.Marcelina Kościelnicka2021-05-311-0/+100
| | | | Fixes #2775.
* memory_bram: Reuse extract_rdff helper for make_outreg.Marcelina Kościelnicka2021-05-254-17/+14
| | | | | Also properly skip read ports with init value or reset when not making use of make_outreg. Proper support for matching those will land later.
* verilog: fix case expression sign and width handlingZachary Snow2021-05-252-0/+108
| | | | | | | | | - The case expression and case item expressions are extended to the maximum width among them, and are only interpreted as signed if all of them are signed - Add overall width and sign detection for AST_CASE - Add sign argument to genWidthRTLIL helper - Coverage for both const and non-const case statements
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-17 20:57:27 +0000