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* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
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* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
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* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Updated the liberty parser to accept [A:B] ranges (AST has not been ↵Niels Moseley2019-03-246-0/+541
| | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
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| * fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
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| * Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value".
| * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-253-3/+1
| | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
| * Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-242-1/+68
| |\ | | | | | | Define basic_cell_type() function and use it to derive the cell type …
| | * Address requested changes - don't require non-$ name.Jim Lawson2019-02-222-4/+7
| | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
| | * Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-192-1/+65
| | | | | | | | | | | | Add simple test.
| * | Merge pull request #824 from litghost/fix_reduce_on_ffClifford Wolf2019-02-242-0/+24
| |\ \ | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter.
| | * | Fix WREDUCE on FF not fixing ARST_VALUE parameter.Keith Rothman2019-02-222-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | | Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
| | | | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
| * | Remove simple_defparam testsEddie Hung2019-02-201-21/+0
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| * | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-175-8/+93
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* | | | One more merge conflictEddie Hung2019-02-171-6/+1
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* | | | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-175-8/+97
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| * | | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
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| * | | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-154-7/+92
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
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* | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
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* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
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| * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
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| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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| * | Extend testcaseEddie Hung2019-02-061-2/+34
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| * | Add testcaseEddie Hung2019-02-061-0/+10
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
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* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
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* | Add testsEddie Hung2019-02-0416-8/+109
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* Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-022-0/+44
|\ | | | | opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-021-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-021-0/+5
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-021-8/+14
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-022-0/+15
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | cmp2lut: new techmap pass.whitequark2019-01-023-2/+33
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* opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-313-0/+23
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* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-1/+1
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* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-163-26/+3
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-072-4/+1
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-23/+3
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* | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-072-0/+20
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* | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-058-0/+45
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* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-1/+1
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