aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Collapse)AuthorAgeFilesLines
* Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #976 from YosysHQ/clifford/fix974Clifford Wolf2019-05-031-0/+22
|\ | | | | Fix width detection of memory access with bit slice
| * Add splitcmplxassign test case and silence splitcmplxassign warningClifford Wolf2019-05-011-0/+22
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Fix typo in tests/svinterfaces/runone.shClifford Wolf2019-05-031-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | fail svinterfaces testcases on yosys error exitJakob Wenzel2019-05-021-2/+2
| |
* | Fix #938 - Crash occurs in case when use write_firrtl commandJim Lawson2019-05-012-0/+23
|/ | | | | | Add missing memory initialization. Sanity-check memory parameters. Add Cell pointer to memory object (for error reporting).
* Updaye pmux2shiftx testClifford Wolf2019-04-221-2/+2
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #909 from zachjs/masterClifford Wolf2019-04-222-0/+48
|\ | | | | support repeat loops with constant repeat counts outside of constant functions
| * support repeat loops with constant repeat counts outside of constant functionsZachary Snow2019-04-092-0/+48
| |
* | Merge pull request #944 from YosysHQ/clifford/pmux2shiftxClifford Wolf2019-04-222-0/+62
|\ \ | | | | | | Add pmux2shiftx command
| * | Improve "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in "pmux2shiftx"Clifford Wolf2019-04-201-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improvements in pmux2shiftxClifford Wolf2019-04-202-20/+30
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add test for pmux2shiftxClifford Wolf2019-04-202-0/+52
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Fix testsClifford Wolf2019-04-212-2/+3
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add tests/aiger/.gitignoreClifford Wolf2019-04-191-0/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Add retime testEddie Hung2019-04-051-0/+6
|/
* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-271-1/+1
|
* Liberty file parser now accepts superfluous ;Niels Moseley2019-03-273-2/+97
|
* Fix "verific -extnets" for more complex situationsClifford Wolf2019-03-261-0/+22
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Updated the liberty parser to accept [A:B] ranges (AST has not been ↵Niels Moseley2019-03-246-0/+541
| | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'.
* Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-03-1911-31/+175
|\
| * fix local name resolution in prefix constructsZachary Snow2019-03-181-0/+56
| |
| * Fix handling of task output ports in clocked always blocks, fixes #857Clifford Wolf2019-03-071-0/+19
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v failsJim Lawson2019-03-041-0/+1
| | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value".
| * Hotfix for "make test"Clifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Add "write_verilog -siminit"Clifford Wolf2019-02-281-1/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fix FIRRTL to Verilog process instance subfield assignment.Jim Lawson2019-02-253-3/+1
| | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
| * Merge pull request #812 from ucb-bar/arrayhierarchyfixesClifford Wolf2019-02-242-1/+68
| |\ | | | | | | Define basic_cell_type() function and use it to derive the cell type …
| | * Address requested changes - don't require non-$ name.Jim Lawson2019-02-222-4/+7
| | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types.
| | * Fix normal (non-array) hierarchy -auto-top.Jim Lawson2019-02-192-1/+65
| | | | | | | | | | | | Add simple test.
| * | Merge pull request #824 from litghost/fix_reduce_on_ffClifford Wolf2019-02-242-0/+24
| |\ \ | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter.
| | * | Fix WREDUCE on FF not fixing ARST_VALUE parameter.Keith Rothman2019-02-222-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
| * | | Fix handling of defparam for when default_nettype is noneClifford Wolf2019-02-241-0/+2
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Revert "Add -B option to autotest.sh to append to backend_opts"Eddie Hung2019-02-211-4/+2
| | | | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.
| * | Remove simple_defparam testsEddie Hung2019-02-201-21/+0
| | |
| * | Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-175-8/+93
| |\ \
* | | | One more merge conflictEddie Hung2019-02-171-6/+1
| | | |
* | | | Merge https://github.com/YosysHQ/yosys into read_aigerEddie Hung2019-02-175-8/+97
|\ \ \ \ | | |/ / | |/| |
| * | | Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | | |
| * | | Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-154-7/+92
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail.
* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
| | |
* | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
| | |
* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
|\ \ \ | | |/ | |/|
| * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| | |
| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| | |
| * | Extend testcaseEddie Hung2019-02-061-2/+34
| | |
| * | Add testcaseEddie Hung2019-02-061-0/+10
| |/
* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
| |
* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
| |