aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Expand)AuthorAgeFilesLines
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* sta: very crude static timing analysis passLofty2021-11-251-0/+81
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
* iopadmap: Add native support for negative-polarity output enable.Marcelina Kościelnicka2021-11-092-3/+3
* dfflegalize: Add tests for aldff lowering.Marcelina Kościelnicka2021-10-272-0/+240
* dfflegalize: Add tests targetting aldff.Marcelina Kościelnicka2021-10-277-7/+320
* dfflegalize: Refactor, add aldff support.Marcelina Kościelnicka2021-10-279-73/+46
* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-254-0/+79
* extract_reduce: Refactor and fix input signal construction.Marcelina Kościelnicka2021-10-211-0/+12
* Fixes in vcdcd.pl for newer Perl versionsClaire Xenia Wolf2021-10-191-3/+3
* Fix a regression from #3035.Marcelina Kościelnicka2021-10-081-0/+21
* FfData: some refactoring.Marcelina Kościelnicka2021-10-072-5/+7
* Merge pull request #3014 from YosysHQ/claire/fix-vgtestClaire Xen2021-09-2440-79/+79
|\
| * Fix "make vgtest" so it runs to the end (but now it fails ;)Claire Xenia Wolf2021-09-2340-79/+79
* | sv: support wand and wor of data typesZachary Snow2021-09-212-0/+39
* | verilog: fix multiple AST_PREFIX scope resolution issuesZachary Snow2021-09-212-0/+100
|/
* abc9: make re-entrant (#2993)Eddie Hung2021-09-091-0/+20
* abc9: holes module to instantiate cells with NEW_ID (#2992)Eddie Hung2021-09-091-0/+14
* abc9: replace cell type/parameters if derived type already processed (#2991)Eddie Hung2021-09-091-0/+7
* sv: support declaration in generate for initializationZachary Snow2021-08-318-0/+114
* sv: support declaration in procedural for initializationZachary Snow2021-08-304-0/+56
* opt_clean: Make the init attribute follow the FF's Q.Marcelina Kościelnicka2021-08-221-2/+2
* Gowin: deal with active-low tristate (#2971)Pepijn de Vos2021-08-201-1/+2
* proc_prune: Make assign removal and promotion per-bit, remember promoted bits.Marcelina Kościelnicka2021-08-141-0/+22
* Add opt_mem_widen pass.Marcelina Kościelnicka2021-08-141-0/+36
* memory_share: Add -nosat and -nowiden options.Marcelina Kościelnicka2021-08-149-1/+228
* memory_dff: Recognize soft transparency logic.Marcelina Kościelnicka2021-08-133-0/+904
* Add new opt_mem_priority pass.Marcelina Kościelnicka2021-08-131-0/+205
* sv: improve support for wire and var with user-defined typesBrett Witherspoon2021-08-122-0/+108
* test/arch/{ecp5,ice40}/memories.ys: Use read_verilog -defer.Marcelina Kościelnicka2021-08-112-78/+156
* memory_dff: Recognize read ports with reset / initial value.Marcelina Kościelnicka2021-08-113-1/+55
* proc_memwr: Use the v2 memwr cell.Marcelina Kościelnicka2021-08-112-5/+5
* Add v2 memory cells.Marcelina Kościelnicka2021-08-118-32/+32
* opt_merge: Use FfInitVals.Marcelina Kościelnicka2021-08-082-1/+43
* proc_rmdead: use explicit pattern set when there are no wildcardsZachary Snow2021-07-293-0/+323
* genrtlil: add width detection for AST_PREFIX nodesZachary Snow2021-07-291-0/+18
* opt_lut: Allow more than one -dlogic per cell type.Marcelina Kościelnicka2021-07-291-0/+24
* verilog: save and restore overwritten macro argumentsZachary Snow2021-07-282-0/+23
* verilog: Emit $meminit_v2 cell.Marcelina Kościelnicka2021-07-281-4/+4
* opt_expr: Propagate constants to port connections.Marcelina Kościelnicka2021-07-272-0/+15
* Add support for parsing the SystemVerilog 'bind' constructRupert Swarbrick2021-07-1614-0/+164
* sv: fix two struct access bugsZachary Snow2021-07-152-0/+92
* Add a test for interfaces on modules loaded on-demandRupert Swarbrick2021-07-145-2/+48
* sv: fix up end label checkingZachary Snow2021-06-166-0/+80
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 06:51:43 +0000