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Author
Age
Files
Lines
*
Revert "Add -B option to autotest.sh to append to backend_opts"
Eddie Hung
2019-02-21
1
-4
/
+2
*
Remove simple_defparam tests
Eddie Hung
2019-02-20
1
-21
/
+0
*
Merge https://github.com/YosysHQ/yosys into dff_init
Eddie Hung
2019-02-17
5
-8
/
+93
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\
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*
Append (instead of over-writing) EXTRA_FLAGS
Jim Lawson
2019-02-15
1
-1
/
+1
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*
Update cells supported for verilog to FIRRTL conversion.
Jim Lawson
2019-02-15
4
-7
/
+92
*
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Add tests for simple cases using defparam
Eddie Hung
2019-02-06
1
-0
/
+21
*
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Add -B option to autotest.sh to append to backend_opts
Eddie Hung
2019-02-06
1
-2
/
+4
*
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Extend testcase
Eddie Hung
2019-02-06
1
-2
/
+34
*
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Add testcase
Eddie Hung
2019-02-06
1
-0
/
+10
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/
*
Remove asicworld tests for (unsupported) switch-level modelling
Clifford Wolf
2019-01-27
4
-69
/
+0
*
Merge pull request #770 from whitequark/opt_expr_cmp
Clifford Wolf
2019-01-02
2
-0
/
+44
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\
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*
opt_expr: improve simplification of comparisons with large constants.
whitequark
2019-01-02
1
-0
/
+18
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*
opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.
whitequark
2019-01-02
1
-0
/
+5
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*
opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.
whitequark
2019-01-02
1
-8
/
+14
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*
opt_expr: simplify any unsigned comparisons with all-0 and all-1.
whitequark
2019-01-02
2
-0
/
+15
*
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cmp2lut: new techmap pass.
whitequark
2019-01-02
3
-2
/
+33
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/
*
opt_lut: eliminate LUTs evaluating to constants or inputs.
whitequark
2018-12-31
3
-0
/
+23
*
Squelch a little more trailing whitespace
Larry Doolittle
2018-12-29
1
-1
/
+1
*
Merge pull request #724 from whitequark/equiv_opt
Clifford Wolf
2018-12-16
3
-26
/
+3
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\
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*
equiv_opt: pass -D EQUIV when techmapping.
whitequark
2018-12-07
2
-4
/
+1
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*
equiv_opt: new command, for verifying optimization passes.
whitequark
2018-12-07
2
-23
/
+3
*
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opt_lut: leave intact LUTs with cascade feeding module outputs.
whitequark
2018-12-07
2
-0
/
+20
*
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Add missing .gitignore
Clifford Wolf
2018-12-06
1
-0
/
+8
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/
*
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
whitequark
2018-12-05
8
-0
/
+45
*
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
whitequark
2018-12-05
1
-1
/
+1
*
opt_lut: new pass, to combine LUTs for tighter packing.
whitequark
2018-12-05
5
-0
/
+43
*
Merge pull request #679 from udif/pr_syntax_error
Clifford Wolf
2018-10-25
13
-0
/
+64
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\
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*
Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...
Udi Finkelstein
2018-10-25
13
-0
/
+64
*
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Support for SystemVerilog interfaces as a port in the top level module + test...
Ruben Undheim
2018-10-20
7
-2
/
+420
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/
*
Basic test for checking correct synthesis of SystemVerilog interfaces
Ruben Undheim
2018-10-18
5
-9
/
+246
*
Support for 'modports' for System Verilog interfaces
Ruben Undheim
2018-10-12
1
-3
/
+17
*
Synthesis support for SystemVerilog interfaces
Ruben Undheim
2018-10-12
1
-0
/
+76
*
Merge pull request #513 from udif/pr_reg_wire_error
Clifford Wolf
2018-08-15
2
-0
/
+75
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\
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*
Modified errors into warnings
Udi Finkelstein
2018-06-05
1
-4
/
+38
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*
reg_wire_error test needs the -sv flag so it is run via a script so it had to...
Udi Finkelstein
2018-06-05
2
-0
/
+1
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*
This PR should be the base for discussion, do not merge it yet!
Udi Finkelstein
2018-03-11
1
-0
/
+40
*
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Fixed typo (sikp -> skip)
Udi Finkelstein
2018-06-05
1
-1
/
+1
*
|
autotest.sh: Change from /bin/bash to /usr/bin/env bash
Johnny Sorocil
2018-05-06
1
-1
/
+1
*
|
Fix tests/simple/specify.v
Clifford Wolf
2018-03-27
1
-2
/
+2
*
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First draft of Verilog parser support for specify blocks and parameters.
Udi Finkelstein
2018-03-27
1
-0
/
+31
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/
*
Major redesign of Verific SVA importer
Clifford Wolf
2018-02-27
1
-1
/
+1
*
Add support for SVA throughout via Verific
Clifford Wolf
2018-02-21
1
-1
/
+1
*
Add support for SVA sequence concatenation ranges via verific
Clifford Wolf
2018-02-18
2
-0
/
+20
*
Add support for SVA until statements via Verific
Clifford Wolf
2018-02-18
1
-0
/
+19
*
Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF
Clifford Wolf
2018-02-15
1
-0
/
+34
*
Remove PSL example from tests/sva/
Clifford Wolf
2017-10-20
2
-35
/
+1
*
Allow $size and $bits in verilog mode, actually check test case
Clifford Wolf
2017-09-29
2
-0
/
+2
*
$size() now works correctly for all cases!
Udi Finkelstein
2017-09-26
1
-5
/
+11
*
$size() seems to work now with or without the optional parameter.
Udi Finkelstein
2017-09-26
1
-8
/
+18
*
Added $bits() for memories as well.
Udi Finkelstein
2017-09-26
1
-6
/
+5
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