aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Expand)AuthorAgeFilesLines
* Merge branch 'master' into xaigEddie Hung2019-02-195-8/+92
|\
| * Merge https://github.com/YosysHQ/yosys into dff_initEddie Hung2019-02-175-8/+93
| |\
| | * Append (instead of over-writing) EXTRA_FLAGSJim Lawson2019-02-151-1/+1
| | * Update cells supported for verilog to FIRRTL conversion.Jim Lawson2019-02-154-7/+92
* | | Support and differentiate between ASCII and binary AIG testingEddie Hung2019-02-082-2/+6
* | | Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
* | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
|\| |
| * | Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
| * | Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
| * | Extend testcaseEddie Hung2019-02-061-2/+34
| * | Add testcaseEddie Hung2019-02-061-0/+10
| |/
* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
* | Add testsEddie Hung2019-02-0416-8/+109
|/
* Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
* Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-022-0/+44
|\
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-021-0/+18
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-021-0/+5
| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-021-8/+14
| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-022-0/+15
* | cmp2lut: new techmap pass.whitequark2019-01-023-2/+33
|/
* opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-313-0/+23
* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-1/+1
* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-163-26/+3
|\
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-072-4/+1
| * equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-23/+3
* | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-072-0/+20
* | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
|/
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-058-0/+45
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-1/+1
* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-055-0/+43
* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2513-0/+64
|\
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...Udi Finkelstein2018-10-2513-0/+64
* | Support for SystemVerilog interfaces as a port in the top level module + test...Ruben Undheim2018-10-207-2/+420
|/
* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-185-9/+246
* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-152-0/+75
|\
| * Modified errors into warningsUdi Finkelstein2018-06-051-4/+38
| * reg_wire_error test needs the -sv flag so it is run via a script so it had to...Udi Finkelstein2018-06-052-0/+1
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-0/+40
* | Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
* | autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
* | Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
|/
* Major redesign of Verific SVA importerClifford Wolf2018-02-271-1/+1
* Add support for SVA throughout via VerificClifford Wolf2018-02-211-1/+1
* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-182-0/+20
* Add support for SVA until statements via VerificClifford Wolf2018-02-181-0/+19
* Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-151-0/+34
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 23:04:36 +0000