| Commit message (Collapse) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| * | | | | | Add broken testcases | Eddie Hung | 2019-02-25 | 1 | -0/+46 | |
| | | | | | | ||||||
| * | | | | | Revert "tests/simple to also do LUT synth" | Eddie Hung | 2019-02-21 | 1 | -1/+0 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce. | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| |\| | | | | ||||||
| | * | | | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b. | |||||
| * | | | | | tests/simple to also do LUT synth | Eddie Hung | 2019-02-21 | 1 | -0/+1 | |
| | | | | | | ||||||
| * | | | | | Working simple_abc9 tests | Eddie Hung | 2019-02-21 | 1 | -2/+2 | |
| | | | | | | ||||||
| * | | | | | Add abc9.v testcase to simple_abc9 | Eddie Hung | 2019-02-21 | 1 | -4/+46 | |
| | | | | | | ||||||
| * | | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-21 | 1 | -21/+0 | |
| |\| | | | | ||||||
| | * | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
| | | | | | | ||||||
| * | | | | | simple_abc9 tests to now preserve memories | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
| | | | | | | ||||||
| * | | | | | Move tests/techmap/abc9 to simple_abc9 | Eddie Hung | 2019-02-20 | 4 | -23/+0 | |
| | | | | | | ||||||
| * | | | | | Add tests/simple_abc9 | Eddie Hung | 2019-02-20 | 1 | -0/+23 | |
| | | | | | | ||||||
| * | | | | | Add a quick abc9 test | Eddie Hung | 2019-02-19 | 4 | -0/+29 | |
| | | | | | | ||||||
| * | | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 5 | -8/+92 | |
| |\| | | | | |_|/ / |/| | | | ||||||
| | * | | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 5 | -8/+93 | |
| | |\ \ \ | | | |/ | | |/| | ||||||
| | | * | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 | |
| | | | | | ||||||
| | | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 4 | -7/+92 | |
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | |||||
| * | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 | |
| | | | | ||||||
| * | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 | |
| | | | | ||||||
| * | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 3 | -2/+67 | |
| |\| | | ||||||
| | * | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 | |
| | | | | ||||||
| | * | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 | |
| | | | | ||||||
| | * | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 | |
| | | | | ||||||
| | * | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 | |
| | |/ | ||||||
| * | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 | |
| | | | ||||||
| * | | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 | |
| | | | ||||||
| * | | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 | |
| |/ | ||||||
| * | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Merge pull request #770 from whitequark/opt_expr_cmp | Clifford Wolf | 2019-01-02 | 2 | -0/+44 | |
| |\ | | | | | opt_expr: refactor and improve simplification of comparisons | |||||
| | * | opt_expr: improve simplification of comparisons with large constants. | whitequark | 2019-01-02 | 1 | -0/+18 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs. | |||||
| | * | opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI. | whitequark | 2019-01-02 | 1 | -0/+5 | |
| | | | ||||||
| | * | opt_expr: refactor simplification of signed X>=0 and X<0. NFCI. | whitequark | 2019-01-02 | 1 | -8/+14 | |
| | | | ||||||
| | * | opt_expr: simplify any unsigned comparisons with all-0 and all-1. | whitequark | 2019-01-02 | 2 | -0/+15 | |
| | | | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input. | |||||
| * | | cmp2lut: new techmap pass. | whitequark | 2019-01-02 | 3 | -2/+33 | |
| |/ | ||||||
| * | opt_lut: eliminate LUTs evaluating to constants or inputs. | whitequark | 2018-12-31 | 3 | -0/+23 | |
| | | ||||||
| * | Squelch a little more trailing whitespace | Larry Doolittle | 2018-12-29 | 1 | -1/+1 | |
| | | ||||||
| * | Merge pull request #724 from whitequark/equiv_opt | Clifford Wolf | 2018-12-16 | 3 | -26/+3 | |
| |\ | | | | | equiv_opt: new command, for verifying optimization passes | |||||
| | * | equiv_opt: pass -D EQUIV when techmapping. | whitequark | 2018-12-07 | 2 | -4/+1 | |
| | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models. | |||||
| | * | equiv_opt: new command, for verifying optimization passes. | whitequark | 2018-12-07 | 2 | -23/+3 | |
| | | | ||||||
| * | | opt_lut: leave intact LUTs with cascade feeding module outputs. | whitequark | 2018-12-07 | 2 | -0/+20 | |
| | | | ||||||
| * | | Add missing .gitignore | Clifford Wolf | 2018-12-06 | 1 | -0/+8 | |
| |/ | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 8 | -0/+45 | |
| | | ||||||
| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -1/+1 | |
| | | ||||||
| * | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 5 | -0/+43 | |
| | | ||||||
| * | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 13 | -0/+64 | |
| |\ | | | | | More meaningful SystemVerilog/Verilog parser error messages | |||||
| | * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 13 | -0/+64 | |
| | | | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | |||||
| * | | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 7 | -2/+420 | |
| |/ | | | | test case | |||||
| * | Basic test for checking correct synthesis of SystemVerilog interfaces | Ruben Undheim | 2018-10-18 | 5 | -9/+246 | |
| | | ||||||
| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+17 | |
| | | ||||||
| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+76 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |