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Age
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*
Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v
Clifford Wolf
2013-05-24
1
-1
/
+3
*
Removed test cases that have been moved to yosys-test.
Clifford Wolf
2013-05-17
83
-18963
/
+0
*
Improved vcdcd.pl (added -d option)
Clifford Wolf
2013-05-14
1
-8
/
+82
*
Some improvements in vcdcd.pl
Clifford Wolf
2013-05-14
1
-4
/
+16
*
Fixed a bug in AST frontend for cases with non-blocking assigned variables as...
Clifford Wolf
2013-04-13
1
-0
/
+19
*
Now only use value from "initial" when no matching "always" block is found
Clifford Wolf
2013-03-31
2
-14
/
+1
*
Added test cases from 2012 paper on comparison of foss verilog synthesis tools
Clifford Wolf
2013-03-31
6
-0
/
+111
*
Added k68 (m68k compatible cpu) test case from verilator
Clifford Wolf
2013-03-31
3
-0
/
+61
*
Renamed hansimem.v test case to mem_arst.v
Clifford Wolf
2013-03-24
1
-1
/
+0
*
Added hansimem testcase (memory with async reset)
Clifford Wolf
2013-03-24
1
-0
/
+44
*
Set execute bit on tests/openmsp430/run-synth.sh for real
Clifford Wolf
2013-03-17
1
-0
/
+0
*
set executable flags to run-synth.sh, added .gitignore
Johann Glaser
2013-03-17
1
-0
/
+3
*
added ckeck for Icarus Verilog, otherwise the tests are silently stopped
Johann Glaser
2013-03-17
1
-0
/
+7
*
added more .gitignore files (make test)
Clifford Wolf
2013-01-05
4
-0
/
+7
*
initial import
Clifford Wolf
2013-01-05
367
-0
/
+28611