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* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-2/+2
* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
* proc_rom: Add special handling of const-0 address bits.Marcelina Kościelnicka2022-05-181-0/+146
* Merge pull request #3314 from jix/sva_value_change_logic_wideJannis Harder2022-05-162-2/+43
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| * verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-112-2/+43
* | Add proc_rom pass.Marcelina Kościelnicka2022-05-131-0/+43
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* Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-097-1/+96
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| * verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-097-1/+96
* | Merge pull request #3297 from jix/sva_nested_clk_elseJannis Harder2022-05-091-0/+11
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| * verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-031-0/+11
* | Fix running sva testsMiodrag Milanovic2022-05-091-4/+3
* | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-072-15/+2
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-052-0/+30
* opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-011-0/+50
* Fix valgrind tests when using verificMiodrag Milanovic2022-03-304-8/+8
* Proper example codeMiodrag Milanovic2022-03-142-1/+3
* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
* Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-042-0/+15
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| * fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-182-0/+15
* | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
* | Added test casesMiodrag Milanovic2022-02-1638-0/+896
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+25
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-144-5/+51
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-112-0/+108
* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-0/+84
* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-077-0/+953
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| * bug fix and cleanupsMiodrag Milanovic2022-02-041-2/+2
| * Add test cases for co-simulationMiodrag Milanovic2022-02-027-0/+953
* | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-302-0/+208
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-192-1/+14
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| * anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
* | sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
* | sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
* | logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
* | fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
* | fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
* | sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
* | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-0/+34
* | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
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* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
* sta: very crude static timing analysis passLofty2021-11-251-0/+81
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
* synth_gatemate: Initial implementationPatrick Urban2021-11-1314-0/+337
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