| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 8 | -0/+45 | |
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| * | opt_lut: add -dlogic, to avoid disturbing logic such as carry chains. | whitequark | 2018-12-05 | 1 | -1/+1 | |
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| * | opt_lut: new pass, to combine LUTs for tighter packing. | whitequark | 2018-12-05 | 5 | -0/+43 | |
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| * | Merge pull request #679 from udif/pr_syntax_error | Clifford Wolf | 2018-10-25 | 13 | -0/+64 | |
| |\ | | | | | More meaningful SystemVerilog/Verilog parser error messages | |||||
| | * | Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵ | Udi Finkelstein | 2018-10-25 | 13 | -0/+64 | |
| | | | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages. | |||||
| * | | Support for SystemVerilog interfaces as a port in the top level module + ↵ | Ruben Undheim | 2018-10-20 | 7 | -2/+420 | |
| |/ | | | | test case | |||||
| * | Basic test for checking correct synthesis of SystemVerilog interfaces | Ruben Undheim | 2018-10-18 | 5 | -9/+246 | |
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| * | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -3/+17 | |
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| * | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+76 | |
| | | | | | This time doing the changes mostly in AST before RTLIL generation | |||||
| * | Merge pull request #513 from udif/pr_reg_wire_error | Clifford Wolf | 2018-08-15 | 2 | -0/+75 | |
| |\ | | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test) | |||||
| | * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -4/+38 | |
| | | | | | | | | | No longer false warnings for memories and assertions | |||||
| | * | reg_wire_error test needs the -sv flag so it is run via a script so it had ↵ | Udi Finkelstein | 2018-06-05 | 2 | -0/+1 | |
| | | | | | | | | | to be moved out of the tests/simple dir that only runs Verilog files | |||||
| | * | This PR should be the base for discussion, do not merge it yet! | Udi Finkelstein | 2018-03-11 | 1 | -0/+40 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines) | |||||
| * | | Fixed typo (sikp -> skip) | Udi Finkelstein | 2018-06-05 | 1 | -1/+1 | |
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| * | | autotest.sh: Change from /bin/bash to /usr/bin/env bash | Johnny Sorocil | 2018-05-06 | 1 | -1/+1 | |
| | | | | | | | | | | | This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris). | |||||
| * | | Fix tests/simple/specify.v | Clifford Wolf | 2018-03-27 | 1 | -2/+2 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | First draft of Verilog parser support for specify blocks and parameters. | Udi Finkelstein | 2018-03-27 | 1 | -0/+31 | |
| |/ | | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST | |||||
| * | Major redesign of Verific SVA importer | Clifford Wolf | 2018-02-27 | 1 | -1/+1 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for SVA throughout via Verific | Clifford Wolf | 2018-02-21 | 1 | -1/+1 | |
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| * | Add support for SVA sequence concatenation ranges via verific | Clifford Wolf | 2018-02-18 | 2 | -0/+20 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Add support for SVA until statements via Verific | Clifford Wolf | 2018-02-18 | 1 | -0/+19 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF | Clifford Wolf | 2018-02-15 | 1 | -0/+34 | |
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| * | Remove PSL example from tests/sva/ | Clifford Wolf | 2017-10-20 | 2 | -35/+1 | |
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| * | Allow $size and $bits in verilog mode, actually check test case | Clifford Wolf | 2017-09-29 | 2 | -0/+2 | |
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| * | $size() now works correctly for all cases! | Udi Finkelstein | 2017-09-26 | 1 | -5/+11 | |
| | | | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly. | |||||
| * | $size() seems to work now with or without the optional parameter. | Udi Finkelstein | 2017-09-26 | 1 | -8/+18 | |
| | | | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated. | |||||
| * | Added $bits() for memories as well. | Udi Finkelstein | 2017-09-26 | 1 | -6/+5 | |
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| * | $size() now works with memories as well! | Udi Finkelstein | 2017-09-26 | 1 | -2/+4 | |
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| * | Add $size() function. At the moment it works only on expressions, not on ↵ | Udi Finkelstein | 2017-09-26 | 1 | -0/+15 | |
| | | | | | memories. | |||||
| * | Add simple VHDL+PSL example | Clifford Wolf | 2017-07-28 | 4 | -17/+64 | |
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| * | Improve Verific SVA importer | Clifford Wolf | 2017-07-27 | 1 | -7/+8 | |
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| * | Add counter.sv SVA test | Clifford Wolf | 2017-07-27 | 1 | -0/+29 | |
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| * | Improve SVA tests, add Makefile and scripts | Clifford Wolf | 2017-07-27 | 11 | -9/+110 | |
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| * | Add more SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 5 | -1/+74 | |
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| * | Add some simple SVA test cases for future Verific work | Clifford Wolf | 2017-07-22 | 4 | -0/+45 | |
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| * | Squelch trailing whitespace | Larry Doolittle | 2017-04-12 | 1 | -1/+1 | |
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| * | Fixed typo in tests/simple/arraycells.v | Clifford Wolf | 2017-01-04 | 1 | -1/+1 | |
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| * | Build hotfix in tests/unit/Makefile | Clifford Wolf | 2016-12-11 | 1 | -1/+1 | |
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| * | Improved unit test structure | rodrigosiqueira | 2016-12-10 | 1 | -11/+18 | |
| | | | | | | | | | | Signed-off-by: rodrigosiqueira <rodrigosiqueiramelo@gmail.com> Signed-off-by: chaws <18oliveira.charles@gmail.com> * Merged run-all-unitest inside unit-test target * Fixed Makefile dependencies * Updated documentation about unit test | |||||
| * | Added required structure to implement unit tests | rodrigosiqueira | 2016-12-04 | 3 | -0/+56 | |
| | | | | | | | | | | | Added modifications inside the main Makefile to refers the unit test Makefile. Added separated Makefile only for compiling unit tests. Added simple example of unit test. Signed-off-by: Charles Oliveira <18oliveira.charles@gmail.com> Signed-off-by: Pablo Alejandro <pabloabur@usp.br> Signed-off-by: Rodrigo Siqueira <siqueira@ime.usp.br> | |||||
| * | Added support for hierarchical defparams | Clifford Wolf | 2016-11-15 | 1 | -0/+23 | |
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| * | Added support for (single-clock) transparent memories to bram tests | Clifford Wolf | 2016-11-01 | 2 | -10/+23 | |
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| * | Fixed "make test" for git head of iverilog | Clifford Wolf | 2016-10-11 | 1 | -1/+1 | |
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| * | Merge branch 'master' of https://github.com/brouhaha/yosys | Clifford Wolf | 2016-09-23 | 13 | -16/+161 | |
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| | * | Add optional SEED=n command line option to Makefile, and -S n command line ↵ | Eric Smith | 2016-09-22 | 13 | -16/+161 | |
| | | | | | | | | | option to test scripts, for deterministic regression tests. | |||||
| * | | Added autotest.sh -I | Clifford Wolf | 2016-09-20 | 1 | -16/+19 | |
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| * | Fix for modules with big interfaces. | Kaj Tuomi | 2016-09-13 | 1 | -2/+2 | |
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| * | Fixed bug with memories that do not have a down-to-zero data width | Clifford Wolf | 2016-08-22 | 1 | -0/+30 | |
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| * | Added another mem2reg test case | Clifford Wolf | 2016-08-21 | 1 | -0/+11 | |
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| * | Another bugfix in mem2reg code | Clifford Wolf | 2016-08-21 | 1 | -0/+22 | |
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index : iCE40/yosys | |
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