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* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-2515-30/+30
* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-212-2/+3
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-1/+1
* Various improvements in test/vloghtbClifford Wolf2014-07-214-30/+52
* Wider range of cell types supported in "share" passClifford Wolf2014-07-212-19/+52
* Added yet another resource sharing test caseClifford Wolf2014-07-202-0/+49
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-202-4/+3
* Improved tests/share/generate.pyClifford Wolf2014-07-201-2/+12
* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-201-0/+2
* Added "miter -equiv -flatten"Clifford Wolf2014-07-201-2/+1
* Added tests/vloghtb/test_share.shClifford Wolf2014-07-205-1/+57
* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-203-0/+58
* Added tests/vloghtbClifford Wolf2014-07-202-0/+18
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-191-0/+25
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-191-0/+24
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-181-0/+24
* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-181-2/+2
* added tests/memoriesClifford Wolf2014-07-184-0/+132
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-171-1/+1
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-1/+40
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+21
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-0/+20
* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-165-5/+15
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-052-0/+19
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-021-0/+7
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-3/+6
* Little steps in realmath test benchClifford Wolf2014-06-212-2/+8
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+12
* Improved handling of relational op of real valuesClifford Wolf2014-06-171-4/+8
* Little steps in realmath test benchClifford Wolf2014-06-162-0/+3
* Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...Clifford Wolf2014-06-151-55/+0
* Added tests/realmath to "make test"Clifford Wolf2014-06-154-4/+5
* Improved realmath test benchClifford Wolf2014-06-152-5/+13
* improved realmath test benchClifford Wolf2014-06-141-1/+4
* progress in realmath test benchClifford Wolf2014-06-142-4/+45
* added first draft of real math testcase generatorClifford Wolf2014-06-141-0/+52
* Added support for math functionsClifford Wolf2014-06-141-0/+57
* Added realexpr.v test caseClifford Wolf2014-06-141-0/+13
* Added read_verilog -sv options, added support for bit, logic,Clifford Wolf2014-06-122-2/+2
* added tests for new verilog featuresClifford Wolf2014-06-072-6/+37
* Added tests/simple/repwhile.vClifford Wolf2014-06-061-0/+20
* Progress in Verific bindingsClifford Wolf2014-03-173-2/+13
* Progress in Verific bindingsClifford Wolf2014-03-141-5/+9
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-217-0/+214
* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-192-0/+170
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
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