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author | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:33:55 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2014-07-19 15:33:55 +0200 |
commit | 297a0962ea399fcfa80656af2bc887c5725f5b82 (patch) | |
tree | 5b37460137ceee98e29bc7e197ee2ed8d73ceeb6 /tests | |
parent | 35edac0b31ff826c60d864febefc294263613716 (diff) | |
download | yosys-297a0962ea399fcfa80656af2bc887c5725f5b82.tar.gz yosys-297a0962ea399fcfa80656af2bc887c5725f5b82.tar.bz2 yosys-297a0962ea399fcfa80656af2bc887c5725f5b82.zip |
Added SAT-based write-port sharing to memory_share
Diffstat (limited to 'tests')
-rw-r--r-- | tests/memories/shared_ports.v | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/tests/memories/shared_ports.v b/tests/memories/shared_ports.v new file mode 100644 index 000000000..94bad53e2 --- /dev/null +++ b/tests/memories/shared_ports.v @@ -0,0 +1,25 @@ +// expect-wr-ports 1 +// expect-rd-ports 1 + +module test( + input clk, + input wr_en1, wr_en2, wr_en3, + input [3:0] wr_addr1, wr_addr2, wr_addr3, + input [15:0] wr_data, + input [3:0] rd_addr, + output reg [31:0] rd_data +); + +reg [31:0] mem [0:15]; + +always @(posedge clk) begin + if (wr_en1) + mem[wr_addr1][15:0] <= wr_data; + else if (wr_en2) + mem[wr_addr2][23:8] <= wr_data; + else if (wr_en3) + mem[wr_addr3][31:16] <= wr_data; + rd_data <= mem[rd_addr]; +end + +endmodule |