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* Some improvements in FSM mapping and recodingClifford Wolf2014-08-141-1/+2
* Added test_verific mode to tests/fsm/generate.pyClifford Wolf2014-08-121-7/+17
* Added multi-dim memory test (requires iverilog git head)Clifford Wolf2014-08-121-0/+11
* Fixed FSM mapping for multiple reset-like signalsClifford Wolf2014-08-101-7/+22
* Some improvements in fsm_opt and fsm_map for FSM with unreachable statesClifford Wolf2014-08-091-1/+2
* Improved FSM testsClifford Wolf2014-08-083-2/+4
* Added FSM test benchClifford Wolf2014-08-082-0/+113
* Improved scope resolution of local regs in Verilog+AST frontendClifford Wolf2014-08-051-0/+63
* Fixed AST handling of variables declared inside a functions main blockClifford Wolf2014-08-051-0/+13
* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-033-2/+3
* Consolidated hana test benches into fewer filesClifford Wolf2014-08-01175-1332/+1622
* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-011-2/+5
* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-306-12/+29
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-291-1/+1
* Added support for "upto" wires to Verilog front- and back-endClifford Wolf2014-07-281-0/+57
* Improvements in tests/vloghtbClifford Wolf2014-07-282-11/+17
* Added techmap -externClifford Wolf2014-07-272-1/+28
* Added tests/various/.gitignoreClifford Wolf2014-07-261-0/+1
* Added tests/various/submod_extract.ysClifford Wolf2014-07-262-0/+27
* Use "wget -N" in tests/vloghtb/run-test.shClifford Wolf2014-07-261-2/+2
* Renamed some of the test cases in tests/simple to avoid name collisionsClifford Wolf2014-07-2515-30/+30
* Use "opt -fine" in test/vloght/test_mapopt.shClifford Wolf2014-07-212-2/+3
* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-1/+1
* Various improvements in test/vloghtbClifford Wolf2014-07-214-30/+52
* Wider range of cell types supported in "share" passClifford Wolf2014-07-212-19/+52
* Added yet another resource sharing test caseClifford Wolf2014-07-202-0/+49
* Supercell creation for $div/$mod worked all along, fixed test benchesClifford Wolf2014-07-202-4/+3
* Improved tests/share/generate.pyClifford Wolf2014-07-201-2/+12
* Small fix in tests/vloghtb/run-test.shClifford Wolf2014-07-201-0/+2
* Added "miter -equiv -flatten"Clifford Wolf2014-07-201-2/+1
* Added tests/vloghtb/test_share.shClifford Wolf2014-07-205-1/+57
* Added tests/share for testing "share" supercell creationClifford Wolf2014-07-203-0/+58
* Added tests/vloghtbClifford Wolf2014-07-202-0/+18
* Added SAT-based write-port sharing to memory_shareClifford Wolf2014-07-191-0/+25
* Fixed bug in memory_share feedback-to-en codeClifford Wolf2014-07-191-0/+24
* Added translation from read-feedback to en-signals in memory_shareClifford Wolf2014-07-181-0/+24
* Bugfix in tests/memories/run-test.shClifford Wolf2014-07-181-2/+2
* added tests/memoriesClifford Wolf2014-07-184-0/+132
* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-171-1/+1
* Implemented dynamic bit-/part-select for memory writesClifford Wolf2014-07-171-1/+40
* Added support for bit/part select to mem2reg rewriterClifford Wolf2014-07-171-0/+21
* Added support for constant bit- or part-select for memory writesClifford Wolf2014-07-171-0/+20
* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-165-5/+15
* now ignore init attributes on non-register wires in sat commandClifford Wolf2014-07-052-0/+19
* fixed parsing of constant with comment between size and valueClifford Wolf2014-07-021-0/+7
* Fixed handling of mixed real/int ternary expressionsClifford Wolf2014-06-251-3/+6
* Little steps in realmath test benchClifford Wolf2014-06-212-2/+8
* Added test case for AstNode::MEM2REG_FL_CMPLX_LHSClifford Wolf2014-06-171-0/+12
* Improved handling of relational op of real valuesClifford Wolf2014-06-171-4/+8
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