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* Add binary AIGs converted from AAGEddie Hung2019-02-0814-0/+51
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* Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaigEddie Hung2019-02-063-2/+67
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| * Add tests for simple cases using defparamEddie Hung2019-02-061-0/+21
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| * Add -B option to autotest.sh to append to backend_optsEddie Hung2019-02-061-2/+4
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| * Extend testcaseEddie Hung2019-02-061-2/+34
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| * Add testcaseEddie Hung2019-02-061-0/+10
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* | Revert most of autotest.sh; for non *.v use Yosys to translateEddie Hung2019-02-061-7/+9
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* | Rename ASCII testsEddie Hung2019-02-0615-0/+0
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* | Add testsEddie Hung2019-02-0416-8/+109
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* Remove asicworld tests for (unsupported) switch-level modellingClifford Wolf2019-01-274-69/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #770 from whitequark/opt_expr_cmpClifford Wolf2019-01-022-0/+44
|\ | | | | opt_expr: refactor and improve simplification of comparisons
| * opt_expr: improve simplification of comparisons with large constants.whitequark2019-01-021-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | The idea behind this simplification is that a N-bit signal X being compared with an M-bit constant where M>N and the constant has Nth or higher bit set, it either always succeeds or always fails. However, the existing implementation only worked with one-hot signals for some reason. It also printed incorrect messages. This commit adjusts the simplification to have as much power as possible, and fixes other bugs.
| * opt_expr: refactor simplification of unsigned X<onehot and X>=onehot. NFCI.whitequark2019-01-021-0/+5
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| * opt_expr: refactor simplification of signed X>=0 and X<0. NFCI.whitequark2019-01-021-8/+14
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| * opt_expr: simplify any unsigned comparisons with all-0 and all-1.whitequark2019-01-022-0/+15
| | | | | | | | | | | | Before this commit, only unsigned comparisons with all-0 would be simplified. This commit also makes the code handling such comparisons to be more rigorous and not abort on unexpected input.
* | cmp2lut: new techmap pass.whitequark2019-01-023-2/+33
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* opt_lut: eliminate LUTs evaluating to constants or inputs.whitequark2018-12-313-0/+23
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* Squelch a little more trailing whitespaceLarry Doolittle2018-12-291-1/+1
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* Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-163-26/+3
|\ | | | | equiv_opt: new command, for verifying optimization passes
| * equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-072-4/+1
| | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-23/+3
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* | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-072-0/+20
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* | Add missing .gitignoreClifford Wolf2018-12-061-0/+8
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.whitequark2018-12-058-0/+45
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* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-1/+1
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* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-055-0/+43
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* Merge pull request #679 from udif/pr_syntax_errorClifford Wolf2018-10-2513-0/+64
|\ | | | | More meaningful SystemVerilog/Verilog parser error messages
| * Rename the generic "Syntax error" message from the Verilog/SystemVerilog ↵Udi Finkelstein2018-10-2513-0/+64
| | | | | | | | | | | | | | parser into unique, meaningful info on the error. Also add 13 compilation examples that triggers each of these messages.
* | Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-207-2/+420
|/ | | | test case
* Basic test for checking correct synthesis of SystemVerilog interfacesRuben Undheim2018-10-185-9/+246
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* Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-3/+17
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* Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+76
| | | | This time doing the changes mostly in AST before RTLIL generation
* Merge pull request #513 from udif/pr_reg_wire_errorClifford Wolf2018-08-152-0/+75
|\ | | | | Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
| * Modified errors into warningsUdi Finkelstein2018-06-051-4/+38
| | | | | | | | No longer false warnings for memories and assertions
| * reg_wire_error test needs the -sv flag so it is run via a script so it had ↵Udi Finkelstein2018-06-052-0/+1
| | | | | | | | to be moved out of the tests/simple dir that only runs Verilog files
| * This PR should be the base for discussion, do not merge it yet!Udi Finkelstein2018-03-111-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements. What it DOES'T do: Detect registers connected to output ports of instances. Where it FAILS: memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals. You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
* | Fixed typo (sikp -> skip)Udi Finkelstein2018-06-051-1/+1
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* | autotest.sh: Change from /bin/bash to /usr/bin/env bashJohnny Sorocil2018-05-061-1/+1
| | | | | | | | | | This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris).
* | Fix tests/simple/specify.vClifford Wolf2018-03-271-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | First draft of Verilog parser support for specify blocks and parameters.Udi Finkelstein2018-03-271-0/+31
|/ | | | | The only functionality of this code at the moment is to accept correct specify syntax and ignore it. No part of the specify block is added to the AST
* Major redesign of Verific SVA importerClifford Wolf2018-02-271-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA throughout via VerificClifford Wolf2018-02-211-1/+1
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* Add support for SVA sequence concatenation ranges via verificClifford Wolf2018-02-182-0/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add support for SVA until statements via VerificClifford Wolf2018-02-181-0/+19
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFFClifford Wolf2018-02-151-0/+34
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* Remove PSL example from tests/sva/Clifford Wolf2017-10-202-35/+1
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* Allow $size and $bits in verilog mode, actually check test caseClifford Wolf2017-09-292-0/+2
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* $size() now works correctly for all cases!Udi Finkelstein2017-09-261-5/+11
| | | | It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
* $size() seems to work now with or without the optional parameter.Udi Finkelstein2017-09-261-8/+18
| | | | Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
* Added $bits() for memories as well.Udi Finkelstein2017-09-261-6/+5
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