Commit message (Collapse) | Author | Age | Files | Lines | |
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* | smtbmc: Add native json based witness format + smt2 backend support | Jannis Harder | 2022-08-16 | 1 | -0/+8 |
| | | | | | | | | | | | | | | | | | | | | This adds a native json based witness trace format. By having a common format that includes everything we support, and providing a conversion utility (yosys-witness) we no longer need to implement every format for every tool that deals with witness traces, avoiding a quadratic opportunity to introduce subtle bugs. Included: * smt2: New yosys-smt2-witness info lines containing full hierarchical paths without lossy escaping. * yosys-smtbmc --dump-yw trace.yw: Dump results in the new format. * yosys-smtbmc --yw trace.yw: Read new format as constraints. * yosys-witness: New tool to convert witness formats. Currently this can only display traces in a human-readable-only format and do a passthrough read/write of the new format. * ywio.py: Small python lib for reading and writing the new format. Used by yosys-smtbmc and yosys-witness to avoid duplication. | ||||
* | Merge pull request #3277 from YosysHQ/lofty/rename-scramble_name | N. Engelhardt | 2022-08-11 | 1 | -0/+31 |
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| * | rename: add -scramble-name option to randomly rename selections | Lofty | 2022-08-08 | 1 | -0/+31 |
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* | | support file locations containing spaces | Miodrag Milanovic | 2022-08-08 | 3 | -9/+10 |
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* | gatemate: Add test for LUT tree mapping | gatecat | 2022-06-27 | 3 | -0/+813 |
| | | | | Signed-off-by: gatecat <gatecat@ds0.me> | ||||
* | Adding expected error message. | Archie | 2022-06-22 | 1 | -0/+1 |
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* | Adding testcase for issue 3374 | Archie | 2022-06-22 | 1 | -0/+3 |
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* | smt2: emit smtlib2_comb_expr outputs after all inputs | Jannis Harder | 2022-06-07 | 2 | -6/+6 |
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* | don't use sed -i because it won't work on macos | Jacob Lifshay | 2022-06-03 | 2 | -2/+3 |
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* | smtlib2_module: try to fix test on macos | Jacob Lifshay | 2022-06-02 | 1 | -1/+1 |
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* | smt2: Add smtlib2_comb_expr attribute to allow user-selected smtlib2 expressions | Jacob Lifshay | 2022-06-02 | 4 | -0/+127 |
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* | verilog: fix width/sign detection for functions | Zachary Snow | 2022-05-30 | 2 | -0/+46 |
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* | verilog: fix size and signedness of array querying functions | Jannis Harder | 2022-05-30 | 1 | -0/+52 |
| | | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions. | ||||
* | verilog: fix $past's signedness | Jannis Harder | 2022-05-25 | 1 | -0/+35 |
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* | verilog: fix signedness when removing unreachable cases | Jannis Harder | 2022-05-24 | 1 | -0/+33 |
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* | Add memory_bmux2rom pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -0/+27 |
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* | Add memory_libmap tests. | Marcelina Kościelnicka | 2022-05-18 | 21 | -0/+1499 |
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* | efinix: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -12/+1 |
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* | ice40: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -56/+0 |
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* | xilinx: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 3 | -46/+15 |
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* | nexus: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -2/+2 |
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* | ecp5: Use `memory_libmap` pass. | Marcelina Kościelnicka | 2022-05-18 | 1 | -135/+18 |
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* | proc_rom: Add special handling of const-0 address bits. | Marcelina Kościelnicka | 2022-05-18 | 1 | -0/+146 |
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* | Merge pull request #3314 from jix/sva_value_change_logic_wide | Jannis Harder | 2022-05-16 | 2 | -2/+43 |
|\ | | | | | verific: Use new value change logic also for $stable of wide signals. | ||||
| * | verific: Use new value change logic also for $stable of wide signals. | Jannis Harder | 2022-05-11 | 2 | -2/+43 |
| | | | | | | | | I missed this in the previous PR. | ||||
* | | Add proc_rom pass. | Marcelina Kościelnicka | 2022-05-13 | 1 | -0/+43 |
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* | Merge pull request #3305 from jix/sva_value_change_logic | Jannis Harder | 2022-05-09 | 7 | -1/+96 |
|\ | | | | | verific: Improve logic generated for SVA value change expressions | ||||
| * | verific: Improve logic generated for SVA value change expressions | Jannis Harder | 2022-05-09 | 7 | -1/+96 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation | ||||
* | | Merge pull request #3297 from jix/sva_nested_clk_else | Jannis Harder | 2022-05-09 | 1 | -0/+11 |
|\ \ | |/ |/| | verific: Fix conditions of SVAs with explicit clocks within procedures | ||||
| * | verific: Fix conditions of SVAs with explicit clocks within procedures | Jannis Harder | 2022-05-03 | 1 | -0/+11 |
| | | | | | | | | | | | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case. | ||||
* | | Fix running sva tests | Miodrag Milanovic | 2022-05-09 | 1 | -4/+3 |
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* | | opt_mem: Remove constant-value bit lanes. | Marcelina Kościelnicka | 2022-05-07 | 2 | -15/+2 |
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* | sv: fix always_comb auto nosync for nested and function blocks | Zachary Snow | 2022-04-05 | 2 | -0/+30 |
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* | opt_merge: Add `-keepdc` option required for formal verification | Jannis Harder | 2022-04-01 | 1 | -0/+50 |
| | | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now. | ||||
* | Fix valgrind tests when using verific | Miodrag Milanovic | 2022-03-30 | 4 | -8/+8 |
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* | Proper example code | Miodrag Milanovic | 2022-03-14 | 2 | -1/+3 |
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* | intel_alm: M10K write-enable is negative-true | Lofty | 2022-03-09 | 1 | -1/+2 |
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* | Merge pull request #3207 from nakengelhardt/json_escape_quotes | Miodrag Milanović | 2022-03-04 | 2 | -0/+15 |
|\ | | | | | fix handling of escaped chars in json backend and frontend (mostly) | ||||
| * | fix handling of escaped chars in json backend and frontend | N. Engelhardt | 2022-02-18 | 2 | -0/+15 |
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* | | test dlatchsr and adlatch | Miodrag Milanovic | 2022-02-16 | 4 | -4/+94 |
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* | | Added test cases | Miodrag Milanovic | 2022-02-16 | 38 | -0/+896 |
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* | verilog: support for time scale delay values | Zachary Snow | 2022-02-14 | 1 | -0/+25 |
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* | Fix access to whole sub-structs (#3086) | Kamil Rakoczy | 2022-02-14 | 4 | -5/+51 |
| | | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com> | ||||
* | verilog: fix dynamic dynamic range asgn elab | Zachary Snow | 2022-02-11 | 2 | -0/+108 |
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* | verilog: fix const func eval with upto variables | Zachary Snow | 2022-02-11 | 2 | -0/+84 |
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* | gowin: Fix LUT RAM inference, add more models. | Marcelina Kościelnicka | 2022-02-09 | 1 | -3/+2 |
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* | Merge pull request #3185 from YosysHQ/micko/co_sim | Miodrag Milanović | 2022-02-07 | 7 | -0/+953 |
|\ | | | | | Add co-simulation in sim pass | ||||
| * | bug fix and cleanups | Miodrag Milanovic | 2022-02-04 | 1 | -2/+2 |
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| * | Add test cases for co-simulation | Miodrag Milanovic | 2022-02-02 | 7 | -0/+953 |
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* | | opt_reduce: Add $bmux and $demux optimization patterns. | Marcelina Kościelnicka | 2022-01-30 | 2 | -0/+208 |
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