xilinx: Use `memory_libmap` pass.

3 files changed, 15 insertions, 46 deletions

diff --git a/tests/arch/xilinx/attributes_test.ys b/tests/arch/xilinx/attributes_test.ys
index 58552d8fb..74861850f 100644
--- a/tests/arch/xilinx/attributes_test.ys
+++ b/tests/arch/xilinx/attributes_test.ys
@@ -11,7 +11,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
 hierarchy -top distributed_ram
 synth_xilinx -top distributed_ram -noiopad
 cd distributed_ram # Constrain all select calls below inside the top module
-select -assert-count 8 t:RAM32X1D
+select -assert-count 1 t:RAM32M
  
 # Set ram_style distributed to blockram memory; will be implemented as distributed
 design -reset
@@ -19,7 +19,7 @@ read_verilog ../common/memory_attributes/attributes_test.v
 setattr -set ram_style "distributed" block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
-select -assert-count 32 t:RAM128X1D
+select -assert-count 16 t:RAM256X1S
  
 # Set synthesis, logic_block to blockram memory; will be implemented as distributed
 design -reset
@@ -28,7 +28,6 @@ setattr -set logic_block 1 block_ram/m:*
 synth_xilinx -top block_ram -noiopad
 cd block_ram # Constrain all select calls below inside the top module
 select -assert-count 0 t:RAMB18E1
-select -assert-count 32 t:RAM128X1D
  
 # Set ram_style block to a distributed memory; will be implemented as blockram
 design -reset
@@ -36,10 +35,3 @@ read_verilog ../common/memory_attributes/attributes_test.v
 synth_xilinx -top distributed_ram_manual -noiopad
 cd distributed_ram_manual # Constrain all select calls below inside the top module
 select -assert-count 1 t:RAMB18E1
- 
-# Set synthesis, ram_block block to a distributed memory; will be implemented as blockram
-design -reset
-read_verilog ../common/memory_attributes/attributes_test.v
-synth_xilinx -top distributed_ram_manual_syn -noiopad
-cd distributed_ram_manual_syn # Constrain all select calls below inside the top module
-select -assert-count 1 t:RAMB18E1
diff --git a/tests/arch/xilinx/blockram.ys b/tests/arch/xilinx/blockram.ys
index ed743cf44..c2b7aede7 100644
--- a/tests/arch/xilinx/blockram.ys
+++ b/tests/arch/xilinx/blockram.ys
@@ -2,7 +2,7 @@
 ###       currently. Checking instance counts instead.
 # Memory bits <= 18K; Data width <= 36; Address width <= 14: -> RAMB18E1
 read_verilog ../common/blockram.v
-chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 1 sync_ram_sdp
+chparam -set ADDRESS_WIDTH 12 -set DATA_WIDTH 1 sync_ram_sdp
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
@@ -35,7 +35,7 @@ chparam -set ADDRESS_WIDTH 8 -set DATA_WIDTH 2 sync_ram_sdp
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 0 t:RAMB18E1
-select -assert-count 4 t:RAM128X1D
+select -assert-count 4 t:RAM64M
 
 # More than 18K bits, data width <= 36 (TDP), and address width from 10 to 15b (non-cascaded) -> RAMB36E1
 design -reset
@@ -50,7 +50,7 @@ select -assert-count 1 t:RAMB36E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
 setattr -set ram_style "block" m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -58,23 +58,7 @@ select -assert-count 1 t:RAMB18E1
 
 design -reset
 read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
-setattr -set ram_block 1 m:memory
-synth_xilinx -top sync_ram_sdp -noiopad
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
-setattr -set ram_style "dont_infer_a_ram_pretty_please" m:memory
-synth_xilinx -top sync_ram_sdp -noiopad
-cd sync_ram_sdp
-select -assert-count 0 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 10 -chparam DATA_WIDTH 1 
+hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 12 -chparam DATA_WIDTH 1 
 setattr -set logic_block 1 m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
@@ -87,11 +71,3 @@ setattr -set ram_style "block" m:memory
 synth_xilinx -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:RAMB18E1
-
-design -reset
-read_verilog ../common/blockram.v
-hierarchy -top sync_ram_sdp -chparam ADDRESS_WIDTH 8 -chparam DATA_WIDTH 1
-setattr -set ram_block 1 m:memory
-synth_xilinx -top sync_ram_sdp -noiopad
-cd sync_ram_sdp
-select -assert-count 1 t:RAMB18E1
diff --git a/tests/arch/xilinx/lutram.ys b/tests/arch/xilinx/lutram.ys
index cc7354501..34caa8c6c 100644
--- a/tests/arch/xilinx/lutram.ys
+++ b/tests/arch/xilinx/lutram.ys
@@ -33,8 +33,8 @@ design -load postopt
 cd lutram_1w1r
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDRE
-select -assert-count 8 t:RAM32X1D
-select -assert-none t:BUFG t:FDRE t:RAM32X1D %% t:* %D
+select -assert-count 1 t:RAM32M
+select -assert-none t:BUFG t:FDRE t:RAM32M %% t:* %D
 
 
 design -reset
@@ -51,10 +51,11 @@ sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs mite
 
 design -load postopt
 cd lutram_1w1r
+dump
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDRE
-select -assert-count 8 t:RAM64X1D
-select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
+select -assert-count 8 t:RAM64X1S
+select -assert-none t:BUFG t:FDRE t:RAM64X1S %% t:* %D
 
 
 design -reset
@@ -133,8 +134,8 @@ design -load postopt
 cd lutram_1w1r
 select -assert-count 1 t:BUFG
 select -assert-count 6 t:FDRE
-select -assert-count 2 t:RAM64M
-select -assert-none t:BUFG t:FDRE t:RAM64M %% t:* %D
+select -assert-count 6 t:RAM64X1S
+select -assert-none t:BUFG t:FDRE t:RAM64X1S %% t:* %D
 
 
 design -reset
@@ -153,5 +154,5 @@ design -load postopt
 cd lutram_1w1r
 select -assert-count 1 t:BUFG
 select -assert-count 8 t:FDRE
-select -assert-count 8 t:RAM16X1D
-select -assert-none t:BUFG t:FDRE t:RAM16X1D %% t:* %D
+select -assert-count 8 t:RAM16X1S
+select -assert-none t:BUFG t:FDRE t:RAM16X1S %% t:* %D