iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #724 from whitequark/equiv_opt	Clifford Wolf	2018-12-16	3	-26/+3
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\| *	equiv_opt: pass -D EQUIV when techmapping.	whitequark	2018-12-07	2	-4/+1
\| *	equiv_opt: new command, for verifying optimization passes.	whitequark	2018-12-07	2	-23/+3
* \|	opt_lut: leave intact LUTs with cascade feeding module outputs.	whitequark	2018-12-07	2	-0/+20
* \|	Add missing .gitignore	Clifford Wolf	2018-12-06	1	-0/+8
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*	gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.	whitequark	2018-12-05	8	-0/+45
*	opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.	whitequark	2018-12-05	1	-1/+1
*	opt_lut: new pass, to combine LUTs for tighter packing.	whitequark	2018-12-05	5	-0/+43
*	Merge pull request #679 from udif/pr_syntax_error	Clifford Wolf	2018-10-25	13	-0/+64
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\| *	Rename the generic "Syntax error" message from the Verilog/SystemVerilog pars...	Udi Finkelstein	2018-10-25	13	-0/+64
* \|	Support for SystemVerilog interfaces as a port in the top level module + test...	Ruben Undheim	2018-10-20	7	-2/+420
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*	Basic test for checking correct synthesis of SystemVerilog interfaces	Ruben Undheim	2018-10-18	5	-9/+246
*	Support for 'modports' for System Verilog interfaces	Ruben Undheim	2018-10-12	1	-3/+17
*	Synthesis support for SystemVerilog interfaces	Ruben Undheim	2018-10-12	1	-0/+76
*	Merge pull request #513 from udif/pr_reg_wire_error	Clifford Wolf	2018-08-15	2	-0/+75
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\| *	Modified errors into warnings	Udi Finkelstein	2018-06-05	1	-4/+38
\| *	reg_wire_error test needs the -sv flag so it is run via a script so it had to...	Udi Finkelstein	2018-06-05	2	-0/+1
\| *	This PR should be the base for discussion, do not merge it yet!	Udi Finkelstein	2018-03-11	1	-0/+40
* \|	Fixed typo (sikp -> skip)	Udi Finkelstein	2018-06-05	1	-1/+1
* \|	autotest.sh: Change from /bin/bash to /usr/bin/env bash	Johnny Sorocil	2018-05-06	1	-1/+1
* \|	Fix tests/simple/specify.v	Clifford Wolf	2018-03-27	1	-2/+2
* \|	First draft of Verilog parser support for specify blocks and parameters.	Udi Finkelstein	2018-03-27	1	-0/+31
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*	Major redesign of Verific SVA importer	Clifford Wolf	2018-02-27	1	-1/+1
*	Add support for SVA throughout via Verific	Clifford Wolf	2018-02-21	1	-1/+1
*	Add support for SVA sequence concatenation ranges via verific	Clifford Wolf	2018-02-18	2	-0/+20
*	Add support for SVA until statements via Verific	Clifford Wolf	2018-02-18	1	-0/+19
*	Fix verific PRIM_SVA_AT handling in properties with PRIM_SVA_DISABLE_IFF	Clifford Wolf	2018-02-15	1	-0/+34
*	Remove PSL example from tests/sva/	Clifford Wolf	2017-10-20	2	-35/+1
*	Allow $size and $bits in verilog mode, actually check test case	Clifford Wolf	2017-09-29	2	-0/+2
*	$size() now works correctly for all cases!	Udi Finkelstein	2017-09-26	1	-5/+11
*	$size() seems to work now with or without the optional parameter.	Udi Finkelstein	2017-09-26	1	-8/+18
*	Added $bits() for memories as well.	Udi Finkelstein	2017-09-26	1	-6/+5
*	$size() now works with memories as well!	Udi Finkelstein	2017-09-26	1	-2/+4
*	Add $size() function. At the moment it works only on expressions, not on memo...	Udi Finkelstein	2017-09-26	1	-0/+15
*	Add simple VHDL+PSL example	Clifford Wolf	2017-07-28	4	-17/+64
*	Improve Verific SVA importer	Clifford Wolf	2017-07-27	1	-7/+8
*	Add counter.sv SVA test	Clifford Wolf	2017-07-27	1	-0/+29
*	Improve SVA tests, add Makefile and scripts	Clifford Wolf	2017-07-27	11	-9/+110
*	Add more SVA test cases for future Verific work	Clifford Wolf	2017-07-22	5	-1/+74
*	Add some simple SVA test cases for future Verific work	Clifford Wolf	2017-07-22	4	-0/+45
*	Squelch trailing whitespace	Larry Doolittle	2017-04-12	1	-1/+1
*	Fixed typo in tests/simple/arraycells.v	Clifford Wolf	2017-01-04	1	-1/+1
*	Build hotfix in tests/unit/Makefile	Clifford Wolf	2016-12-11	1	-1/+1
*	Improved unit test structure	rodrigosiqueira	2016-12-10	1	-11/+18
*	Added required structure to implement unit tests	rodrigosiqueira	2016-12-04	3	-0/+56
*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	1	-0/+23
*	Added support for (single-clock) transparent memories to bram tests	Clifford Wolf	2016-11-01	2	-10/+23
*	Fixed "make test" for git head of iverilog	Clifford Wolf	2016-10-11	1	-1/+1
*	Merge branch 'master' of https://github.com/brouhaha/yosys	Clifford Wolf	2016-09-23	13	-16/+161
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\| *	Add optional SEED=n command line option to Makefile, and -S n command line op...	Eric Smith	2016-09-22	13	-16/+161