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Age
Files
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*
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf
2014-07-29
1
-1
/
+1
*
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf
2014-07-28
1
-0
/
+57
*
Improvements in tests/vloghtb
Clifford Wolf
2014-07-28
2
-11
/
+17
*
Added techmap -extern
Clifford Wolf
2014-07-27
2
-1
/
+28
*
Added tests/various/.gitignore
Clifford Wolf
2014-07-26
1
-0
/
+1
*
Added tests/various/submod_extract.ys
Clifford Wolf
2014-07-26
2
-0
/
+27
*
Use "wget -N" in tests/vloghtb/run-test.sh
Clifford Wolf
2014-07-26
1
-2
/
+2
*
Renamed some of the test cases in tests/simple to avoid name collisions
Clifford Wolf
2014-07-25
15
-30
/
+30
*
Use "opt -fine" in test/vloght/test_mapopt.sh
Clifford Wolf
2014-07-21
2
-2
/
+3
*
Added "opt_const -fine" and "opt_reduce -fine"
Clifford Wolf
2014-07-21
1
-1
/
+1
*
Various improvements in test/vloghtb
Clifford Wolf
2014-07-21
4
-30
/
+52
*
Wider range of cell types supported in "share" pass
Clifford Wolf
2014-07-21
2
-19
/
+52
*
Added yet another resource sharing test case
Clifford Wolf
2014-07-20
2
-0
/
+49
*
Supercell creation for $div/$mod worked all along, fixed test benches
Clifford Wolf
2014-07-20
2
-4
/
+3
*
Improved tests/share/generate.py
Clifford Wolf
2014-07-20
1
-2
/
+12
*
Small fix in tests/vloghtb/run-test.sh
Clifford Wolf
2014-07-20
1
-0
/
+2
*
Added "miter -equiv -flatten"
Clifford Wolf
2014-07-20
1
-2
/
+1
*
Added tests/vloghtb/test_share.sh
Clifford Wolf
2014-07-20
5
-1
/
+57
*
Added tests/share for testing "share" supercell creation
Clifford Wolf
2014-07-20
3
-0
/
+58
*
Added tests/vloghtb
Clifford Wolf
2014-07-20
2
-0
/
+18
*
Added SAT-based write-port sharing to memory_share
Clifford Wolf
2014-07-19
1
-0
/
+25
*
Fixed bug in memory_share feedback-to-en code
Clifford Wolf
2014-07-19
1
-0
/
+24
*
Added translation from read-feedback to en-signals in memory_share
Clifford Wolf
2014-07-18
1
-0
/
+24
*
Bugfix in tests/memories/run-test.sh
Clifford Wolf
2014-07-18
1
-2
/
+2
*
added tests/memories
Clifford Wolf
2014-07-18
4
-0
/
+132
*
Also simulate unmapped memories in "make test"
Clifford Wolf
2014-07-17
1
-1
/
+1
*
Implemented dynamic bit-/part-select for memory writes
Clifford Wolf
2014-07-17
1
-1
/
+40
*
Added support for bit/part select to mem2reg rewriter
Clifford Wolf
2014-07-17
1
-0
/
+21
*
Added support for constant bit- or part-select for memory writes
Clifford Wolf
2014-07-17
1
-0
/
+20
*
Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface
Clifford Wolf
2014-07-16
1
-2
/
+13
*
Added note to "make test": use git checkout of iverilog
Clifford Wolf
2014-07-16
5
-5
/
+15
*
now ignore init attributes on non-register wires in sat command
Clifford Wolf
2014-07-05
2
-0
/
+19
*
fixed parsing of constant with comment between size and value
Clifford Wolf
2014-07-02
1
-0
/
+7
*
Fixed handling of mixed real/int ternary expressions
Clifford Wolf
2014-06-25
1
-3
/
+6
*
Little steps in realmath test bench
Clifford Wolf
2014-06-21
2
-2
/
+8
*
Added test case for AstNode::MEM2REG_FL_CMPLX_LHS
Clifford Wolf
2014-06-17
1
-0
/
+12
*
Improved handling of relational op of real values
Clifford Wolf
2014-06-17
1
-4
/
+8
*
Little steps in realmath test bench
Clifford Wolf
2014-06-16
2
-0
/
+3
*
Removed long running tests from tests/simple/realexpr.v (replaced by tests/re...
Clifford Wolf
2014-06-15
1
-55
/
+0
*
Added tests/realmath to "make test"
Clifford Wolf
2014-06-15
4
-4
/
+5
*
Improved realmath test bench
Clifford Wolf
2014-06-15
2
-5
/
+13
*
improved realmath test bench
Clifford Wolf
2014-06-14
1
-1
/
+4
*
progress in realmath test bench
Clifford Wolf
2014-06-14
2
-4
/
+45
*
added first draft of real math testcase generator
Clifford Wolf
2014-06-14
1
-0
/
+52
*
Added support for math functions
Clifford Wolf
2014-06-14
1
-0
/
+57
*
Added realexpr.v test case
Clifford Wolf
2014-06-14
1
-0
/
+13
*
Added read_verilog -sv options, added support for bit, logic,
Clifford Wolf
2014-06-12
2
-2
/
+2
*
added tests for new verilog features
Clifford Wolf
2014-06-07
2
-6
/
+37
*
Added tests/simple/repwhile.v
Clifford Wolf
2014-06-06
1
-0
/
+20
*
Progress in Verific bindings
Clifford Wolf
2014-03-17
3
-2
/
+13
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