iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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*	Fixed another bug found using vloghammer	Clifford Wolf	2013-07-07	1	-0/+10
*	Removed tests/xsthammer	Clifford Wolf	2013-07-07	13	-1748/+0
*	Fixed vivado related xsthammer bugs	Clifford Wolf	2013-07-05	3	-2/+14
*	Various improvements in xsthammer report generator	Clifford Wolf	2013-07-05	1	-6/+23
*	Added work-around to isim bug in xsthammer report script	Clifford Wolf	2013-07-05	1	-4/+5
*	Added CARRY4 Xilinx cell to xsthammer cell lib	Clifford Wolf	2013-07-05	1	-0/+13
*	Added xsthammer report generator	Clifford Wolf	2013-07-05	4	-13/+170
*	Improved xsthammer quartus support	Clifford Wolf	2013-07-04	2	-1/+484
*	Added Altera Cyclon III cell library to xsthammer	Clifford Wolf	2013-07-04	3	-14/+115
*	Added defparam support to Verilog/AST frontend	Clifford Wolf	2013-07-04	1	-0/+16
*	Added Altera Quartus support to xsthammer	Clifford Wolf	2013-07-03	3	-2/+39
*	Progress in xsthammer	Clifford Wolf	2013-07-03	5	-9/+23
*	Added vivado support to xsthammer	Clifford Wolf	2013-06-26	5	-7/+69
*	Added timout functionality to SAT solver	Clifford Wolf	2013-06-20	1	-2/+2
*	Added "eval" pass	Clifford Wolf	2013-06-19	1	-2/+2
*	Added more stuff to xsthammer, found first xst bug	Clifford Wolf	2013-06-17	2	-2/+175
*	Added ternary op and concat op to xsthammer	Clifford Wolf	2013-06-15	1	-7/+124
*	Added consteval testing to xsthammer and fixed bugs	Clifford Wolf	2013-06-13	1	-2/+7
*	More xsthammer improvements (using xst 14.5 now)	Clifford Wolf	2013-06-13	5	-69/+49
*	Another fix for a bug found using xsthammer	Clifford Wolf	2013-06-12	1	-4/+8
*	Further improved and extended xsthammer	Clifford Wolf	2013-06-11	6	-138/+226
*	More xsthammer improvements	Clifford Wolf	2013-06-10	2	-21/+27
*	Progress xsthammer scripts	Clifford Wolf	2013-06-10	3	-27/+37
*	Progress in xsthammer: working proof for cell models	Clifford Wolf	2013-06-10	3	-34/+51
*	Progress on xsthammer	Clifford Wolf	2013-06-10	5	-0/+268
*	Added first xsthammer scripts	Clifford Wolf	2013-06-10	4	-0/+183
*	Fixed undef behavior in tests/asicworld/code_verilog_tutorial_fsm_full_tb.v	Clifford Wolf	2013-05-24	1	-1/+3
*	Removed test cases that have been moved to yosys-test.	Clifford Wolf	2013-05-17	83	-18963/+0
*	Improved vcdcd.pl (added -d option)	Clifford Wolf	2013-05-14	1	-8/+82
*	Some improvements in vcdcd.pl	Clifford Wolf	2013-05-14	1	-4/+16
*	Fixed a bug in AST frontend for cases with non-blocking assigned variables as...	Clifford Wolf	2013-04-13	1	-0/+19
*	Now only use value from "initial" when no matching "always" block is found	Clifford Wolf	2013-03-31	2	-14/+1
*	Added test cases from 2012 paper on comparison of foss verilog synthesis tools	Clifford Wolf	2013-03-31	6	-0/+111
*	Added k68 (m68k compatible cpu) test case from verilator	Clifford Wolf	2013-03-31	3	-0/+61
*	Renamed hansimem.v test case to mem_arst.v	Clifford Wolf	2013-03-24	1	-1/+0
*	Added hansimem testcase (memory with async reset)	Clifford Wolf	2013-03-24	1	-0/+44
*	Set execute bit on tests/openmsp430/run-synth.sh for real	Clifford Wolf	2013-03-17	1	-0/+0
*	set executable flags to run-synth.sh, added .gitignore	Johann Glaser	2013-03-17	1	-0/+3
*	added ckeck for Icarus Verilog, otherwise the tests are silently stopped	Johann Glaser	2013-03-17	1	-0/+7
*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05	4	-0/+7
*	initial import	Clifford Wolf	2013-01-05	367	-0/+28611