iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Added "yosys -qq" to also quiet warning messages	Clifford Wolf	2014-11-09	1	-1/+1
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*	Added support for task and function args in parentheses	Clifford Wolf	2014-10-27	1	-1/+35
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*	Added "synth" command	Clifford Wolf	2014-09-14	1	-2/+2
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*	Fixed autotest for non-basename arguments	Clifford Wolf	2014-09-06	1	-0/+3
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*	Added tests/various/constmsk_test.ys	Clifford Wolf	2014-09-04	3	-0/+68
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*	Added autotest -e (do not use -noexpr on write_verilog)	Clifford Wolf	2014-08-30	3	-4/+6
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*	Cosmetic changes to FSM tests	Clifford Wolf	2014-08-21	1	-1/+1
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*	Some improvements in FSM mapping and recoding	Clifford Wolf	2014-08-14	1	-1/+2
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*	Added test_verific mode to tests/fsm/generate.py	Clifford Wolf	2014-08-12	1	-7/+17
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*	Added multi-dim memory test (requires iverilog git head)	Clifford Wolf	2014-08-12	1	-0/+11
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*	Fixed FSM mapping for multiple reset-like signals	Clifford Wolf	2014-08-10	1	-7/+22
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*	Some improvements in fsm_opt and fsm_map for FSM with unreachable states	Clifford Wolf	2014-08-09	1	-1/+2
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*	Improved FSM tests	Clifford Wolf	2014-08-08	3	-2/+4
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*	Added FSM test bench	Clifford Wolf	2014-08-08	2	-0/+113
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*	Improved scope resolution of local regs in Verilog+AST frontend	Clifford Wolf	2014-08-05	1	-0/+63
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*	Fixed AST handling of variables declared inside a functions main block	Clifford Wolf	2014-08-05	1	-0/+13
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*	Added "wreduce" to some of the standard test benches	Clifford Wolf	2014-08-03	3	-2/+3
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*	Consolidated hana test benches into fewer files	Clifford Wolf	2014-08-01	175	-1332/+1622
\| \| \| \| \| \| \| \|	for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module ", sprintf("module f%d_",ARGIND)); print; }' \ ${pf}__test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done; ..etc..
*	Added "test_autotb -n <num_iter>" option	Clifford Wolf	2014-08-01	1	-2/+5
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*	Added "make -j{N}" support to "make test"	Clifford Wolf	2014-07-30	6	-12/+29
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*	Renamed "write_autotest" to "test_autotb" and moved to passes/tests/	Clifford Wolf	2014-07-29	1	-1/+1
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*	Added support for "upto" wires to Verilog front- and back-end	Clifford Wolf	2014-07-28	1	-0/+57
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*	Improvements in tests/vloghtb	Clifford Wolf	2014-07-28	2	-11/+17
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*	Added techmap -extern	Clifford Wolf	2014-07-27	2	-1/+28
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*	Added tests/various/.gitignore	Clifford Wolf	2014-07-26	1	-0/+1
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*	Added tests/various/submod_extract.ys	Clifford Wolf	2014-07-26	2	-0/+27
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*	Use "wget -N" in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-26	1	-2/+2
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*	Renamed some of the test cases in tests/simple to avoid name collisions	Clifford Wolf	2014-07-25	15	-30/+30
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*	Use "opt -fine" in test/vloght/test_mapopt.sh	Clifford Wolf	2014-07-21	2	-2/+3
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*	Added "opt_const -fine" and "opt_reduce -fine"	Clifford Wolf	2014-07-21	1	-1/+1
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*	Various improvements in test/vloghtb	Clifford Wolf	2014-07-21	4	-30/+52
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*	Wider range of cell types supported in "share" pass	Clifford Wolf	2014-07-21	2	-19/+52
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*	Added yet another resource sharing test case	Clifford Wolf	2014-07-20	2	-0/+49
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*	Supercell creation for $div/$mod worked all along, fixed test benches	Clifford Wolf	2014-07-20	2	-4/+3
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*	Improved tests/share/generate.py	Clifford Wolf	2014-07-20	1	-2/+12
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*	Small fix in tests/vloghtb/run-test.sh	Clifford Wolf	2014-07-20	1	-0/+2
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*	Added "miter -equiv -flatten"	Clifford Wolf	2014-07-20	1	-2/+1
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*	Added tests/vloghtb/test_share.sh	Clifford Wolf	2014-07-20	5	-1/+57
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*	Added tests/share for testing "share" supercell creation	Clifford Wolf	2014-07-20	3	-0/+58
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*	Added tests/vloghtb	Clifford Wolf	2014-07-20	2	-0/+18
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*	Added SAT-based write-port sharing to memory_share	Clifford Wolf	2014-07-19	1	-0/+25
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*	Fixed bug in memory_share feedback-to-en code	Clifford Wolf	2014-07-19	1	-0/+24
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*	Added translation from read-feedback to en-signals in memory_share	Clifford Wolf	2014-07-18	1	-0/+24
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*	Bugfix in tests/memories/run-test.sh	Clifford Wolf	2014-07-18	1	-2/+2
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*	added tests/memories	Clifford Wolf	2014-07-18	4	-0/+132
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*	Also simulate unmapped memories in "make test"	Clifford Wolf	2014-07-17	1	-1/+1
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*	Implemented dynamic bit-/part-select for memory writes	Clifford Wolf	2014-07-17	1	-1/+40
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*	Added support for bit/part select to mem2reg rewriter	Clifford Wolf	2014-07-17	1	-0/+21
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*	Added support for constant bit- or part-select for memory writes	Clifford Wolf	2014-07-17	1	-0/+20
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*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	1	-2/+13
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