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* | Add testcase for #2010Eddie Hung2020-05-011-0/+10
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* intel_alm: work around a Quartus ICEDan Ravensloft2020-04-231-0/+12
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* tests: read +/xilinx/cell_sim.v before xilinx_dsp testEddie Hung2020-04-221-0/+1
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* test: ice40_dsp test to read +/ice40/cells_sim.v for default paramsEddie Hung2020-04-221-0/+1
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* xilinx: xilinx_dffopt to read cells_sim.v; fix testEddie Hung2020-04-221-13/+22
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* Merge pull request #1949 from YosysHQ/eddie/select_blackboxEddie Hung2020-04-221-0/+28
|\ | | | | select: do not select inside black-/white- boxes unless '=' prefix used
| * tests: update select black/white-box testsEddie Hung2020-04-221-0/+7
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| * select: add test for not selecting inside black/white boxesEddie Hung2020-04-161-0/+21
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* | Merge pull request #1973 from YosysHQ/eddie/fix1966Eddie Hung2020-04-221-1/+3
|\ \ | | | | | | tests: fix various/plugin.sh when PREFIX != /usr/local/share
| * | tests: use `yosys-config --datdir` instead of hard-codedEddie Hung2020-04-221-1/+3
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* | | Merge pull request #1950 from YosysHQ/eddie/design_importEddie Hung2020-04-222-5/+22
|\ \ \ | | | | | | | | design: -import to not count black/white-boxes as candidates for top
| * | | design: add testEddie Hung2020-04-162-5/+22
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* | | Merge pull request #1976 from YosysHQ/dave/fix-sim-constClaire Wolf2020-04-221-0/+13
|\ \ \ | | | | | | | | sim: Fix handling of constant-connected cell inputs at startup
| * | | sim: Fix handling of constant-connected cell inputs at startupDavid Shah2020-04-211-0/+13
| | |/ | |/| | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | hierarchy: Convert positional parameters to named.Marcelina Kościelnicka2020-04-211-0/+23
| | | | | | | | | | | | Fixes #1821.
* | | Merge pull request #1851 from YosysHQ/claire/bitselwriteClaire Wolf2020-04-2113-0/+1224
|\ \ \ | | | | | | | | Improved rewrite code for writing to bit slice
| * | | Remove '-ignore_unknown_cells' option from 'sat'Eddie Hung2020-04-201-6/+6
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| * | | Simplify test case scriptEddie Hung2020-04-201-30/+17
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| * | | Remove ununsed filesEddie Hung2020-04-205-83/+0
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| * | | Modifications of tests as per Eddie's requestdiego2020-04-2015-78/+1237
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| * | | Wrong fixed valuediego2020-04-171-1/+1
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| * | | Adding tests for dynamic part select optimisationdiego2020-04-167-0/+161
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* | | | tests: remove write_ilangEddie Hung2020-04-202-3/+0
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* | | | abc9: add testcase reduced from #1970Eddie Hung2020-04-201-0/+19
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* | | tests: add select -unset testsEddie Hung2020-04-162-0/+20
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* | tests: add design -delete testsEddie Hung2020-04-162-0/+18
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* | Merge pull request #1943 from YosysHQ/dave/fix-1919David Shah2020-04-161-0/+18
|\ \ | | | | | | ast: Fix handling of identifiers in the global scope
| * | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / opt_expr: Fix X and CO outputs for $alu identity-mapping rules.Marcelina Kościelnicka2020-04-161-8/+66
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* Merge pull request #1933 from YosysHQ/eddie/zinit_moreEddie Hung2020-04-151-2/+96
|\ | | | | zinit: handle $__DFFS?E?_[NP][NP][01] too
| * tests: zinit for new typesEddie Hung2020-04-141-2/+96
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* | Merge pull request #1930 from YosysHQ/claire/fix1876Claire Wolf2020-04-151-0/+60
|\ \ | | | | | | Fix handling of ternary with constant condition
| * | tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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* | synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
| | | | | | | | | | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* | opt_expr: Add more $alu optimizations.Marcelina Kościelnicka2020-04-141-4/+52
|/ | | | | | | | | | | Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
| | | | Fixes #1704.
* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-3/+8
|\ | | | | support using previously declared types/localparams/parameters in package
| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-3/+8
| | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
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* | zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
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* | tests: zinit on $adffEddie Hung2020-04-131-19/+18
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* | Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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* | opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-131-0/+28
| | | | | | | | Fixes #1500.
* | Add .gitignore to tests/select/Xiretza2020-04-121-0/+1
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* | Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
|\ \ | | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * | ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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| * | ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| | | | | | | | | | | | LSE/Synplify use case insensitive matching.
| * | ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
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