aboutsummaryrefslogtreecommitdiffstats
path: root/tests/various
Commit message (Collapse)AuthorAgeFilesLines
* fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-182-0/+15
|
* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-143-2/+49
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
| | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* Fix the tests we just brokeClaire Xenia Wolf2021-12-101-4/+4
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* sta: very crude static timing analysis passLofty2021-11-251-0/+81
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* More deadname stuffClaire Xenia Wolf2021-06-092-4/+4
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* abc9: uniquify blackboxes like whiteboxes (#2695)Eddie Hung2021-03-291-1/+56
| | | | | | | | | * abc9_ops: uniquify blackboxes too * abc9_ops: update comment * abc9_ops: allow bypass for param-less blackboxes * Add tests
* blackbox: Include whiteboxed modulesgatecat2021-03-171-0/+14
| | | | Signed-off-by: gatecat <gatecat@ds0.me>
* Add tests for $countbitsMichael Singer2021-02-262-0/+76
|
* Merge pull request #2594 from zachjs/func-arg-widthwhitequark2021-02-234-37/+46
|\ | | | | verilog: fix sizing of constant args for tasks/functions
| * verilog: fix sizing of constant args for tasks/functionsZachary Snow2021-02-214-37/+46
| | | | | | | | | | | | | | | | | | | | | | | | - Simplify synthetic localparams for normal calls to update their width - This step was inadvertently removed alongside `added_mod_children` - Support redeclaration of constant function arguments - `eval_const_function` never correctly handled this, but the issue was not exposed in the existing tests until the recent change to always attempt constant function evaluation when all-const args are used - Check asserts in const_arg_loop and const_func tests - Add coverage for width mismatch error cases
* | verilog: support recursive functions using ternary expressionsZachary Snow2021-02-122-0/+76
|/ | | | | | | This adds a mechanism for marking certain portions of elaboration as occurring within unevaluated ternary branches. To enable elaboration of the overall ternary, this also adds width detection for these unelaborated function calls.
* genrtlil: fix signed port connection codegen failuresZachary Snow2021-02-052-7/+28
| | | | | | | | This fixes binding signed memory reads, signed unary expressions, and signed complex SigSpecs to ports. This also sets `is_signed` for wires generated from signed params when -pwires is used. Though not necessary for any of the current usages, `is_signed` is now appropriately set when the `extendWidth` helper is used.
* verilog: significant block scoping improvementsZachary Snow2021-01-312-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change set contains a number of bug fixes and improvements related to scoping and resolution in generate and procedural blocks. While many of the frontend changes are interdependent, it may be possible bring the techmap changes in under a separate PR. Declarations within unnamed generate blocks previously encountered issues because the data declarations were left un-prefixed, breaking proper scoping. The LRM outlines behavior for generating names for unnamed generate blocks. The original goal was to add this implicit labelling, but doing so exposed a number of issues downstream. Additional testing highlighted other closely related scope resolution issues, which have been fixed. This change also adds support for block item declarations within unnamed blocks in SystemVerilog mode. 1. Unlabled generate blocks are now implicitly named according to the LRM in `label_genblks`, which is invoked at the beginning of module elaboration 2. The Verilog parser no longer wraps explicitly named generate blocks in a synthetic unnamed generate block to avoid creating extra hierarchy levels where they should not exist 3. The techmap phase now allows special control identifiers to be used outside of the topmost scope, which is necessary because such wires and cells often appear in unlabeled generate blocks, which now prefix the declarations within 4. Some techlibs required modifications because they relied on the previous invalid scope resolution behavior 5. `expand_genblock` has been simplified, now only expanding the outermost scope, completely deferring the inspection and elaboration of nested scopes; names are now resolved by looking in the innermost scope and stepping outward 6. Loop variables now always become localparams during unrolling, allowing them to be resolved and shadowed like any other identifier 7. Identifiers in synthetic function call scopes are now prefixed and resolved in largely the same manner as other blocks before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x` after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x` 8. Support identifiers referencing a local generate scope nested more than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`, or `A.B.C.D` 9. Variables can now be declared within unnamed blocks in SystemVerilog mode Addresses the following issues: 656, 2423, 2493
* Allow combination of rand and const modifiersZachary Snow2021-01-212-0/+9
|
* Add plugin.so.dSYM to .gitignoreZachary Snow2021-01-181-0/+1
| | | | | This artifact is automatically generated by the builtin clang on macOS when -g is used.
* Merge pull request #2518 from zachjs/recursionwhitequark2021-01-012-0/+71
|\ | | | | verilog: improved support for recursive functions
| * verilog: improved support for recursive functionsZachary Snow2020-12-312-0/+71
| |
* | sv: complete support for implied task/function port directionsZachary Snow2020-12-312-0/+29
|/
* Fix elaboration of whole memory words used as indicesZachary Snow2020-12-263-0/+48
|
* Fix constants bound to redeclared function argsZachary Snow2020-12-261-0/+10
| | | | | | | | The changes in #2476 ensured that function inputs like `input x;` retained their single-bit size when instantiated with a constant argument and turned into a localparam. That change did not handle the possibility for an input to be redeclared later on with an explicit width, such as `integer x;`.
* Merge pull request #2501 from zachjs/genrtlil-tern-signwhitequark2020-12-231-4/+9
|\ | | | | genrtlil: fix mux2rtlil generated wire signedness
| * genrtlil: fix mux2rtlil generated wire signednessZachary Snow2020-12-221-4/+9
| |
* | Merge pull request #2476 from zachjs/const-arg-widthwhitequark2020-12-231-0/+10
|\ \ | |/ |/| Fix constants bound to single bit arguments (fixes #2383)
| * Fix constants bound to single bit arguments (fixes #2383)Zachary Snow2020-12-221-0/+10
| |
* | Merge pull request #2479 from zachjs/const-arg-hintwhitequark2020-12-221-0/+9
|\ \ | | | | | | Allow constant function calls in constant function arguments
| * | Allow constant function calls in constant function argumentsZachary Snow2020-12-071-0/+9
| |/
* / Sign extend port connections where necessaryZachary Snow2020-12-182-0/+98
|/ | | | | | | | | | | - Signed cell outputs are sign extended when bound to larger wires - Signed connections are sign extended when bound to larger cell inputs - Sign extension is performed in hierarchy and flatten phases - genrtlil indirects signed constants through signed wires - Other phases producing RTLIL may need to be updated to preserve signedness information - Resolves #1418 - Resolves #2265
* Merge pull request #2133 from dh73/nodev_headClaire Xen2020-11-2518-65/+322
|\ | | | | Adding latch tests for shift&mask AST dynamic part-select enhancements
| * Removing trailing whitespacediego2020-06-101-30/+30
| |
| * Adding latch tests for shift&mask AST dynamic part-select enhancementsdiego2020-06-0918-68/+325
| |
* | tests: Centralize test collection and Makefile generationXiretza2020-09-211-19/+3
| |
* | Merge pull request #2352 from zachjs/const-func-localparamclairexen2020-09-011-3/+6
|\ \ | | | | | | Allow localparams in constant functions
| * | Allow localparams in constant functionsZachary Snow2020-08-201-3/+6
| | |
* | | Fix constant args used with function ports split across declarationsZachary Snow2020-08-291-0/+20
|/ /
* | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-201-143/+0
|\ \ | | | | | | Remove passes redundant with opt_dff
| * | peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-071-143/+0
| | |
* | | Merge branch 'const-func-block-var' of https://github.com/zachjs/yosys into ↵Claire Wolf2020-08-182-0/+24
|\ \ \ | | | | | | | | | | | | | | | | | | | | zachjs-const-func-block-var Signed-off-by: Claire Wolf <claire@symbioticeda.com>
| * | | Allow blocks with declarations within constant functionsZachary Snow2020-07-252-0/+24
| | | |
* | | | Merge pull request #2281 from zachjs/const-realclairexen2020-08-181-0/+12
|\ \ \ \ | |_|/ / |/| | | Allow reals as constant function parameters
| * | | Allow reals as constant function parametersZachary Snow2020-07-191-0/+12
| |/ /
* | | Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undefclairexen2020-07-281-0/+35
|\ \ \ | | | | | | | | equiv_induct: Fix up assumption for $equiv cells in -undef mode.
| * | | equiv_induct: Fix up assumption for $equiv cells in -undef mode.Marcelina Kościelnicka2020-07-271-0/+35
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this fix, equiv_induct only assumed that one of the following is true: - defined value of A is equal to defined value of B - A is undefined This lets through valuations where A is defined, B is undefined, and the defined (meaningless) value of B happens to match the defined value of A. Instead, tighten this up to OR of the following: - defined value of A is equal to defined value of B, and B is not undefined - A is undefined
* / / Avoid generating wires for function args which are constantZachary Snow2020-07-242-0/+45
|/ /
* | Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-104-0/+49
| | | | | | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* | Revert PRs #2203 and #2244.whitequark2020-07-094-49/+0
| | | | | | | | | | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* | Add logic param and integer bad syntax testsKamil Rakoczy2020-07-063-0/+21
| | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-0/+28
|\ \ | | | | | | Signed and macro grammar update
| * | Add signed/unsigned testsKamil Rakoczy2020-06-261-0/+28
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-16 10:55:02 +0000