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* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-192-0/+170
* Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
* Updated ABC and some related changesClifford Wolf2014-02-131-2/+1
* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-121-1/+2
* Removed old unused files from tests/Clifford Wolf2014-02-051-63/+0
* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-031-50/+10
* Added autotest.sh -p optionClifford Wolf2014-01-021-3/+8
* Use "abc -dff" in "make test"Clifford Wolf2013-12-311-3/+2
* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-311-1/+1
* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-241-1/+1
* Added modelsim support to autotestClifford Wolf2013-11-241-2/+10
* Moved common techlib files to techlibs/commonClifford Wolf2013-09-152-3/+3
* Added $div and $mod technology mappingClifford Wolf2013-08-091-3/+3
* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-091-2/+2
* Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-141-8/+82
* Some improvements in vcdcd.plClifford Wolf2013-05-141-4/+16
* added more .gitignore files (make test)Clifford Wolf2013-01-051-0/+1
* initial importClifford Wolf2013-01-055-0/+550