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authorClifford Wolf <clifford@clifford.at>2013-09-15 11:52:57 +0200
committerClifford Wolf <clifford@clifford.at>2013-09-15 11:52:57 +0200
commit288ba9618af9c5ba9db1131955c92d59166d120d (patch)
treed65852d388355322a9e7166ba0b0661e24eb220e /tests/tools
parent647c23b7b7e3a72fc64d9b1ad07dacd590865898 (diff)
downloadyosys-288ba9618af9c5ba9db1131955c92d59166d120d.tar.gz
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Moved common techlib files to techlibs/common
Diffstat (limited to 'tests/tools')
-rwxr-xr-xtests/tools/autotest.sh4
-rwxr-xr-xtests/tools/rtlview.sh2
2 files changed, 3 insertions, 3 deletions
diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh
index cb1e3a96d..992c8563e 100755
--- a/tests/tools/autotest.sh
+++ b/tests/tools/autotest.sh
@@ -130,8 +130,8 @@ do
"$toolsdir"/../../yosys -b "verilog $backend_opts" "$@" -o ${bn}_syn${test_count}.v $fn $scriptfiles
compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \
${bn}_tb.v ${bn}_syn${test_count}.v $libs \
- "$toolsdir"/../../techlibs/simlib.v \
- "$toolsdir"/../../techlibs/stdcells_sim.v
+ "$toolsdir"/../../techlibs/common/simlib.v \
+ "$toolsdir"/../../techlibs/common/stdcells_sim.v
if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi
$toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count}
test_count=$(( test_count + 1 ))
diff --git a/tests/tools/rtlview.sh b/tests/tools/rtlview.sh
index 6a4adcae1..61fef802e 100755
--- a/tests/tools/rtlview.sh
+++ b/tests/tools/rtlview.sh
@@ -11,7 +11,7 @@ prjdir="$(dirname $0)/rtlview.tmp"
mkdir -p "$prjdir"
cp "$1" "$prjdir"/schematic.v
-cp "$(dirname $0)"/../../techlibs/blackbox.v "$prjdir"/blackbox.v
+cp "$(dirname $0)"/../../techlibs/common/blackbox.v "$prjdir"/blackbox.v
cd "$prjdir"
if fuser -s ise.out; then