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* Merge branch 'master' of https://github.com/brouhaha/yosysClifford Wolf2016-09-231-1/+6
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| * Add optional SEED=n command line option to Makefile, and -S n command line ↵Eric Smith2016-09-221-1/+6
| | | | | | | | option to test scripts, for deterministic regression tests.
* | Added autotest.sh -IClifford Wolf2016-09-201-16/+19
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* Fix for modules with big interfaces.Kaj Tuomi2016-09-131-2/+2
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* Added "test_autotb -seed" (and "autotest.sh -S")Clifford Wolf2016-08-061-2/+4
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* Fixed autotest.sh handling of `timescaleClifford Wolf2016-07-021-14/+10
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* Improvements and fixes in autotest.sh script and test_autotbClifford Wolf2016-05-201-6/+6
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* Fix for Modelsim transcript line warp issue #164Kaj Tuomi2016-05-191-4/+4
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* Optionally use ${CC} when compiling test utils.Sergey Kvachonok2016-03-251-1/+1
| | | | Default to gcc when not set.
* Switched to Python 3Clifford Wolf2015-08-221-4/+1
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* Another block of spelling fixesLarry Doolittle2015-08-141-1/+1
| | | | Smaller this time
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
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* Some test related fixesClifford Wolf2015-02-121-1/+1
| | | | (incl. removal of three bad test cases)
* Refactoring of memory_bram and xilinx bramsClifford Wolf2015-01-181-0/+2
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* Tiny fix in vcdcd.plClifford Wolf2015-01-131-2/+2
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* Added "synth" commandClifford Wolf2014-09-141-2/+2
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* Fixed autotest for non-basename argumentsClifford Wolf2014-09-061-0/+3
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* Added autotest -e (do not use -noexpr on write_verilog)Clifford Wolf2014-08-301-2/+4
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* Added "wreduce" to some of the standard test benchesClifford Wolf2014-08-031-1/+1
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* Added "test_autotb -n <num_iter>" optionClifford Wolf2014-08-011-2/+5
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* Added "make -j{N}" support to "make test"Clifford Wolf2014-07-302-6/+23
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* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-291-1/+1
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* Added "opt_const -fine" and "opt_reduce -fine"Clifford Wolf2014-07-211-1/+1
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* Also simulate unmapped memories in "make test"Clifford Wolf2014-07-171-1/+1
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* Added note to "make test": use git checkout of iverilogClifford Wolf2014-07-161-2/+11
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* Progress in Verific bindingsClifford Wolf2014-03-171-1/+9
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* Progress in Verific bindingsClifford Wolf2014-03-141-5/+9
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* Added vcd2txt.pl and txt2tikztiming.py (tests/tools/...)Clifford Wolf2014-02-192-0/+170
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* Added frontend (-f) option to autotest.shClifford Wolf2014-02-151-5/+8
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* Updated ABC and some related changesClifford Wolf2014-02-131-2/+1
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* Disabled "abc -dff" in "make test" for now (waiting for scorr bugfix in ABC)Clifford Wolf2014-02-121-1/+2
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* Removed old unused files from tests/Clifford Wolf2014-02-051-63/+0
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* Replaced isim with xsim in tests/tools/autotest.sh, removed xst supportClifford Wolf2014-02-031-50/+10
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* Added autotest.sh -p optionClifford Wolf2014-01-021-3/+8
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* Use "abc -dff" in "make test"Clifford Wolf2013-12-311-3/+2
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* Fixed commented out techmap call in tests/tools/autotest.shClifford Wolf2013-12-311-1/+1
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* Renamed stdcells_sim.v to simcells.v and fixed blackbox.vClifford Wolf2013-11-241-1/+1
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* Added modelsim support to autotestClifford Wolf2013-11-241-2/+10
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* Moved common techlib files to techlibs/commonClifford Wolf2013-09-152-3/+3
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* Added $div and $mod technology mappingClifford Wolf2013-08-091-3/+3
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* Major redesign of expr width/sign detecion (verilog/ast frontend)Clifford Wolf2013-07-091-2/+2
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* Improved vcdcd.pl (added -d option)Clifford Wolf2013-05-141-8/+82
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* Some improvements in vcdcd.plClifford Wolf2013-05-141-4/+16
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* added more .gitignore files (make test)Clifford Wolf2013-01-051-0/+1
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* initial importClifford Wolf2013-01-055-0/+550
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