iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Removed old unused files from tests/	Clifford Wolf	2014-02-05	1	-63/+0
*	Replaced isim with xsim in tests/tools/autotest.sh, removed xst support	Clifford Wolf	2014-02-03	1	-50/+10
*	Added autotest.sh -p option	Clifford Wolf	2014-01-02	1	-3/+8
*	Use "abc -dff" in "make test"	Clifford Wolf	2013-12-31	1	-3/+2
*	Fixed commented out techmap call in tests/tools/autotest.sh	Clifford Wolf	2013-12-31	1	-1/+1
*	Renamed stdcells_sim.v to simcells.v and fixed blackbox.v	Clifford Wolf	2013-11-24	1	-1/+1
*	Added modelsim support to autotest	Clifford Wolf	2013-11-24	1	-2/+10
*	Moved common techlib files to techlibs/common	Clifford Wolf	2013-09-15	2	-3/+3
*	Added $div and $mod technology mapping	Clifford Wolf	2013-08-09	1	-3/+3
*	Major redesign of expr width/sign detecion (verilog/ast frontend)	Clifford Wolf	2013-07-09	1	-2/+2
*	Improved vcdcd.pl (added -d option)	Clifford Wolf	2013-05-14	1	-8/+82
*	Some improvements in vcdcd.pl	Clifford Wolf	2013-05-14	1	-4/+16
*	added more .gitignore files (make test)	Clifford Wolf	2013-01-05	1	-0/+1
*	initial import	Clifford Wolf	2013-01-05	5	-0/+550