iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-1/+8
*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-0/+5
*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	1	-2/+13
*	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	Clifford Wolf	2014-03-11	1	-1/+1
*	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	Clifford Wolf	2014-03-11	1	-1/+1
*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21	1	-4/+4
*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21	7	-0/+214