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* Merge pull request #1422 from YosysHQ/eddie/aigmap_selectClifford Wolf2019-10-031-0/+10
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| * Add quick testEddie Hung2019-09-301-0/+10
* | Extend test with renaming cells with prefix tooEddie Hung2019-10-021-0/+2
* | Add testEddie Hung2019-09-301-0/+16
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* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-2/+12
* Hell let's add the original #1381 testcase tooEddie Hung2019-09-201-3/+22
* Add testcaseEddie Hung2019-09-201-0/+43
* Added extractinv passMarcin Kościelnicki2019-09-191-0/+41
* Add -match-init option to dff2dffs.Marcin Kościelnicki2019-09-111-0/+50
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-0/+98
* improve clkbuf_inhibit propagation upwards through hierarchyMarcin Kościelnicki2019-08-271-5/+33
* Improve tests to check that clkbuf is connected to expectedEddie Hung2019-08-261-6/+21
* Check clkbuf_inhibit=1 is ignored for custom selectionEddie Hung2019-08-231-0/+1
* Add simple clkbufmap testsEddie Hung2019-08-231-0/+52
* tests/techmap/run-test.sh to cope with *.ysEddie Hung2019-08-232-7/+18
* Add testEddie Hung2019-08-203-0/+15
* Added read-enable to memory modelClifford Wolf2015-09-251-1/+8
* Added $meminit support to "memory" commandClifford Wolf2015-02-141-0/+5
* Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interfaceClifford Wolf2014-07-161-2/+13
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
* Use private namespace in mem_simple_4x1_mapClifford Wolf2014-02-211-4/+4
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-217-0/+214