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* tests: Centralize test collection and Makefile generationXiretza2020-09-211-1/+1
* Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.shClifford Wolf2014-03-111-1/+1
* Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)Clifford Wolf2014-03-111-1/+1
* Added tests/techmap/mem_simple_4x1Clifford Wolf2014-02-211-0/+17