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* verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-091-0/+1
| | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation
* Add simple VHDL+PSL exampleClifford Wolf2017-07-281-4/+4
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* Improve SVA tests, add Makefile and scriptsClifford Wolf2017-07-271-0/+13