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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-12-061-5/+11
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| * abc9: Fix breaking of SCCsDavid Shah2019-12-011-0/+6
* | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dffEddie Hung2019-11-271-9/+0
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| * Remove notesEddie Hung2019-11-261-9/+0
* | Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dffEddie Hung2019-11-231-7/+7
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| * \ Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adffEddie Hung2019-11-211-2/+7
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* | | | Add testcase for signal used as part input part outputEddie Hung2019-11-221-0/+5
* | | | Missing endmoduleEddie Hung2019-11-221-0/+1
* | | | Merge branch 'eddie/xaig_dff_adff' into xaig_dffEddie Hung2019-11-211-3/+14
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| * | | Add two testsEddie Hung2019-11-191-0/+12
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* | | Add testEddie Hung2019-11-211-1/+6
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* | Add multi clock testEddie Hung2019-11-201-0/+5
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* Fix issue with part of PI being 1'bxEddie Hung2019-06-201-0/+5
* Add a couple more testsEddie Hung2019-06-121-0/+12
* Rename to #23Eddie Hung2019-05-291-3/+3
* Add abc_test024Eddie Hung2019-05-291-6/+19
* Add abc9_test022Eddie Hung2019-05-281-0/+22
* Remove topo sort no-loop assertion, with testEddie Hung2019-04-241-0/+73
* Fix abc9 with (* keep *) wiresEddie Hung2019-04-231-0/+38
* Uncomment out more testsEddie Hung2019-02-261-25/+39
* Enable two inout testsEddie Hung2019-02-261-16/+14
* Add broken testcasesEddie Hung2019-02-251-0/+46
* Add abc9.v testcase to simple_abc9Eddie Hung2019-02-211-4/+46
* Move tests/techmap/abc9 to simple_abc9Eddie Hung2019-02-201-0/+6